You are not logged in.
I have a couple of questions regarding the CM-MMCX
1. What is the output signal level of the sampling clock from this module?
2. Is the sampling clock output signal of the CM-MMCX phase aligned with the clock that connects to the AD993 on board the WARP3
Last edited by sgv1975 (2017-Jul-27 09:32:21)
Offline
1) I think it's around 1Vp-p
2) All the outputs of the sampling clock buffer (which includes the clocks driven to the AD9963's, FPGA and CM header) have fixed phase relationships. The clocks will not be phase aligned but the inter-clock phases should be static.
Offline