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#1 2018-Jun-27 08:54:54

5g3
Member
Registered: 2018-Jun-14
Posts: 4

accessing sd card with warp v3 board

Hey all,

I am trying to use the spi sd pcore to access the sd card on the warp v3 board.

I understand that the CPLD code needs to be modified (the one below), specifically I need to connect the CPLD GPIO pins to the SPI CS, CLK, and MOSI lines to the sd card.

https://warpproject.org/trac/browser/Ha … order=name

I've added this pcore to my reference design https://warpproject.org/trac/browser/Pl … order=name

In Xilinx Software Development IDE, I add the sd_spi.h, compile the microblaze program, add these lines of code:
    sd_fpga_ctrl_en(SPI_BASE_ADDR);
    status = sd_rw_init(SPI_BASE_ADDR);

But I get an error in CMD0 - no valid response output through the console terminal. So, likely my CPLD modification is wrong, but I'm not sure.

My system.mhs file has the following added:

BEGIN w3_sd_spi
PARAMETER INSTANCE = w3_sd_spi_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x44a00000
PARAMETER C_HIGHADDR = 0x44a0FFFF
BUS_INTERFACE S_AXI = axi4lite_1
PORT S_AXI_ACLK = clk_80MHz
PORT spi_sclk = CPLD_GPIO_0_pin
PORT spi_mosi = CPLD_GPIO_1_pin
PORT spi_miso = CPLD_GPIO_2_pin
PORT spi_cs_n = CPLD_GPIO_3_pin
PORT spi_enable_n = CPLD_GPIO_4_pin
PORT cfg_req_n = CPLD_GPIO_5_pin
PORT cfg_sel = CPLD_GPIO_pin
END

And then, for the cpld code in w3_cpld_sd_config.v,  I commented out the spi_boot instantation and added these lines instead:

    assign sd_mosi = cpld_gpio_1;
    assign sd_sclk = cpld_gpio_0;
    assign sd_cs_n = cpld_gpio_3;
        assign cpld_gpio_2 = spi_miso;

Any suggestions on what I am doing wrong? Any help would be greatly appreciated!

Last edited by 5g3 (2018-Jun-27 11:33:56)

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#2 2018-Jun-27 14:50:06

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4901

Re: accessing sd card with warp v3 board

A few possibilities:

-Check the pin assignments for the new signals in the CPLD design

-Did you recompile the CPLD design with ISE Project Navigator, then re-program the CPLD via JTAG?

-Check the pin assignments for the new signals in the FPGA design

We've used the MHS/UCF below successfully:

system.mhs:

Code:

#Top-level ports
...
# SD SPI
 PORT sd_spi_SCLK = sd_spi_SCLK, DIR = O
 PORT sd_spi_MISO = sd_spi_MISO, DIR = I
 PORT sd_spi_MOSI = sd_spi_MOSI, DIR = O
 PORT sd_spi_CS_N = sd_spi_CS_N, DIR = O
 PORT sd_spi_enable_n = sd_spi_enable_n, DIR = O
 PORT sd_cfg_req_n = sd_cfg_req_n, DIR = O
 PORT sd_cfg_sel = sd_cfg_sel, DIR = O, VEC = [2:0]


#w3_sd_spi instance
BEGIN w3_sd_spi
 PARAMETER INSTANCE = w3_sd_spi_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x43000000
 PARAMETER C_HIGHADDR = 0x43000FFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
 BUS_INTERFACE S_AXI = axi4lite_1
 PORT S_AXI_ACLK = clk_80MHz
 PORT spi_sclk = sd_spi_SCLK
 PORT spi_miso = sd_spi_MISO
 PORT spi_mosi = sd_spi_MOSI
 PORT spi_cs_n = sd_spi_CS_N
 PORT spi_enable_n = sd_spi_enable_n
 PORT cfg_req_n = sd_cfg_req_n
 PORT cfg_sel = sd_cfg_sel
END

FPGA constraints (data/system.ucf):

Code:

#FPGA <-> CPLD signals for accessing SD card
NET sd_spi_SCLK LOC = J25 | IOSTANDARD=LVCMOS25;
NET sd_spi_MISO LOC = N24 | IOSTANDARD=LVCMOS25;
NET sd_spi_MOSI LOC = N23 | IOSTANDARD=LVCMOS25;
NET sd_spi_CS_N LOC = P24 | IOSTANDARD=LVCMOS25;

NET sd_spi_enable_n LOC = R24 | IOSTANDARD=LVCMOS25;
NET sd_cfg_req_n LOC = H25 | IOSTANDARD=LVCMOS25;
NET sd_cfg_sel<0> LOC = L24 | IOSTANDARD=LVCMOS25;
NET sd_cfg_sel<1> LOC = H24 | IOSTANDARD=LVCMOS25;
NET sd_cfg_sel<2> LOC = J24 | IOSTANDARD=LVCMOS25;

Net sd_spi_SCLK TNM_NET = sd_spi_SCLK;
TIMESPEC TS_sd_spi_SCLK = PERIOD sd_spi_SCLK 20 MHz;

CPLD constraints:

Code:

...
NET "fpga_spi_sclk" LOC = "P85" | IOSTANDARD = LVCMOS25; #CPLD_GPIO0 / V6.J25
NET "fpga_spi_miso" LOC = "P86" | IOSTANDARD = LVCMOS25; #CPLD_GPIO1 / V6.N24
NET "fpga_spi_mosi" LOC = "P87" | IOSTANDARD = LVCMOS25; #CPLD_GPIO2 / V6.N23
NET "fpga_spi_cs_n" LOC = "P89" | IOSTANDARD = LVCMOS25; #CPLD_GPIO3 / V6.P24
NET "fpga_spi_enable_n" LOC = "P90" | IOSTANDARD = LVCMOS25 | PULLUP; #CPLD_GPIO4 / V6.R24
NET "fpga_cfg_req_n" LOC = "P82" | IOSTANDARD = LVCMOS25 | PULLUP; #CPLD_GPIO5 / V6.H25

NET "fpga_cfg_sel<0>" LOC = "P81" | IOSTANDARD = LVCMOS25; #CPLD_GPIO6 / V6.L24
NET "fpga_cfg_sel<1>" LOC = "P80" | IOSTANDARD = LVCMOS25; #CPLD_GPIO7 / V6.H24
NET "fpga_cfg_sel<2>" LOC = "P79" | IOSTANDARD = LVCMOS25; #CPLD_GPIO8 / V6.J24

This code comes from an experimental build of the WARPLab Reference Design that supported reconfiguring the FPGA via Ethernet. You're welcome to look at that design (http://warpproject.org/dl/refdes/warpla … Config.zip) but please understand it's old (based on WARPLab 7.3) and completely unsupported (I built it years ago, don't recall exactly how it worked). Despite this, it could be a useful reference for building your own FPGA-SD connections.

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#3 2018-Jun-27 15:49:31

5g3
Member
Registered: 2018-Jun-14
Posts: 4

Re: accessing sd card with warp v3 board

Hey thanks a lot! Additionally, do you happen to have a microblaze example using the sd_spi.h and sd_spi.c libs?

Specifically, where sd_write_block and sd_read_block are used, just to understand them a bit better.

Syntactically, would it be something like this? (assuming that buffer_test and buffer_test_size are valid arguments being passed): 

sd_write_block(SPI_BASE_ADDR,SSPI_REG_SPITX,buffer_test,buffer_test_size);

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#4 2018-Jun-27 16:37:03

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4901

Re: accessing sd card with warp v3 board

The best resource would be the example SD read/write code in that .zip archive (w3_WARPLab_EDK_2RF_v7.3.0_EthSD/SDK_Workspace/w3_WARPLab_v7_AXI_2rf/src/wl_user.c). I implemented the SD interface as a "user command" in WARPLab, to minimize changes relative to the reference design code.

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#5 2018-Jun-27 16:40:43

5g3
Member
Registered: 2018-Jun-14
Posts: 4

Re: accessing sd card with warp v3 board

Ok thanks your help is really appreciated, will give it a go and report back!

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#6 2018-Jul-05 10:17:22

5g3
Member
Registered: 2018-Jun-14
Posts: 4

Re: accessing sd card with warp v3 board

So quick question regarding the CPLD code, it presently doesn't have the functionality that once a .bin is booted from the sd card, the SPI lines are changed to connect directly to the FPGA for SD read/write access?

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#7 2018-Jul-05 10:31:21

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4901

Re: accessing sd card with warp v3 board

So quick question regarding the CPLD code, it presently doesn't have the functionality that once a .bin is booted from the sd card, the SPI lines are changed to connect directly to the FPGA for SD read/write access?

That's correct - the CPLD design we load during manufacturing (source here) only supports FPGA configuration. You can reprogram the CPLD with a custom design with a JTAG cable via the JTAG header on the bottom of the WARP v3 board.

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