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#1 2018-Sep-17 09:55:44

alice_warp
Member
From: Italy
Registered: 2015-Sep-08
Posts: 52

Time constraints not met

Hi,
I changed some things in the Reference Design 802.11.
Unfortunately, I have some trouble about time constraints  (see below). Do you know I can solve them?

Code:

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
* TS_clk_gen_proc_bus_clks_clk_gen_proc_bus | SETUP       |    -9.346ns|    15.596ns|      56|      426415
  _clks_SIG_MMCM0_CLKOUT1 = PERIOD TIMEGRP  | HOLD        |    -0.361ns|            |   20421|     3040307
  "clk_gen_proc_bus_clks_clk_gen_proc_bus_c |             |            |            |        |            
  lks_SIG_MMCM0_CLKOUT1" TS_samp_clk * 2 HI |             |            |            |        |            
  GH 50%                                    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_ETH_A_MAC_v6_emac_v2_2_clk_phy_tx = PE | SETUP       |     3.121ns|     2.243ns|       0|           0
  RIOD TIMEGRP "v6_emac_v2_2_clk_phy_tx" 8  | HOLD        |    -0.656ns|            |     106|       44320
  ns HIGH 50%                               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_axi_sysmon_adc_0_axi_sysmon_adc_0_SYSM | SETUP       |    11.717ns|     1.850ns|       0|           0
  ON_ADC_CORE_I_DCLK_ext_clk = PERIOD TIMEG | HOLD        |    -0.543ns|            |      26|        3775
  RP "axi_sysmon_adc_0_axi_sysmon_adc_0_SYS | MINPERIOD   |    12.500ns|    12.500ns|       0|           0
  MON_ADC_CORE_I_DCLK_ext_clk" TS_clk_gen_p |             |            |            |        |            
  roc_bus_clks_clk_gen_proc_bus_clks_SIG_MM |             |            |            |        |            
  CM0_CLKOUT0 / 2 HIGH 50%                  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RXD<3>" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RXD<2>" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RXD<1>" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RXD<0>" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RXD<3>" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RXD<2>" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RXD<1>" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RX_CTL" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RXD<0>" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RX_CTL" OFFSET = IN 1.2 | SETUP       |    -0.405ns|     1.605ns|       1|         405
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.144ns|            |       0|           0
  _RXC" "FALLING"                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RXD<3>" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RXD<2>" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RX_CTL" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RXD<1>" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RXD<0>" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_A_RGMII_RX_CTL" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_A_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RXD<3>" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RXD<2>" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RXD<0>" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* COMP "ETH_B_RGMII_RXD<1>" OFFSET = IN 1.2 | SETUP       |    -0.404ns|     1.604ns|       1|         404
   ns VALID 2.4 ns BEFORE COMP "ETH_B_RGMII | HOLD        |     2.142ns|            |       0|           0
  _RXC" "RISING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_clk_gen_async_clks_clk_gen_async_clks_ | SETUP       |     2.243ns|     2.757ns|       0|           0
  SIG_MMCM1_CLKOUT1 = PERIOD TIMEGRP "clk_g | HOLD        |    -0.361ns|            |     197|       27961
  en_async_clks_clk_gen_async_clks_SIG_MMCM | MINPERIOD   |     1.775ns|     3.225ns|       0|           0
  1_CLKOUT1" TS_osc200_p HIGH 50%           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_ETH_A_MAC_v6_emac_v2_2_clk_phy_rx = PE | SETUP       |     6.634ns|     1.366ns|       0|           0
  RIOD TIMEGRP "v6_emac_v2_2_clk_phy_rx" 8  | HOLD        |    -0.361ns|            |     264|       42506
  ns HIGH 50%                               | MINPERIOD   |     6.148ns|     1.852ns|       0|           0
----------------------------------------------------------------------------------------------------------
* TS_DDR3_SODIMM_clk_rsync = PERIOD TIMEGRP | SETUP       |     2.796ns|     0.978ns|       0|           0
   "TNM_DDR3_SODIMM_clk_rsync" 6.25 ns HIGH | HOLD        |    -0.360ns|            |    1548|      359652
   50%                                      | MINLOWPULSE |     4.610ns|     1.640ns|       0|           0
----------------------------------------------------------------------------------------------------------
* TS_ETH_A_MAC_AXI4LITE_CLK_2_GTX_CLK = MAX | SETUP       |     6.589ns|     1.411ns|       0|           0
  DELAY FROM TIMEGRP "axi4lite_clk" TO TIME | HOLD        |    -0.247ns|            |       2|         494
  GRP "clk_gtx" 8 ns DATAPATHONLY           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_ETH_A_MAC_AXI4LITECLKS_2_TX_MAC_ACLK = | SETUP       |     6.589ns|     1.411ns|       0|           0
   MAXDELAY FROM TIMEGRP "axi4lite_clk" TO  | HOLD        |    -0.247ns|            |       2|         494
  TIMEGRP "phy_clk_tx" 8 ns DATAPATHONLY    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_clk_gen_proc_bus_clks_clk_gen_proc_bus | SETUP       |     4.739ns|     3.022ns|       0|           0
  _clks_SIG_MMCM0_CLKOUT0 = PERIOD TIMEGRP  | HOLD        |    -0.163ns|            |      78|        9169
  "clk_gen_proc_bus_clks_clk_gen_proc_bus_c | MINLOWPULSE |     6.500ns|     6.000ns|       0|           0
  lks_SIG_MMCM0_CLKOUT0" TS_samp_clk HIGH 5 |             |            |            |        |            
  0%                                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TIMEGRP "RFA_AD_TRXD_group" OFFSET = IN 0 | SETUP       |     0.594ns|     0.106ns|       0|           0
  .7 ns VALID 22 ns BEFORE COMP "RFA_AD_TRX | HOLD        |    20.999ns|            |       0|           0
  CLK" "FALLING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TIMEGRP "RFB_AD_TRXD_group" OFFSET = IN 0 | SETUP       |     0.594ns|     0.106ns|       0|           0
  .7 ns VALID 22 ns BEFORE COMP "RFB_AD_TRX | HOLD        |    20.999ns|            |       0|           0
  CLK" "FALLING"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TIMEGRP "RFB_AD_TRXD_group" OFFSET = IN 0 | SETUP       |     0.595ns|     0.105ns|       0|           0
  .7 ns VALID 22 ns BEFORE COMP "RFB_AD_TRX | HOLD        |    20.997ns|            |       0|           0
  CLK" "RISING"                             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TIMEGRP "RFA_AD_TRXD_group" OFFSET = IN 0 | SETUP       |     0.595ns|     0.105ns|       0|           0
  .7 ns VALID 22 ns BEFORE COMP "RFA_AD_TRX | HOLD        |    20.997ns|            |       0|           0
  CLK" "RISING"                             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_async_rx_samp_clks_IN = MAXDELAY FROM  | SETUP       |     1.389ns|     0.611ns|       0|           0
  TIMEGRP "AD_TRXCLK_IDDRS" TO TIMEGRP "AD_ | HOLD        |     0.125ns|            |       0|           0
  SYSCLK_FFS" 2 ns DATAPATHONLY             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_ref_clk = PERIOD TIMEGRP "re | MINPERIOD   |     1.775ns|     3.225ns|       0|           0
  f_clk" 5 ns HIGH 50%                      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clock_generator_MPMC_Clocks_clock_gene | MINPERIOD   |     1.792ns|     1.333ns|       0|           0
  rator_MPMC_Clocks_SIG_MMCM0_CLKOUT0 = PER |             |            |            |        |            
  IOD TIMEGRP "clock_generator_MPMC_Clocks_ |             |            |            |        |            
  clock_generator_MPMC_Clocks_SIG_MMCM0_CLK |             |            |            |        |            
  OUT0" TS_clk_gen_proc_bus_clks_clk_gen_pr |             |            |            |        |            
  oc_bus_clks_SIG_MMCM0_CLKOUT0 * 4 HIGH 50 |             |            |            |        |            
  %                                         |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_RFB_AD_TRXCLK = PERIOD TIMEGRP "TNM_RF | MINPERIOD   |     1.811ns|     1.314ns|       0|           0
  B_AD_TRXCLK" TS_samp_clk * 4 HIGH 50%     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_RFA_AD_TRXCLK = PERIOD TIMEGRP "TNM_RF | MINPERIOD   |     1.811ns|     1.314ns|       0|           0
  A_AD_TRXCLK" TS_samp_clk * 4 HIGH 50%     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_osc200_p = PERIOD TIMEGRP "osc200_p" 2 | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
  00 MHz HIGH 50%                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_host_clk = PERIOD TIMEGRP "h | MINPERIOD   |     3.043ns|     3.207ns|       0|           0
  ost" 6.25 ns HIGH 50%                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_pll_refclk = PERIOD TIMEGRP "pll_refcl | SETUP       |     4.108ns|     0.892ns|       0|           0
  k" 200 MHz HIGH 50%                       | HOLD        |     0.075ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_AXI4LITE_CLK_2_REF_CLK = MAX | SETUP       |     4.186ns|     0.814ns|       0|           0
  DELAY FROM TIMEGRP "axi4lite_clk" TO TIME | HOLD        |     0.249ns|            |       0|           0
  GRP "clk_ref_clk" 5 ns DATAPATHONLY       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_samp_clk = PERIOD TIMEGRP "samp_clk" 8 | MINLOWPULSE |     6.500ns|     6.000ns|       0|           0
  0 MHz HIGH 50%                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_gen_proc_bus_clks_clk_gen_proc_bus | SETUP       |     5.265ns|     7.880ns|       0|           0
  _clks_SIG_MMCM0_CLKOUT3 = PERIOD TIMEGRP  | HOLD        |     0.034ns|            |       0|           0
  "clk_gen_proc_bus_clks_clk_gen_proc_bus_c |             |            |            |        |            
  lks_SIG_MMCM0_CLKOUT3" TS_samp_clk * 0.25 |             |            |            |        |            
   PHASE 12.5 ns HIGH 50%                   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_gen_proc_bus_clks_clk_gen_proc_bus | SETUP       |     5.270ns|     7.840ns|       0|           0
  _clks_SIG_MMCM0_CLKOUT2 = PERIOD TIMEGRP  | HOLD        |     0.011ns|            |       0|           0
  "clk_gen_proc_bus_clks_clk_gen_proc_bus_c |             |            |            |        |            
  lks_SIG_MMCM0_CLKOUT2" TS_samp_clk * 0.25 |             |            |            |        |            
   HIGH 50%                                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_DDR3_SODIMM_clk_rsync_rise_to_fall = M | SETUP       |     5.543ns|     0.707ns|       0|           0
  AXDELAY FROM TIMEGRP "TG_DDR3_SODIMM_clk_ | HOLD        |     0.106ns|            |       0|           0
  rsync_rise" TO TIMEGRP "TG_DDR3_SODIMM_cl |             |            |            |        |            
  k_rsync_fall" 6.25 ns                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_TX_MAC_ACLK_2_AXI4LITECLKS = | SETUP       |     5.562ns|     0.688ns|       0|           0
   MAXDELAY FROM TIMEGRP "phy_clk_tx" TO TI | HOLD        |     0.022ns|            |       0|           0
  MEGRP "axi4lite_clk" 6.25 ns DATAPATHONLY |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_REF_CLK_2_AXI4LITE_CLK = MAX | SETUP       |     5.849ns|     0.401ns|       0|           0
  DELAY FROM TIMEGRP "clk_ref_clk" TO TIMEG | HOLD        |     0.075ns|            |       0|           0
  RP "axi4lite_clk" 6.25 ns DATAPATHONLY    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_RX_MAC_ACLK_2_AXI4LITECLKS = | MAXDELAY    |     5.893ns|     0.357ns|       0|           0
   MAXDELAY FROM TIMEGRP "phy_clk_rx" TO TI | HOLD        |     0.022ns|            |       0|           0
  MEGRP "axi4lite_clk" 6.25 ns DATAPATHONLY |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_GTX_CLK_2_AXI4LITE_CLK = MAX | SETUP       |     5.910ns|     0.340ns|       0|           0
  DELAY FROM TIMEGRP "clk_gtx" TO TIMEGRP " | HOLD        |     0.022ns|            |       0|           0
  axi4lite_clk" 6.25 ns DATAPATHONLY        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_v6_emac_v2_2_clk_ref_gtx = P | MINHIGHPULSE|     6.110ns|     1.890ns|       0|           0
  ERIOD TIMEGRP "v6_emac_v2_2_clk_ref_gtx"  |             |            |            |        |            
  8 ns HIGH 50%                             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_gen_async_clks_clk_gen_async_clks_ | SETUP       |     6.424ns|     1.576ns|       0|           0
  SIG_MMCM1_CLKOUT0 = PERIOD TIMEGRP "clk_g | HOLD        |     0.041ns|            |       0|           0
  en_async_clks_clk_gen_async_clks_SIG_MMCM | MINHIGHPULSE|     6.110ns|     1.890ns|       0|           0
  1_CLKOUT0" TS_osc200_p * 0.625 HIGH 50%   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_GTX_CLK_2_RX_MAC_ACLK = MAXD | SETUP       |     6.669ns|     1.331ns|       0|           0
  ELAY FROM TIMEGRP "clk_gtx" TO TIMEGRP "p | HOLD        |     0.211ns|            |       0|           0
  hy_clk_rx" 8 ns DATAPATHONLY              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_AXI4LITECLKS_2_RX_MAC_ACLK = | SETUP       |     6.840ns|     1.160ns|       0|           0
   MAXDELAY FROM TIMEGRP "axi4lite_clk" TO  | HOLD        |     0.022ns|            |       0|           0
  TIMEGRP "phy_clk_rx" 8 ns DATAPATHONLY    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_DDR3_SODIMM_MC_PHY_INIT_SEL = MAXDELAY | SETUP       |    11.495ns|     1.005ns|       0|           0
   FROM TIMEGRP "TNM_DDR3_SODIMM_PHY_INIT_S | HOLD        |     0.015ns|            |       0|           0
  EL" TO TIMEGRP "FFS" 12.5 ns              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_rx_phy_T8 = MAXDELAY FROM TIMEGRP "TNM | SETUP       |    46.647ns|     3.353ns|       0|           0
  _rx_phy_CE8" TO TIMEGRP "TNM_rx_phy_CE8"  | HOLD        |     0.001ns|            |       0|           0
  20 MHz                                    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_AXISTREAMCLKS_2_TX_MAC_ACLK  | N/A         |         N/A|         N/A|     N/A|         N/A
  = MAXDELAY FROM TIMEGRP "axistream_clk" T |             |            |            |        |            
  O TIMEGRP "phy_clk_tx" 8 ns DATAPATHONLY  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_RX_MAC_ACLK_2_AXI4LITECLKS = | N/A         |         N/A|         N/A|     N/A|         N/A
   MAXDELAY FROM TIMEGRP "phy_clk_rx" TO TI |             |            |            |        |            
  MEGRP "axi4lite_clk" 6.25 ns DATAPATHONLY |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_TX_MAC_ACLK_2_AXISTREAMCLKS  | N/A         |         N/A|         N/A|     N/A|         N/A
  = MAXDELAY FROM TIMEGRP "phy_clk_tx" TO T |             |            |            |        |            
  IMEGRP "axistream_clk" 6.25 ns DATAPATHON |             |            |            |        |            
  LY                                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_AXI4LITECLKS_2_TX_MAC_ACLK = | N/A         |         N/A|         N/A|     N/A|         N/A
   MAXDELAY FROM TIMEGRP "axi4lite_clk" TO  |             |            |            |        |            
  TIMEGRP "phy_clk_tx" 8 ns DATAPATHONLY    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_mpmc_320MHz_clk_rd_base = PERIOD T | N/A         |         N/A|         N/A|     N/A|         N/A
  IMEGRP "clk_mpmc_320MHz_clk_rd_base" TS_c |             |            |            |        |            
  lk_gen_proc_bus_clks_clk_gen_proc_bus_clk |             |            |            |        |            
  s_SIG_MMCM0_CLKOUT0 * 4 HIGH 50%          |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_sync_mb_high_intc_path" TIG      | SETUP       |         N/A|     2.097ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_intr_sync_p1_mb_high_intc_path"  | SETUP       |         N/A|    -0.200ns|     N/A|           0
  TIG                                       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_DDR3_SODIMM_IODELAY_CTRL_RDY | SETUP       |         N/A|     0.723ns|     N/A|           0
  _O_SYNCH_path" TIG                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_DDR3_SODIMM_IODELAY_CTRL_RST | SETUP       |         N/A|     0.723ns|     N/A|           0
  _SYNCH_path" TIG                          |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_mb_high_Reset_path" TIG      | SETUP       |         N/A|     0.541ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_mb_high_Interrupt_path" TIG  | SETUP       |         N/A|     0.357ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_mb_low_Reset_path" TIG       | SETUP       |         N/A|     0.541ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_mb_high_axi_periph_reset_resync_ | MAXDELAY    |         N/A|     1.321ns|     N/A|           0
  path" TIG                                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_mb_low_axi_periph_reset_resync_p | MAXDELAY    |         N/A|     1.321ns|     N/A|           0
  ath" TIG                                  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_mb_shared_axi_reset_resync_path" | MAXDELAY    |         N/A|     1.321ns|     N/A|           0
   TIG                                      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_mb_high_ilmb_POR_FF_I_path"  | SETUP       |         N/A|     0.915ns|     N/A|           0
  TIG                                       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_mb_high_dlmb_POR_FF_I_path"  | SETUP       |         N/A|     0.915ns|     N/A|           0
  TIG                                       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_mb_low_dlmb_POR_FF_I_path" T | SETUP       |         N/A|     0.915ns|     N/A|           0
  IG                                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_mb_low_ilmb_POR_FF_I_path" T | SETUP       |         N/A|     0.915ns|     N/A|           0
  IG                                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_AXISTREAMCLKS_2_RX_MAC_ACLK  | N/A         |         N/A|         N/A|     N/A|         N/A
  = MAXDELAY FROM TIMEGRP "axistream_clk" T |             |            |            |        |            
  O TIMEGRP "phy_clk_rx" 8 ns DATAPATHONLY  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_RX_MAC_ACLK_2_AXISTREAMCLKS  | N/A         |         N/A|         N/A|     N/A|         N/A
  = MAXDELAY FROM TIMEGRP "phy_clk_rx" TO T |             |            |            |        |            
  IMEGRP "axistream_clk" 6.25 ns DATAPATHON |             |            |            |        |            
  LY                                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_AXI4LITECLKS_2_RX_MAC_ACLK = | N/A         |         N/A|         N/A|     N/A|         N/A
   MAXDELAY FROM TIMEGRP "axi4lite_clk" TO  |             |            |            |        |            
  TIMEGRP "phy_clk_rx" 8 ns DATAPATHONLY    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_RX_MAC_ACLK_2_GTX_CLK = MAXD | N/A         |         N/A|         N/A|     N/A|         N/A
  ELAY FROM TIMEGRP "phy_clk_rx" TO TIMEGRP |             |            |            |        |            
   "clk_gtx" 8 ns DATAPATHONLY              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_GTX_CLK_2_RX_MAC_ACLK = MAXD | N/A         |         N/A|         N/A|     N/A|         N/A
  ELAY FROM TIMEGRP "clk_gtx" TO TIMEGRP "p |             |            |            |        |            
  hy_clk_rx" 8 ns DATAPATHONLY              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_AXISTREAMCLKS_2_REF_CLK = MA | N/A         |         N/A|         N/A|     N/A|         N/A
  XDELAY FROM TIMEGRP "axistream_clk" TO TI |             |            |            |        |            
  MEGRP "clk_ref_clk" 5 ns DATAPATHONLY     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_REF_CLK_2_AXISTREAMCLKS = MA | N/A         |         N/A|         N/A|     N/A|         N/A
  XDELAY FROM TIMEGRP "clk_ref_clk" TO TIME |             |            |            |        |            
  GRP "axistream_clk" 6.25 ns DATAPATHONLY  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_AXI4LITE_CLK_2_REF_CLK = MAX | N/A         |         N/A|         N/A|     N/A|         N/A
  DELAY FROM TIMEGRP "axi4lite_clk" TO TIME |             |            |            |        |            
  GRP "clk_ref_clk" 5 ns DATAPATHONLY       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_REF_CLK_2_AXI4LITE_CLK = MAX | N/A         |         N/A|         N/A|     N/A|         N/A
  DELAY FROM TIMEGRP "clk_ref_clk" TO TIMEG |             |            |            |        |            
  RP "axi4lite_clk" 6.25 ns DATAPATHONLY    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_TX_MAC_ACLK_2_RX_MAC_ACLK =  | N/A         |         N/A|         N/A|     N/A|         N/A
  MAXDELAY FROM TIMEGRP "phy_clk_tx" TO TIM |             |            |            |        |            
  EGRP "phy_clk_rx" 8 ns DATAPATHONLY       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_RX_MAC_ACLK_2_TX_MAC_ACLK =  | N/A         |         N/A|         N/A|     N/A|         N/A
  MAXDELAY FROM TIMEGRP "phy_clk_rx" TO TIM |             |            |            |        |            
  EGRP "phy_clk_tx" 8 ns DATAPATHONLY       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_AXISTREAMCLKS_2_RX_MAC_ACLK  | N/A         |         N/A|         N/A|     N/A|         N/A
  = MAXDELAY FROM TIMEGRP "axistream_clk" T |             |            |            |        |            
  O TIMEGRP "phy_clk_rx" 8 ns DATAPATHONLY  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_RX_MAC_ACLK_2_AXISTREAMCLKS  | N/A         |         N/A|         N/A|     N/A|         N/A
  = MAXDELAY FROM TIMEGRP "phy_clk_rx" TO T |             |            |            |        |            
  IMEGRP "axistream_clk" 6.25 ns DATAPATHON |             |            |            |        |            
  LY                                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_AXISTREAMCLKS_2_TX_MAC_ACLK  | N/A         |         N/A|         N/A|     N/A|         N/A
  = MAXDELAY FROM TIMEGRP "axistream_clk" T |             |            |            |        |            
  O TIMEGRP "phy_clk_tx" 8 ns DATAPATHONLY  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_TX_MAC_ACLK_2_AXISTREAMCLKS  | N/A         |         N/A|         N/A|     N/A|         N/A
  = MAXDELAY FROM TIMEGRP "phy_clk_tx" TO T |             |            |            |        |            
  IMEGRP "axistream_clk" 6.25 ns DATAPATHON |             |            |            |        |            
  LY                                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_GTX_CLK_2_AXI4LITE_CLK = MAX | N/A         |         N/A|         N/A|     N/A|         N/A
  DELAY FROM TIMEGRP "clk_gtx" TO TIMEGRP " |             |            |            |        |            
  axi4lite_clk" 6.25 ns DATAPATHONLY        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_AXISTREAMCLKS_2_GTX_CLK = MA | N/A         |         N/A|         N/A|     N/A|         N/A
  XDELAY FROM TIMEGRP "axistream_clk" TO TI |             |            |            |        |            
  MEGRP "clk_gtx" 8 ns DATAPATHONLY         |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_GTX_CLK_2_AXISTREAMCLKS = MA | N/A         |         N/A|         N/A|     N/A|         N/A
  XDELAY FROM TIMEGRP "clk_gtx" TO TIMEGRP  |             |            |            |        |            
  "axistream_clk" 6.25 ns DATAPATHONLY      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_AXI4LITE_CLK_2_GTX_CLK = MAX | N/A         |         N/A|         N/A|     N/A|         N/A
  DELAY FROM TIMEGRP "axi4lite_clk" TO TIME |             |            |            |        |            
  GRP "clk_gtx" 8 ns DATAPATHONLY           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_RX_MAC_ACLK_2_TX_MAC_ACLK =  | N/A         |         N/A|         N/A|     N/A|         N/A
  MAXDELAY FROM TIMEGRP "phy_clk_rx" TO TIM |             |            |            |        |            
  EGRP "phy_clk_tx" 8 ns DATAPATHONLY       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_TX_MAC_ACLK_2_RX_MAC_ACLK =  | N/A         |         N/A|         N/A|     N/A|         N/A
  MAXDELAY FROM TIMEGRP "phy_clk_tx" TO TIM |             |            |            |        |            
  EGRP "phy_clk_rx" 8 ns DATAPATHONLY       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_RX_MAC_ACLK_2_GTX_CLK = MAXD | N/A         |         N/A|         N/A|     N/A|         N/A
  ELAY FROM TIMEGRP "phy_clk_rx" TO TIMEGRP |             |            |            |        |            
   "clk_gtx" 8 ns DATAPATHONLY              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_AXISTREAMCLKS_2_REF_CLK = MA | N/A         |         N/A|         N/A|     N/A|         N/A
  XDELAY FROM TIMEGRP "axistream_clk" TO TI |             |            |            |        |            
  MEGRP "clk_ref_clk" 5 ns DATAPATHONLY     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_A_MAC_REF_CLK_2_AXISTREAMCLKS = MA | N/A         |         N/A|         N/A|     N/A|         N/A
  XDELAY FROM TIMEGRP "clk_ref_clk" TO TIME |             |            |            |        |            
  GRP "axistream_clk" 6.25 ns DATAPATHONLY  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_RFA_TRX_TO_20M = MAXDELAY FROM TIMEGRP | N/A         |         N/A|         N/A|     N/A|         N/A
   "TNM_RFA_AD_TRXCLK" TO TIMEGRP "TNM_clk_ |             |            |            |        |            
  20MHz" 40 ns                              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_RFB_TRX_TO_20M = MAXDELAY FROM TIMEGRP | N/A         |         N/A|         N/A|     N/A|         N/A
   "TNM_RFB_AD_TRXCLK" TO TIMEGRP "TNM_clk_ |             |            |            |        |            
  20MHz" 40 ns                              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_async_rx_samp_clks_OUT = MAXDELAY FROM | N/A         |         N/A|         N/A|     N/A|         N/A
   TIMEGRP "AD_SYSCLK_FFS" TO TIMEGRP "AD_T |             |            |            |        |            
  RXCLK_IDDRS" 2 ns DATAPATHONLY            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_GTX_CLK_2_AXISTREAMCLKS = MA | N/A         |         N/A|         N/A|     N/A|         N/A
  XDELAY FROM TIMEGRP "clk_gtx" TO TIMEGRP  |             |            |            |        |            
  "axistream_clk" 6.25 ns DATAPATHONLY      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_AXISTREAMCLKS_2_GTX_CLK = MA | N/A         |         N/A|         N/A|     N/A|         N/A
  XDELAY FROM TIMEGRP "axistream_clk" TO TI |             |            |            |        |            
  MEGRP "clk_gtx" 8 ns DATAPATHONLY         |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ETH_B_MAC_TX_MAC_ACLK_2_AXI4LITECLKS = | N/A         |         N/A|         N/A|     N/A|         N/A
   MAXDELAY FROM TIMEGRP "phy_clk_tx" TO TI |             |            |            |        |            
  MEGRP "axi4lite_clk" 6.25 ns DATAPATHONLY |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_samp_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths
Analyzed       |
|           Constraint          | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    |
Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|TS_samp_clk                    |     12.500ns|      6.000ns|     31.192ns|            0|        20581|           
0|1838175782803840|
| TS_RFA_AD_TRXCLK              |      3.125ns|      1.314ns|          N/A|            0|            0|            0|   
        0|
| TS_RFB_AD_TRXCLK              |      3.125ns|      1.314ns|          N/A|            0|            0|            0|   
        0|
| TS_clk_gen_proc_bus_clks_clk_g|     50.000ns|      7.880ns|          N/A|            0|            0|            4|   
        0|
| en_proc_bus_clks_SIG_MMCM0_CLK|             |             |             |             |             |             |   
         |
| OUT3                          |             |             |             |             |             |             |   
         |
| TS_clk_gen_proc_bus_clks_clk_g|      6.250ns|     15.596ns|          N/A|        20477|            0|1838175782798162|
           0|
| en_proc_bus_clks_SIG_MMCM0_CLK|             |             |             |             |             |             |   
         |
| OUT1                          |             |             |             |             |             |             |   
         |
| TS_clk_gen_proc_bus_clks_clk_g|     12.500ns|      6.000ns|      6.250ns|           78|           26|         5465|   
       76|
| en_proc_bus_clks_SIG_MMCM0_CLK|             |             |             |             |             |             |   
         |
| OUT0                          |             |             |             |             |             |             |   
         |
|  TS_clk_mpmc_320MHz_clk_rd_bas|      3.125ns|          N/A|          N/A|            0|            0|            0|   
        0|
|  e                            |             |             |             |             |             |             |   
         |
|  TS_clock_generator_MPMC_Clock|      3.125ns|      1.333ns|          N/A|            0|            0|            0|   
        0|
|  s_clock_generator_MPMC_Clocks|             |             |             |             |             |             |   
         |
|  _SIG_MMCM0_CLKOUT0           |             |             |             |             |             |             |   
         |
|  TS_axi_sysmon_adc_0_axi_sysmo|     25.000ns|     12.500ns|          N/A|           26|            0|           76|   
        0|
|  n_adc_0_SYSMON_ADC_CORE_I_DCL|             |             |             |             |             |             |   
         |
|  K_ext_clk                    |             |             |             |             |             |             |   
         |
| TS_clk_gen_proc_bus_clks_clk_g|     50.000ns|      7.840ns|          N/A|            0|            0|          133|   
        0|
| en_proc_bus_clks_SIG_MMCM0_CLK|             |             |             |             |             |             |   
         |
| OUT2                          |             |             |             |             |             |             |   
         |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+

Derived Constraints for TS_osc200_p
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths
Analyzed       |
|           Constraint          | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    |
Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|TS_osc200_p                    |      5.000ns|      2.800ns|      3.225ns|            0|          197|            0|   
     9790|
| TS_clk_gen_async_clks_clk_gen_|      5.000ns|      3.225ns|          N/A|          197|            0|         9238|   
        0|
| async_clks_SIG_MMCM1_CLKOUT1  |             |             |             |             |             |             |   
         |
| TS_clk_gen_async_clks_clk_gen_|      8.000ns|      1.890ns|          N/A|            0|            0|          552|   
        0|
| async_clks_SIG_MMCM1_CLKOUT0  |             |             |             |             |             |             |   
         |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+

29 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.

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#2 2018-Sep-18 09:08:15

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5005

Re: Time constraints not met

Those timing results indicate the new design has many paths which cannot achieve 160MHz timing. The "Worst Case Slack" gives timing margin - a positive slack indicates timing was achieved, negative slack means at least one path was too long. In your case the longest path was 9.34nsec longer than allowed - this is a huge value given the 6.25nsec clock period. The "Timing Errors" count the number of paths that failed to meet timing; 20k errors is a lot.

Altogether it seems your modifications added significant complexity to the FPGA design, including many combinational paths which cannot run at 160MHz. You will need to modify your new logic to have better timing performance. The Xilinx Timing Analyzer tool (part of ISE) can help identify which paths failed timing.

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