You are not logged in.
Hello! I plan to use the fmc_bb_4da module to acquire and output the user data that they are sent to AD9963 ADCs/DACs for Wireless TX,In my experiment,I choose IBSS mode for WARP V3 board and connect computer with WARP V3 board in a same WLAN. then I connect fmc_bb-4da module with oscilloscope. I sent user data from my computer to WARP board for wireless emit by Ethernet.I use Wireshark application in my computer successfully capture the wireless data package but there is no data output on the oscilloscope.
That's what I did：
After adding fmc_bb_4da IP core and modify MHS and UCF file in project ,In XPS System Assembly View Ports windows, I connect the Port FMC_bb_4da::user_DAC_x to the ad_bridge_onboard::ad_RFX_TXD Port and remain the connection between the ad_bridge_onboard core and AD9963 ADCs/DACs in the XPS Ports interface (I need remain the wireless function for further development).
because the fmc_bb_4da core needs clock inputs,so I connect the fmc_bb_4da::sys_samp_clk port to clk_gen_proc_bus_clk::CLKOUT1 port to synchronous with and valid for registering the user-supplied data signals (the w3_ad_bridge core clock input is also connect to the CLKOUT1 port),the sys_samp_clk_90 port is connected to CLKOUT2,I configure the CLKOUT1 and CLKOUT2 have the same parameters except a 90 degree Phase shift.
I think it maybe the clock problem that causes no output on the oscilloscope,is that? thank you!
Last edited by chenhongwei (2019-Mar-25 01:33:39)
Offline
We have not attempted this customization to the 802.11 Ref Design, so I cannot provide specific instructions. However a few issues I observe in the changes you describe:
-The max sampling rate of the AD9116 DACs is 125MHz. The clk_gen_proc_bus_clk::CLKOUT1 port (net clk_160MHz in system.mhs) is a 160MHz clock.
-The Tx PHY outputs samples at 10, 20 or 40MSps depending on the configured bandwidth (default is 20MSps). These samples are always synchronous to the 160MHz clock and are qualified by the RF_AD_samp_ce clock-enable signal.
-The fmc_bb_4da core requires sys_samp_clk/sys_samp_clk_90 to have the same frequency as the sampling rate. You will need to add logic to interface the PHY I/Q output ports (160MHz with 10/20/40MHz clock enable) to the fmc_bb_4da I/Q inputs (same rate as sys_samp_clk input).
Offline
thank you for your reply!
Offline
Hello! I have thought about your suggestion carefully several days.
My understanding about your suggesion is as follows： I need to design a IP core like the ad_bridge_onboard IP core to interface the TX PHY to the fmc_bb_4da. becuase The max sampling rate of the AD9116 DACs is 125MHz while the PHY I/Q output ports outputs samples bandwith at 10/20/40MHz,160Mhz clock.
Offline
Yes, you will need to design custom logic to connect these interfaces.
Offline
Hello! murphpo,I'm sorry to bother you.I still have some points unable to understand in the Reference design about the samples/data rate.
1.why the PHY I/Q outputs' default is 20Msps while the synchronization clock is 160Mhz,so how four these data lines outputs with default 20Mhz bandwidth synchronization to 160Mhz clock. (i see the equation clock rate = 4x max sample rate,20 x 4=80,maybe reduce the duty cycle).
2.My understanding is that the w3_ad_bridge pull in 160Mhz clock signal to synchronous to accept the PHY outputs ,so the w3_ad_bridge's sys_samp_clk/sys_samp_clk_90 is 160Mhz,while the FPGA-generated TXCLK's frequency (the same to Tx I/Q data rate) is equivalent to the sys_samp_clk_90 frequency that is 160Mhz,according to the WARP v3 User Guide: RF Interfaces (http://warpproject.org/trac/wiki/Hardwa … /WARPv3/RF) ,This webpage gives some examples of valid combinations of clock sources, clock frequencies and filter settings,I think the Tx I/Q data rate is the same to FPGA-generated TXCLK's frequency and the same to sys_samp_clk_90 frequency,so why the Tx I/Q data rate can be 40Mhz/80Mhz/10Mhz ?
3.are the PHY interface output rfc_dac_i , rfc_dac_q ,rfd_dac_i,rfd_dac_q have the same output data with the rfa_dac_i,rfa_dac_q,rfb_dac_i,rfb_dac_q?
That's what I don't understand.thank you!
Last edited by chenhongwei (2019-Apr-08 05:51:22)
Offline
The Tx PHY outputs a new sample when the samp_ce input is asserted. The samp_ce input and I/Q outputs are clocked at 160MHz. The RF_AD_samp_ce net connected to the samp_ce port asserts for 1 clock cycle every N clock cycles, for N = 16 (10MSps), 8 (20MSps), or 4 (40MSps).
The fmc_bb_4da inputs are different. These inputs must be given a new sample on every rising edge of the sys_samp_clk clock - this interface does not use the same fast clock + slow samp_ce scheme as the w3_ad_bridge and Tx PHY.
Offline
thank you for your reply!
Offline