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#1 2019-Aug-22 16:50:18

banerjee.152
Member
Registered: 2018-Oct-19
Posts: 4

Decrease WARP sampling rate

The current sampling rate( the default) is 40Mhz for Warp V3. I want to work with a lower sampling rate of 10Mhz. I was looking at the w3_clock_controller.c file and the w3_ad_controller.c file. Now in the w3_ad_controller.c file there is a part of the code which tells us what needs to be done to change the sampling rate . The following snippet is given.


brief Configures the ADC and DAC clock sources in the AD9963. Refer to the WARP v3 user guide and AD9963 for details
on various clocking modes
\param baseaddr Base memory address of w3_ad_controller pcore
\param csMask OR'd combination of RFA_AD_CS and RFB_AD_CS
\param DAC_clkSrc DAC clock source; must be AD_DACCLKSRC_DLL (use DLL clock) or AD_DACCLKSRC_EXT (use external reference clock)
\param ADC_clkSrc ADC clock source; must be AD_ADCCLKSRC_DLL (use DLL clock) or AD_ADCCLKSRC_EXT (use external reference clock)
\param ADC_clkDiv ADC clock divider; must be one of [AD_ADCCLKDIV_1, AD_ADCCLKDIV_2, AD_ADCCLKDIV_4] for divide-by of [1, 2, 4]
\param ADC_DCS ADC duty cycle stabilizer; must be AD_DCS_ON or AD_DCS_OFF. AD9963 datasheet recommends DCS be enabled only for ADC rates above 75MHz.
\return Returns 0 on success, -1 for invalid paramters
*/
int ad_config_clocks(u32 baseaddr, u32 csMask, u8 DAC_clkSrc, u8 ADC_clkSrc, u8 ADC_clkDiv, u8 ADC_DCS) {

    u8 regVal;
    u8 bitsToSet_reg66, bitsToSet_reg71;

    //Sanity check inputs
    if( ((csMask & (AD_CTRL_ALL_RF_CS)) == 0))
        return -1;

    /* AD9963 reg 0x66:
        7:6 Disable DAC clocks
        4:3 Disable ADC clocks
        2: Disable DCS
        1:0 ADCDIV
   
      AD9963 reg 0x71:
        7: ADC clock selection (1=DLL, 0=ext)
        6: DAC clock selection (1=DLL, 0=ext)
        4:0 DLL config
    */
   
    //Assert sane default bits, and any config bits user options require
    bitsToSet_reg66 = (ADC_DCS & AD_DCS_OFF) | (ADC_clkDiv & (AD_ADCCLKDIV_1 | AD_ADCCLKDIV_2 | AD_ADCCLKDIV_4));
    bitsToSet_reg71 = (DAC_clkSrc & AD_DACCLKSRC_DLL) | (ADC_clkSrc & AD_ADCCLKSRC_DLL);
   
    //For RFA and RFB, clear-then-set affected bits in clock config registers (0x66 and 0x71)
    if(csMask & RFA_AD_CS) {
        regVal = (u8)ad_spi_read(baseaddr, RFA_AD_CS, 0x66);
        regVal = regVal & ~(AD_DCS_OFF | AD_ADCCLKDIV_1 | AD_ADCCLKDIV_2 | AD_ADCCLKDIV_4);
        regVal = regVal | bitsToSet_reg66;
        ad_spi_write(baseaddr, RFA_AD_CS, 0x66, regVal);

        regVal = (u8)ad_spi_read(baseaddr, RFA_AD_CS, 0x71);
        regVal = regVal & ~(AD_DACCLKSRC_DLL | AD_ADCCLKSRC_DLL);
        regVal = regVal | bitsToSet_reg71;
        ad_spi_write(baseaddr, RFA_AD_CS, 0x71, regVal);
    }

    if(csMask & RFB_AD_CS) {
        regVal = (u8)(ad_spi_read(baseaddr, RFB_AD_CS, 0x66)>>8);
        regVal = regVal & ~(AD_DCS_OFF | AD_ADCCLKDIV_1 | AD_ADCCLKDIV_2 | AD_ADCCLKDIV_4);
        regVal = regVal | bitsToSet_reg66;
        ad_spi_write(baseaddr, RFB_AD_CS, 0x66, regVal);

        regVal = (u8)(ad_spi_read(baseaddr, RFB_AD_CS, 0x71)>>8);
        regVal = regVal & ~(AD_DACCLKSRC_DLL | AD_ADCCLKSRC_DLL);
        regVal = regVal | bitsToSet_reg71;
        ad_spi_write(baseaddr, RFB_AD_CS, 0x71, regVal);
    }

    if(csMask & RFC_AD_CS) {
        regVal = (u8)(ad_spi_read(baseaddr, RFC_AD_CS, 0x66)>>8);
        regVal = regVal & ~(AD_DCS_OFF | AD_ADCCLKDIV_1 | AD_ADCCLKDIV_2 | AD_ADCCLKDIV_4);
        regVal = regVal | bitsToSet_reg66;
        ad_spi_write(baseaddr, RFC_AD_CS, 0x66, regVal);

        regVal = (u8)(ad_spi_read(baseaddr, RFC_AD_CS, 0x71)>>8);
        regVal = regVal & ~(AD_DACCLKSRC_DLL | AD_ADCCLKSRC_DLL);
        regVal = regVal | bitsToSet_reg71;
        ad_spi_write(baseaddr, RFC_AD_CS, 0x71, regVal);






But I dont understand how to change the Clock value to get it sampled at a lower rate of 10Mhz

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#2 2019-Aug-23 09:33:15

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Decrease WARP sampling rate

The 802.11 Ref Design w3_low.c :: wlan_platform_low_set_samp_rate() function demonstrates how to configure the clock buffers and ADC/DAC chip for 10MSps.

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#3 2019-Aug-23 13:17:10

banerjee.152
Member
Registered: 2018-Oct-19
Posts: 4

Re: Decrease WARP sampling rate

Thanks for the response.
I was using this line of code to set 80Mhz to 10Mhz. Does this work, in  w3_clock_controller.c file.

clk_config_dividers(CLK_BASEADDR, 8, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));



And how to verify, If I am sampling at a lower rate?


Avishek

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#4 2019-Aug-26 09:46:49

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Decrease WARP sampling rate

clk_config_dividers(CLK_BASEADDR, 8, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));

This will set a 10MHz clock input to the AD9963 chips. You must also consider the clock configuration inside the AD9963, specifically whether the interpolation/decimation filters are enabled. Please refer to the code I linked to above.

And how to verify, If I am sampling at a lower rate?

Input a signal with a known frequency (like a 1MHz sinusoid) and observe the number of baseband samples per cycle of the sinusoid This would be straightforward in WARPLab.

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