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There are 5 C-project files available in Repository.
I am running "Wlan_Ap" among them.
I have done all the steps as mentioned for running a C-project except the "Generation Linker File".
Because you have told that we cannot modify the Linker file.
But still it is showing the below message and not running properly.
The message that I have got is like:
"The current launch is configured to reset the entire system.However the design contains multiple processor,and resetting the system will reset the other processor as well.
If you would like to avoid this,please update the launch configuration to reset the processor only."
After pressing "ok" button still it is not running properly.
So, what configuration we should follow?
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This message indicates you are trying to use the SDK debugger to load the software design. While this is technically possible it is not the recommended flow. Use the Program FPGA tool to configure the FPGA and load the software applications for CPU High and CPU Low (as described in the user guide).
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I have given "wlan_mac_high_ap.elf" and "wlan_mac_low_dcf.elf" files to intialize the block RAM of "mb_high" and "mb_low" processor respectively.
I have configured the Putty terminal as required.
Still,I was getting the above message in Xilinx SDK Tool:
"The current launch is configured to reset the entire system.However the design contains multiple processor,and resetting the system will reset the other processor as well."
But,When I ran the "wlan_mac_high_ap" project the Wlan Access Point named "Mango-AP" was configured properly and in the Putty terminal,some unreadable output was coming.(Baud Rate:57600)
Doubts:
1) How to remove the above message that I got in Xilinx Tool?
2) How to get actual message in Putty terminal instead of getting the Unreadable message?
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The 802.11 design uses a 115200bps UART rate.
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