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#1 2020-Nov-09 01:59:39

vutran
Member
Registered: 2017-Jul-01
Posts: 52

WARP not sharing SAMP clock

Hi Admin,

I have tested 2 WARPv3 (WARPLab7.7.1) using a CM-PLL cable for clock sharing. What I found is that the SAMP clock is not shared between 2 WARP boards. I use exactly the recommended SW configuration in (https://warpproject.org/trac/wiki/WARPL … figuration), and the master board can trigger the slave board as expected. However, I got weird phase shifts among antennas, they are drifting even on the master board. When I print the values of the register 0x45 of SAMP AD9512 and RF AD9512 on the 2 boards, and I get the following results:

On Master board:
    SAMP: 0, RF: 256 (1)
On Slave board:
    SAMP: 0, RF: 512 (2)

Based on the AD9512 datasheet, a value of 0 means that it uses the clk1 which is the onboard clock, not the one from CM-PLL. But it should use the clock originates from the onboard clock in the RF AD9512 on the master board.
On-board master -> RF-AD9512 -> CM-PLL -------> SAMP master
                                                                    |
                                                                     ---> SAMP & RF slave
Am I right?

Can you please advise? Thank you.

Best,
Vu

Last edited by vutran (2020-Nov-09 02:00:15)

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#2 2020-Nov-10 09:01:38

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5142

Re: WARP not sharing SAMP clock

The nodes print the clock configurations they adopt during boot. Look at the UART output of both nodes at boot - you'll have to scroll up from the WARPLab boot messages to see the clock config logic printouts. This will at least confirm whether the code is executing the configuration option you want.

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#3 2020-Nov-10 19:22:24

vutran
Member
Registered: 2017-Jul-01
Posts: 52

Re: WARP not sharing SAMP clock

Hi Murphpo,

Even when I insert the printf in a mem_rw request then I call a mem_rw request after the initialization, I get the same values. I mean they are not the values during BOOT time, but the values during run time.

Best,
Vu

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#4 2020-Nov-12 19:37:03

vutran
Member
Registered: 2017-Jul-01
Posts: 52

Re: WARP not sharing SAMP clock

Hi Murph,

Any update on this issue?

Best,
Vu

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#5 2020-Nov-13 12:45:34

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5142

Re: WARP not sharing SAMP clock

I would still suggest as above - verify what clocking modes the nodes are choosing at boot time by looking at the UART output. I also do not understand your description of the AD9512 registers; these are 8-bit registers, where to the values 256 and 512 come from? From the datasheet reg 0x45[0]=[0,1] => [CLK2,CLK1] input; the WARP v3 design connects CLK1 on both buffers to the on-board 80MHz TCXO and CLK2 to the clock module header (WARP v3 user guide : Clocking).

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#6 2020-Nov-18 09:31:11

vutran
Member
Registered: 2017-Jul-01
Posts: 52

Re: WARP not sharing SAMP clock

Hi,

It shows the same values at boot time and run time. As the SPI_Read returns 2 registers in RF_AD9512 and SAMP_AD9512, one takes MSB the other takes LSB, the output value becomes 512 and 256.

0x45[0]=[0,1] => [CLK2,CLK1] input

But it also specifies that if both CLK1 and CLK2 are ON, CLK1 will be used
https://drive.google.com/file/d/1H1IzMEZ8JhE5FX_YMQIU3CkqOn9wcAUQ/view?usp=sharing

Can you confirm this?

Last edited by vutran (2020-Nov-18 09:33:21)

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