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#1 2007-Jul-11 21:29:00

From: Vienna, VA
Registered: 2007-Jan-24
Posts: 121

Problem in reading RSSI data

We are testing our pcore for interfacing WARP radio card. A part of this pcore is intended for reading RSSI value. The basic scheme is thus: a 12.5MHz clock is generated by a counter and passed to the RSSI ADC, and the RSSI data is read using 50MHz clk. Therefore, each RSSI value will be read 4 times. We also use chipscope to collect these data for debugging purpose.

The problem we found is that, quite frequently, instead of getting four equal samples for the same RSSI reading, the first sample of the four is much higher than the other three, which are equal. Have you guys ran into this problem? What might be the cause? Thanks.



#2 2007-Jul-11 22:19:09

From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Problem in reading RSSI data

We've never seen this behavior, but it sounds like it could be timing problems at the input registers. The RSSI ADC data bus is registered in the radio_bridge pcore. These registers are packed into the 10 IO buffers connected to the data bus. These registers are clocked by the same signal used to drive the Tx/Rx DAC/DAC, probably the OPB clock in your system (technically, it's whatever signal is fed to the converter_clock_in port on the radio_bridge).

The odd RSSI behavior you're seeing could be setup/hold violations at these IOB registers. If the RSSI data changes around the same time as the 50MHz clock transitions at the IOBs, you would expect to see unpredictable data values registered that cycle.

We got lucky and avoided this problem by having the phases of the RSSI clock and input gateways aligned (i.e. we ended up processing one of the three good samples). We'll probably update the radio_bridge at some point to avoid this problem explicitly.



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