source: Documentation/Tutorials/Custom_Peripherals/html/sections/Creating_the_Model.html

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6    <title>Creating the Model</title>
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22                <h1 class="LessonTitle">Creating the Model</h1>
23            </div>
24                <div class="summary">
25        <p>The steps to create the model are described in this section. At the end the entire DDS model will be complete and ready for simulation.</p>
26    </div>
27           
28                <div id="step_1" class="lessonStep top">
29       
30        <div class="image">
31<img src="images/Creating_the_Model/media_1222029457018.png" width="560" height="319">
32</div> <p>Open <strong>MATLAB 2007a</strong>.</p>
33    </div>
34    <div class="clear"></div>
35    <div id="step_2" class="lessonStep top">
36       
37        <div class="image">
38<img src="images/Creating_the_Model/media_1222029980844.png" width="244" height="179">
39</div> <p>Open the <strong>Simulink Library</strong> browser by typing <strong>'simulink'</strong> on the MATLAB Command Window.</p>
40    </div>
41    <div class="clear"></div>
42    <div id="step_3" class="lessonStep top">
43       
44        <div class="image">
45<img src="images/Creating_the_Model/media_1222029990559.png" width="486" height="802">
46</div> <p>This should open a browser that looks like the above picture. Notice that there is a WARP Blockset. If you do not see this in your library, re-visit the instructions on installing the WARP user repository at http://warp.rice.edu/trac.</p>
47    </div>
48    <div class="clear"></div>
49    <div id="step_4" class="lessonStep top">
50       
51        <div class="image">
52<img src="images/Creating_the_Model/media_1222030014885.png" width="313" height="170">
53</div> <p>Open a new model by clicking <strong>New </strong>-&gt; <strong>Model</strong> in the Simulink Library Browser. This should open a blank canvas where the new design will be built.</p>
54    </div>
55    <div class="clear"></div>
56    <div id="step_5" class="lessonStep top">
57       
58        <div class="image">
59<img src="images/Creating_the_Model/media_1222030135166.png" width="486" height="802">
60</div> <p>Expand the Xilinx Blockset by clicking the plus (+) sign next to it. These are the blocks that we will use to create the custom peripherals as they can be generated into HDL code. Only blocks with a white <strong>X</strong> are valid for generation.</p>
61    </div>
62    <div class="clear"></div>
63    <div id="step_6" class="lessonStep top">
64       
65        <div class="image">
66<img src="images/Creating_the_Model/media_1222047713686.png" width="560" height="410">
67</div> <p>Drag in a <strong>System Generator</strong> block. This is required at the top-level in every Sysgen design. It has the system parameters such as simulation sampling period and corresponding clock frequency. This also has the options to generate HDL.</p>
68
69
70<p>Save the model as <strong>ddsexample.mdl</strong> in a folder that does not contain spaces. For example, 'C:\Documents and Settings\User\Desktop' is <strong>not</strong> a valid location while 'C:\WARP_Tutorial\Peripherals' is valid.</p>
71    </div>
72    <div class="clear"></div>
73    <div id="step_7" class="lessonStep top">
74       
75        <div class="image">
76<img src="images/Creating_the_Model/media_1222047790362.png" width="560" height="410">
77</div> <p>Drag in an <strong>Accumulator</strong> Block. This will increment a phase value to feed to the LUT.</p>
78    </div>
79    <div class="clear"></div>
80    <div id="step_8" class="lessonStep top">
81       
82        <div class="image">
83<img src="images/Creating_the_Model/media_1222047804688.png" width="403" height="512">
84</div> <p>Double-click the block to open the options window. Set it up as shown above. The synchronous reset port will not be needed and choose 32 bits for the data to maintain high-precision.</p>
85    </div>
86    <div class="clear"></div>
87    <div id="step_9" class="lessonStep top">
88       
89        <div class="image">
90<img src="images/Creating_the_Model/media_1222047869971.png" width="560" height="410">
91</div> <p>Drag in a <strong>Slice</strong> block. We are going to use a LUT to store the sine and cosine waves, but they will only be 2^12 deep. So we need to slice off the top 12 bits of the Accumulator to feed into the address port of the LUT.</p>
92    </div>
93    <div class="clear"></div>
94    <div id="step_10" class="lessonStep top">
95       
96        <div class="image">
97<img src="images/Creating_the_Model/media_1222047899012.png" width="485" height="431">
98</div> <p>In the options for the Slice, set the width to be 12 and MSB input. This will slice 12 bits from the top of the word.</p>
99    </div>
100    <div class="clear"></div>
101    <div id="step_11" class="lessonStep top">
102       
103        <div class="image">
104<img src="images/Creating_the_Model/media_1222048048007.png" width="560" height="410">
105</div> <p>Drag in 2 <strong>ROM</strong> blocks. These will serve as the LUT that store the sine and cosine waves. Rename the blocks as <strong>SIN</strong> and <strong>COS</strong> to diambiguate them.</p>
106    </div>
107    <div class="clear"></div>
108    <div id="step_12" class="lessonStep top">
109       
110        <div class="image">
111<img src="images/Creating_the_Model/media_1222048088286.png" width="384" height="363">
112</div> <p>In the options for the SIN block, the depth should be set as <strong>2^12</strong> as thats the number of sample we want to store. The Initial Value Vector must be set one complete sine wave.</p>
113    </div>
114    <div class="clear"></div>
115    <div id="step_13" class="lessonStep top">
116       
117        <div class="image">
118<img src="images/Creating_the_Model/media_1222051041794.png" width="384" height="363">
119</div> <p>In the Output Type tab, make sure to set the output for <strong>Signed</strong> with <strong>16</strong> bits and binary point at <strong>15</strong>. This should give us sufficient precision for the waves.</p>
120    </div>
121    <div class="clear"></div>
122    <div id="step_14" class="lessonStep top">
123       
124        <div class="image">
125<img src="images/Creating_the_Model/media_1222048113159.png" width="384" height="363">
126</div> <p>Similarly for the COS, the Initial Value vector must the cosine wave. Remember to set the precision as well just like the sine wave.</p>
127    </div>
128    <div class="clear"></div>
129    <div id="step_15" class="lessonStep top">
130       
131        <div class="image">
132<img src="images/Creating_the_Model/media_1222048166873.png" width="560" height="410">
133</div> <p>In order to drive the Accumulator, we need a constant phase increment input. This will be done using the <strong>From Register</strong> Block. The idea is that given a constant phase increment, the accumulator will loop through the values stored in the ROM at that rate. If the phase increment value is high, the sine and cosine wave outputs will have a higher frequency, while if the value is low, the output freqency will be low as well.</p>
134    </div>
135    <div class="clear"></div>
136    <div id="step_16" class="lessonStep top">
137       
138        <div class="image">
139<img src="images/Creating_the_Model/media_1222048218833.png" width="417" height="289">
140</div> <p>Setup the From Register by giving it the name <strong>phaseInc</strong>. Set the Initial Value to <strong>1</strong>. Set the register to be <strong>Locally owned and initialized</strong>.</p>
141    </div>
142    <div class="clear"></div>
143    <div id="step_17" class="lessonStep top">
144       
145        <div class="image">
146<img src="images/Creating_the_Model/media_1222048227464.png" width="417" height="289">
147</div> <p>Also for the Output type, we can take an input up to <strong>32</strong> bits as that is the width of the Accumulator. However, this time we want it to be <strong>Unsigned</strong> as we will like only positive increment values.</p>
148    </div>
149    <div class="clear"></div>
150    <div id="step_18" class="lessonStep top">
151       
152        <div class="image">
153<img src="images/Creating_the_Model/media_1222048326430.png" width="560" height="410">
154</div> <p>The output of the ROM blocks varies between 1 and -1. That is the extent that the DAC can output. To avoid hitting the rails, the output must be scaled. Use a <strong>Scale</strong> block on the output of the ROMs.</p>
155    </div>
156    <div class="clear"></div>
157    <div id="step_19" class="lessonStep top">
158       
159        <div class="image">
160<img src="images/Creating_the_Model/media_1222048333757.png" width="372" height="246">
161</div> <p>Set the block to scale by <strong>2^-1</strong>. Now the output should vary between -0.5 and 0.5. </p>
162    </div>
163    <div class="clear"></div>
164    <div id="step_20" class="lessonStep top">
165       
166        <div class="image">
167<img src="images/Creating_the_Model/media_1222048565536.png" width="560" height="410">
168</div> <p>Before passing the sine and cosine values to the DAC, lets add a <strong>Register</strong> so we can reset the output if needed.</p>
169    </div>
170    <div class="clear"></div>
171    <div id="step_21" class="lessonStep top">
172       
173        <div class="image">
174<img src="images/Creating_the_Model/media_1222048582499.png" width="384" height="248">
175</div> <p>Check the <strong>synchronous reset port</strong> box that can be asserted using a register.</p>
176    </div>
177    <div class="clear"></div>
178    <div id="step_22" class="lessonStep top">
179       
180        <div class="image">
181<img src="images/Creating_the_Model/media_1222048818650.png" width="560" height="410">
182</div> <p>Add a <strong>From Register</strong> block and a <strong>Convert</strong> block to connect to the reset ports of the registers. The From Register can only output Unsigned or Signed, but the reset requires a Boolean input. This will be done by the Convert block.</p>
183    </div>
184    <div class="clear"></div>
185    <div id="step_23" class="lessonStep top">
186       
187        <div class="image">
188<img src="images/Creating_the_Model/media_1222048839986.png" width="417" height="289">
189</div> <p>Name the From Register <strong>outputReset</strong>. Make sure the initial value is <strong>0</strong> so the system is not in reset by default.</p>
190    </div>
191    <div class="clear"></div>
192    <div id="step_24" class="lessonStep top">
193       
194        <div class="image">
195<img src="images/Creating_the_Model/media_1222048845063.png" width="417" height="289">
196</div> <p>Change the output type of the From Register to <strong>Unsigned</strong> with <strong>1</strong> bit.</p>
197    </div>
198    <div class="clear"></div>
199    <div id="step_25" class="lessonStep top">
200       
201        <div class="image">
202<img src="images/Creating_the_Model/media_1222048826553.png" width="497" height="389">
203</div> <p>For the Convert block, change the output type to <strong>Boolean</strong>.</p>
204    </div>
205    <div class="clear"></div>
206    <div id="step_26" class="lessonStep top">
207       
208        <div class="image">
209<img src="images/Creating_the_Model/media_1222048898711.png" width="486" height="802">
210</div> <p>The last step is to add DACs. Two pairs of DACs will connect to both outputs; one forwarding the data to the Analog Board and the other to the Radio Board.</p>
211
212
213<p>To add the DAC blocks, expand the <strong>WARP Blockset</strong>.</p>
214    </div>
215    <div class="clear"></div>
216    <div id="step_27" class="lessonStep top">
217       
218        <div class="image">
219<img src="images/Creating_the_Model/media_1222049058578.png" width="560" height="410">
220</div> <p>Drag in <strong>Analog 4 DAC 1A </strong>and <strong>Analog 4 DAC 1B</strong>. The 4 is because the Analog Daughtercard is normally in slot 4, while 1A and 1B correspond to the DAC outputs on the daughtercard.</p>
221    </div>
222    <div class="clear"></div>
223    <div id="step_28" class="lessonStep top">
224       
225        <div class="image">
226<img src="images/Creating_the_Model/media_1222049098799.png" width="560" height="410">
227</div> <p>Connect the output of your system to Radio blocks as well. Thus this model can be connected to the Analog Board or Radio Board. Drag in <strong>Radio 2 DAC I</strong> and <strong>Radio 2 DAC Q</strong>. Remember to connect the sine to the Q channel and the cosine to I channel.</p>
228    </div>
229    <div class="clear"></div>
230    <div id="step_29" class="lessonStep top">
231       
232        <div class="image">
233<img src="images/Creating_the_Model/media_1222050230364.png" width="560" height="365">
234</div> <p>Finally, drag in <strong>Bus Creator</strong> and <strong>Scope</strong> blocks and connect the Analog Board outputs to them. This well help in simulation.</p>
235
236
237<p>At this time, the model itself is complete. Next we will test and simulate model before generating the HDL corresponding to it.</p>
238    </div>
239    <div class="clear"></div>
240
241        </div>
242        <div id="lessonNavigation">
243            <table>
244                <tr>
245                    <td class="lessonNav_Left"><a href="Requirements.html">&lt;&lt; Requirements</a></td>
246                    <td class="lessonNav_TOC"><a href="../Custom_Peripherals.html">Top</a></td>
247                    <td class="lessonNav_Right"><a href="Simulating_the_Design.html">Simulating the Design &gt;&gt;</a> </td>
248                </tr>
249            </table>
250        </div>
251    </div> 
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