source: Documentation/Tutorials/Custom_Peripherals/html/sections/Exporting_as_Peripheral_Core.html

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modification to custom peripheral generation tutorial
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1<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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6    <title>Exporting as Peripheral Core</title>
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13            <a id="logo" href="http://warp.rice.edu/trac/"><img src="http://warp.rice.edu/images/warpLogo.jpg" alt="Rice University WARP - Wireless Open-Access Research Platform" height="45" width="285" /></a>
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21            <div class="LessonHeader">
22                <h1 class="LessonTitle">Exporting as Peripheral Core</h1>
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24                <div class="summary">
25        <p>The final step to create a custom HDL core is described in this section. The result is a peripheral core (pcore) that can be inserted into a Xilinx Platform Studio (XPS) project.</p>
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31<img src="images/Exporting_as_Peripheral_Core/media_1222052238358.png" width="417" height="289">
32</div> <p>Before generating the HDL core, set the intial value of the <strong>phaseInc</strong> register back to 1 embedding this value into the hardware design. The From Registers will get memory-mapped in the process of generation and we will be able to change their values by reading and writing certain address locations.</p>
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38<img src="images/Exporting_as_Peripheral_Core/media_1222052262140.png" width="560" height="365">
39</div> <p>In order to create memory map, drag in the <strong>EDK Processor</strong> block from the Xilinx Library.</p>
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45<img src="images/Exporting_as_Peripheral_Core/media_1222052284363.png" width="419" height="496">
46</div> <p>Double-clicking it will reveal the options window. Click <strong>Add</strong> to create the register map. This will populate the map with the list of registers found in the system. The registers can be expanded to see their address locations. Click <strong>Apply</strong> to save.</p>
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52<img src="images/Exporting_as_Peripheral_Core/media_1233876573946.png" width="419" height="496">
53</div> <p>Move to the <strong>Implementation</strong> tab of the EDK Processor block. Here check <strong>Register Read-Back</strong> as shown above. Click <strong>Ok</strong> or <strong>Apply</strong> to save.</p>
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59<img src="images/Exporting_as_Peripheral_Core/media_1222052727145.png" width="434" height="586">
60</div> <p>Open the <strong>System Generator</strong> block. It will reveals a whole set of options to create the design. As the model is going to be part of a Xilinx Platform Studio project, choose <strong>EDK Export Tool</strong> to the Compilation. This will create all the supporting files so it can be recognized by the Embedded Development Kit (EDK) that Xilinx provides.</p>
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65        <div class="image">
66<img src="images/Exporting_as_Peripheral_Core/media_1222052998431.png" width="434" height="586">
67</div> <p>The WARP Boards are Virtex-II Pro FPGA-based so select the <strong>Virtex2P </strong>-&gt; <strong>xc2vp70 </strong>-&gt; <strong>-6 </strong>-&gt; <strong>ff1517</strong>. This selects the correct target as each FPGA has a different architecture inside.</p>
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69
70<p>Finally, click <strong>Generate</strong> to start the compilation.</p>
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76<img src="images/Exporting_as_Peripheral_Core/media_1222053233488.png" width="349" height="162">
77</div> <p>The above window will pop-up once the generation is complete. At this point there is an XPS-compatible peripheral core available in the <strong>./netlist/pcores</strong> folder. This includes the HDL for the core and associated data files that identifies the type of core, the memory-mapped locations etc.</p>
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83            <table>
84                <tr>
85                    <td class="lessonNav_Left"><a href="Simulating_the_Design.html">&lt;&lt; Simulating the Design</a></td>
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