Base System Builder - FPGA Board v1.2
This section describes the process of launching XPS and creating a simple hardware/software platform using Base System Builder. This section of the tutorial is specifically created for FPGA Board v1.2. Once you complete this section, skip to XPS Intro - Implementing the hardware design. Skip this section if you have FPGA Board v2.2.
Launch the Xilinx Platform Studio application.
Select Base System Builder to create a new project.
Enter a path for your project. Two key requirements:
-The project file must be named 'system.xmp'
-The project file must be saved to a folder with no spaces in its path - "C:\Documents and Settings\user\" will not work!
Choose the option for a new design.
Base System Builder supports many development boards, including the WARP hardware platform. For this exercise, choose the board named 'WARP FPGA Board' and select revision 'FPGA 1.2'.
The Xilinx EDK supports two embedded processors. The PowerPC processor is a "hard" processor core, embedded in the fabric of the Virtex-II Pro FPGA on the WARP FPGA board. MicroBlaze is a "soft" processor core, implemented in the FPGA fabric itself. For this exercise (and all WARP designs generally), select the PowerPC core.
The clocking and memory architectures for EDK designs are very flexible. Base System Builder supports some simple clock/memory configurations. In more sophisticated designs, the clocking and memory options can be further customized by hand. For this exercise, select the clock frequencies and memory sizes shown above.
The next few screens present a list of available I/O devices. Each device corresponds to an off-chip interface on the WARP FPGA board. Each device can be enaled/disabled using its checkbox. For this exercise, choose the peripherals as follows:
Enabled:
- User I/O (with 'Use interrupt enabled)
- rs232 (configured for 57600 bps)
Disabled:
- sysace_compactflash
- eeprom_controller
- Ethernet_MAC
- user_io_board_controller_slot1
- SRAM0 / SRAM1
After configuring off-chip devices, you now configure on-chip peripheral cores. By default, an internal RAM block is enabled. For this exercise, click 'Remove' to omit this core from the design.
For user applications running in the PowerPC processor, the EDK tools can map the WARP FPGA board's serial port (the core named 'rs232' here) to the STDIN/STDOUT conventions. This allows funcitons like printf() to work normally, using an external terminal emulator as the PowerPC's display and keyboard.
XPS can also create sample software projects which exercise the memory and peripheral devices in your hardware design. For this exercise, disable both example proejcts (you'll create a new software project later).
Base System Builder assigns default memory addresses to each memory and memory-mapped peripheral device. The addresses in your project may vary from those shown here. In general, the defaults selected by BSB work fine.
When Base System Builder finishes, XPS will open the resulting project. The remaining sections of this exercise describe how to use this interface to customize and test your hardware & software platform.