[1446] | 1 | <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> |
---|
| 2 | <html xmlns="http://www.w3.org/1999/xhtml"> |
---|
| 3 | <head> |
---|
| 4 | <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"> |
---|
| 5 | <meta name="generator" content="ScreenSteps http://www.screensteps.com/" /> |
---|
| 6 | <title>Base System Builder - FPGA Board v2.2</title> |
---|
| 7 | <link href="../neutral.css" media="screen" rel="stylesheet" type="text/css" /> |
---|
| 8 | </head> |
---|
| 9 | |
---|
| 10 | <body class="lucida"> |
---|
| 11 | <div id="wrapper"> |
---|
| 12 | <div id="header"> |
---|
| 13 | <a id="logo" href="http://warp.rice.edu/trac/"><img src="http://warp.rice.edu/images/warpLogo.jpg" alt="Rice University WARP - Wireless Open-Access Research Platform" height="45" width="285" /></a> |
---|
| 14 | </div> |
---|
| 15 | <div id="mainnav" class="nav"> |
---|
| 16 | <ul> |
---|
| 17 | <li class="first active"><a href="/trac/wiki">Home</a></li><li><a href="/forums">Forums</a></li><li><a href="/trac/browser">Browse Source</a></li> |
---|
| 18 | </ul> |
---|
| 19 | </div> |
---|
| 20 | <div id="LessonContent"> |
---|
| 21 | <div class="LessonHeader"> |
---|
| 22 | <h1 class="LessonTitle">Base System Builder - FPGA Board v2.2</h1> |
---|
| 23 | </div> |
---|
| 24 | <div class="summary"> |
---|
[1447] | 25 | <p>This section describes the process of launching XPS and creating a simple hardware/software platform using Base System Builder. This section of the tutorial is specifically created for FPGA Board v2.2. Once you complete this, skip to <strong>XPS Intro - Implementing the hardware design</strong>. Use the previous section if you have FPGA Board v1.2.</p> |
---|
[1446] | 26 | </div> |
---|
| 27 | |
---|
| 28 | <div id="step_1" class="lessonStep top"> |
---|
| 29 | |
---|
| 30 | <div class="image"> |
---|
| 31 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265822590190.png" width="560" height="463"> |
---|
| 32 | </div> <p>Launch Xilinx Platform Studio.</p> |
---|
| 33 | </div> |
---|
| 34 | <div class="clear"></div> |
---|
| 35 | <div id="step_2" class="lessonStep top"> |
---|
| 36 | |
---|
| 37 | <div class="image"> |
---|
| 38 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823146473.png" width="361" height="282"> |
---|
| 39 | </div> <p>Select Base System Builder to create a new design.</p> |
---|
| 40 | </div> |
---|
| 41 | <div class="clear"></div> |
---|
| 42 | <div id="step_3" class="lessonStep top"> |
---|
| 43 | |
---|
| 44 | <div class="image"> |
---|
| 45 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823185409.png" width="408" height="247"> |
---|
| 46 | </div> <p>Enter a path for your project. Two key requirements:<br /> |
---|
| 47 | -The project file must be named 'system.xmp'<br /> |
---|
| 48 | -The project file must be saved to a folder with no spaces in its path - "C:\Documents and Settings\user\" will not work!</p> |
---|
| 49 | </div> |
---|
| 50 | <div class="clear"></div> |
---|
| 51 | <div id="step_4" class="lessonStep top"> |
---|
| 52 | |
---|
| 53 | <div class="image"> |
---|
| 54 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823266596.png" width="507" height="727"> |
---|
| 55 | </div> <p>Choose the option for a new design.</p> |
---|
| 56 | </div> |
---|
| 57 | <div class="clear"></div> |
---|
| 58 | <div id="step_5" class="lessonStep top"> |
---|
| 59 | |
---|
| 60 | <div class="image"> |
---|
| 61 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823600798.png" width="509" height="726"> |
---|
| 62 | </div> <p>Select <strong>WARP Kits (FPGA/Clock/Radio Boards)</strong> and <strong>FPGA v2.2 / Radio 1.4 / Clock 1.1</strong>.</p> |
---|
| 63 | </div> |
---|
| 64 | <div class="clear"></div> |
---|
| 65 | <div id="step_6" class="lessonStep top"> |
---|
| 66 | |
---|
| 67 | <div class="image"> |
---|
| 68 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823645566.png" width="509" height="730"> |
---|
| 69 | </div> <p>The Xilinx EDK supports two embedded processors. The PowerPC processor is a "hard" processor core, embedded in the fabric of the Virtex-4 FPGA on the WARP FPGA board. MicroBlaze is a "soft" processor core, implemented in the FPGA fabric itself. For this exercise (and all WARP designs generally), select the PowerPC core.</p> |
---|
| 70 | </div> |
---|
| 71 | <div class="clear"></div> |
---|
| 72 | <div id="step_7" class="lessonStep top"> |
---|
| 73 | |
---|
| 74 | <div class="image"> |
---|
| 75 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823731472.png" width="509" height="727"> |
---|
| 76 | </div> <p>The clocking and memory architectures for EDK designs are very flexible. Base System Builder supports some simple clock/memory configurations. In more sophisticated designs, the clocking and memory options can be further customized by hand. For this exercise, select the clock frequencies and memory sizes shown above. </p> |
---|
| 77 | </div> |
---|
| 78 | <div class="clear"></div> |
---|
| 79 | <div id="step_8" class="lessonStep top"> |
---|
| 80 | |
---|
| 81 | <div class="image"> |
---|
| 82 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823783501.png" width="508" height="727"> |
---|
| 83 | </div> <p>The next few screens present a list of available I/O devices. Each device corresponds to an off-chip interface on the WARP FPGA board. Each device can be enaled/disabled using its checkbox. For this exercise, choose the peripherals as follows:</p> |
---|
| 84 | |
---|
| 85 | |
---|
| 86 | <p><strong>Enabled:</strong><br /> |
---|
| 87 | - warp_v4_userio_all<br /> |
---|
| 88 | - rs232_db9<br /> |
---|
| 89 | - clock_board_config<br /> |
---|
| 90 | - radio_bridge_slot_2<br /> |
---|
| 91 | - radio_controller_0</p> |
---|
| 92 | |
---|
| 93 | |
---|
| 94 | <p><strong>Disabled:</strong><br /> |
---|
| 95 | - rs232_usb (a second serial port that is converted to USB on the board using an FTDI chip)<br /> |
---|
| 96 | - sysace_compactflash<br /> |
---|
| 97 | - TriMode_MAC_GMII<br /> |
---|
| 98 | - DDR2_SDRAM_2GB<br /> |
---|
| 99 | - radio_bridge_slot_1<br /> |
---|
| 100 | - radio_bridge_slot_3<br /> |
---|
| 101 | - radio_bridge_slot_4<br /> |
---|
| 102 | - eeprom_controller<br /> |
---|
| 103 | - analog_bridge_slot_4<br /> |
---|
| 104 | - user_io_board_controller_slot1</p> |
---|
| 105 | </div> |
---|
| 106 | <div class="clear"></div> |
---|
| 107 | <div id="step_9" class="lessonStep top"> |
---|
| 108 | |
---|
| 109 | <div class="image"> |
---|
| 110 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823805887.png" width="508" height="727"> |
---|
| 111 | </div> |
---|
| 112 | </div> |
---|
| 113 | <div class="clear"></div> |
---|
| 114 | <div id="step_10" class="lessonStep top"> |
---|
| 115 | |
---|
| 116 | <div class="image"> |
---|
| 117 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823830892.png" width="510" height="728"> |
---|
| 118 | </div> |
---|
| 119 | </div> |
---|
| 120 | <div class="clear"></div> |
---|
| 121 | <div id="step_11" class="lessonStep top"> |
---|
| 122 | |
---|
| 123 | <div class="image"> |
---|
| 124 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823849668.png" width="509" height="727"> |
---|
| 125 | </div> |
---|
| 126 | </div> |
---|
| 127 | <div class="clear"></div> |
---|
| 128 | <div id="step_12" class="lessonStep top"> |
---|
| 129 | |
---|
| 130 | <div class="image"> |
---|
| 131 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823863571.png" width="510" height="727"> |
---|
| 132 | </div> <p>After configuring off-chip devices, you now configure on-chip peripheral cores. By default, an internal RAM block is enabled. For this exercise, click 'Remove' to omit this core from the design.</p> |
---|
| 133 | </div> |
---|
| 134 | <div class="clear"></div> |
---|
| 135 | <div id="step_13" class="lessonStep top"> |
---|
| 136 | |
---|
| 137 | <div class="image"> |
---|
| 138 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823879179.png" width="509" height="727"> |
---|
| 139 | </div> <p>For user applications running in the PowerPC processor, the EDK tools can map the WARP FPGA board's serial port (the core named 'rs232_db9' here) to the STDIN/STDOUT conventions. This allows funcitons like printf() to work normally, using an external terminal emulator as the PowerPC's display and keyboard.</p> |
---|
| 140 | |
---|
| 141 | |
---|
| 142 | <p>XPS can also create sample software projects which exercise the memory and peripheral devices in your hardware design. For this exercise, disable both example proejcts (you'll create a new software project later).</p> |
---|
| 143 | </div> |
---|
| 144 | <div class="clear"></div> |
---|
| 145 | <div id="step_14" class="lessonStep top"> |
---|
| 146 | |
---|
| 147 | <div class="image"> |
---|
| 148 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265823894935.png" width="509" height="728"> |
---|
| 149 | </div> <p>Base System Builder assigns default memory addresses to each memory and memory-mapped peripheral device. The addresses in your project may vary from those shown here. In general, the defaults selected by BSB work fine.</p> |
---|
| 150 | </div> |
---|
| 151 | <div class="clear"></div> |
---|
| 152 | <div id="step_15" class="lessonStep top"> |
---|
| 153 | |
---|
| 154 | <div class="image"> |
---|
| 155 | <img src="images/Base_System_Builder_-_FPGA_Board_v2/media_1265824078763.png" width="560" height="324"> |
---|
| 156 | </div> <p>When Base System Builder finishes, XPS will open the resulting project. The remaining sections of this exercise describe how to use this interface to customize and test your hardware & software platform.</p> |
---|
| 157 | </div> |
---|
| 158 | <div class="clear"></div> |
---|
| 159 | |
---|
| 160 | </div> |
---|
| 161 | <div id="lessonNavigation"> |
---|
| 162 | <table> |
---|
| 163 | <tr> |
---|
| 164 | <td class="lessonNav_Left"><a href="Base_System_Builder_-_FPGA_Board_v1.html"><< Base System Builder - FPGA Board v1.2</a></td> |
---|
| 165 | <td class="lessonNav_TOC"><a href="../XPS_Intro.html">Top</a></td> |
---|
| 166 | <td class="lessonNav_Right"><a href="XPS_Intro_-_Implementing_the_hardware_platform.html">XPS Intro - Implementing the hardware platform >></a> </td> |
---|
| 167 | </tr> |
---|
| 168 | </table> |
---|
| 169 | </div> |
---|
| 170 | </div> |
---|
| 171 | </body> |
---|
| 172 | </html> |
---|