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| 20 | <div id="LessonContent"> |
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| 21 | <div class="LessonHeader"> |
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| 22 | <h1 class="LessonTitle">XPS Intro - Implementing the hardware platform</h1> |
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| 23 | </div> |
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| [970] | 24 | <div class="summary"> |
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| 25 | <p>This section goes over the basic steps to create the hardware bitstream.</p> |
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| 26 | </div> |
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| [952] | 27 | |
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| 28 | <div id="step_1" class="lessonStep top"> |
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| 29 | |
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| 30 | <div class="image"> |
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| 31 | <a href="images/XPS_Intro_-_Implementing_the_hardware_platform/SysAssemblyView_labeled_lg.png" class="image" target="_blank"><img src="images/XPS_Intro_-_Implementing_the_hardware_platform/SysAssemblyView_labeled.png" width="580" height="286"></a> |
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| 32 | <div class="caption"><a href="images/XPS_Intro_-_Implementing_the_hardware_platform/SysAssemblyView_labeled_lg.png" target="_blank">Zoom</a></div> |
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| 33 | </div> <p>The main XPS window is divided into three primary areas:</p> |
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| 34 | |
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| 35 | |
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| [1446] | 36 | <p><strong>Platform Files</strong>: This pane lists the files which describe your project. It also lists the configuration files used to drive the hardware implementation processes. There are three panes for this view:<br /> |
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| 37 | <strong> • Project: </strong>Lists the EDK files which describe your hardware (MHS/UCF) and software (MSS) projects. It also lists configuration files which drive the back-end tools.<br /> |
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| 38 | <strong> • Applications: </strong>Lists your software applications (used below).<br /> |
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| [952] | 39 | <strong> • IP Catalog:</strong> This view lists all of the peripheral cores available to build your hardware platform. These cores are drawn from Xilinx-provided cores distributed with the EDK, WARP-supplied cores and cores of your own design. </p> |
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| 40 | |
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| 41 | |
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| [1446] | 42 | <p><strong>System Assembly View:</strong><br /> |
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| 43 | The hardware design is composed of multiple processor, bus and peripheral cores. Each core is listed in this pane. The system assembly view pane has three displays:<br /> |
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| 44 | <strong> • Bus Interfaces</strong>: Lists each core's bus connectivity. Some cores are attached to the PLB; some (like clock_generator_0) are not attached to any bus.<br /> |
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| 45 | <strong> • Ports:</strong> In addition to bus interfacs, some cores have core-to-core connections in hardware. Each core's top-level ports and their connections are shown in this view <br /> |
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| [952] | 46 | <strong> • Addresses</strong>: Peripherals with bus connections are mapped into the address space of the PowerPC processor. This view configures the address space for each core.</p> |
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| 47 | |
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| 48 | |
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| 49 | <p><strong>Log Viewer:</strong> XPS uses many back-end tools to synthesize hardware and compile software. This viewer displays the output as these tools run. This is where to look for error messages if your build fails.</p> |
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| 50 | </div> |
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| 51 | <div class="clear"></div> |
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| 52 | <div id="step_2" class="lessonStep top"> |
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| 53 | |
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| 54 | <div class="image"> |
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| [1446] | 55 | <a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1265824217494_lg.png" class="image" target="_blank"><img src="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1265824217494.png" width="580" height="249"></a> |
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| 56 | <div class="caption"><a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1265824217494_lg.png" target="_blank">Zoom</a></div> |
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| 57 | </div> <p>Skip this step if you are using FPGA Board v1.2. As the FPGAv2 uses the Clock Board to drive the FPGA, the DCM must be held in reset while the Clock Board is being configured. To make this possible connect 'config_invalid' on the clock_board_config to the RST port of clock_generator_0, as shown above.</p> |
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| 58 | </div> |
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| 59 | <div class="clear"></div> |
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| 60 | <div id="step_3" class="lessonStep top"> |
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| 61 | |
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| 62 | <div class="image"> |
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| 63 | <a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1265824296149_lg.png" class="image" target="_blank"><img src="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1265824296149.png" width="580" height="170"></a> |
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| 64 | <div class="caption"><a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1265824296149_lg.png" target="_blank">Zoom</a></div> |
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| 65 | </div> <p>Skip this step if you are using FPGA Board v1.2. In this project we also enabled the radio_bridge peripheral to allow the hardware and software to talk to the Radio Board. However, the clock that is available to the Radio Board must also be available the radio_bridge peripheral. To enable this, connect 'converter_clock_in' on radio_bridge_slot_2 to 'sys_clk_s'.</p> |
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| 66 | </div> |
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| 67 | <div class="clear"></div> |
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| 68 | <div id="step_4" class="lessonStep top"> |
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| 69 | |
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| 70 | <div class="image"> |
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| [952] | 71 | <a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215633920202_lg.png" class="image" target="_blank"><img src="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215633920202.png" width="580" height="324"></a> |
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| 72 | <div class="caption"><a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215633920202_lg.png" target="_blank">Zoom</a></div> |
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| 73 | </div> <p>Switch to the Address view in the System Assembly View panel. Click <strong>Generate Addresses</strong>; the log viewer will display the auto-generated address map for your PowerPC processor.</p> |
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| 74 | </div> |
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| 75 | <div class="clear"></div> |
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| [1446] | 76 | <div id="step_5" class="lessonStep top"> |
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| [952] | 77 | |
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| 78 | <div class="image"> |
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| 79 | <a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215634025193_lg.png" class="image" target="_blank"><img src="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215634025193.png" width="580" height="326"></a> |
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| 80 | <div class="caption"><a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215634025193_lg.png" target="_blank">Zoom</a></div> |
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| [973] | 81 | </div> <p>From the <strong>Hardware</strong> menu, select <strong>Generate Bistream</strong>. This will initiate the hardware synthesis process. The EDK will use tools from Xilinx ISE to synthesize the VHDL description of each peripheral, apply timing and I/O constraints, map the design into hardware and generate an FPGA configuration file (the bitstream). This process will take a few minutes, depending on the speed of your PC.</p> |
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| [952] | 82 | </div> |
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| 83 | <div class="clear"></div> |
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| [1446] | 84 | <div id="step_6" class="lessonStep top"> |
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| [952] | 85 | |
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| 86 | <div class="image"> |
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| 87 | <a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215634981586_lg.png" class="image" target="_blank"><img src="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215634981586.png" width="580" height="324"></a> |
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| 88 | <div class="caption"><a href="images/XPS_Intro_-_Implementing_the_hardware_platform/media_1215634981586_lg.png" target="_blank">Zoom</a></div> |
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| [973] | 89 | </div> <p>When the log viewer displays <strong>Bitstream generation is complete</strong>, the hardware platform is fully synthesized and ready for use. Several warnings will come up during the synthesis but if <strong>Done!</strong> appears then the generation is complete. If not, then errors were thrown and need to be investigated.</p> |
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| 90 | |
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| 91 | |
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| 92 | <p>The next section describes how to create a software project which runs on this hardware design.</p> |
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| [952] | 93 | </div> |
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| 95 | |
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| 99 | <tr> |
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| [1446] | 100 | <td class="lessonNav_Left"><a href="Base_System_Builder_-_FPGA_Board_v2.html"><< Base System Builder - FPGA Board v2.2</a></td> |
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| [952] | 101 | <td class="lessonNav_TOC"><a href="../XPS_Intro.html">Top</a></td> |
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| 102 | <td class="lessonNav_Right"><a href="XPS_Intro_-_Implementing_the_software_design.html">XPS Intro - Implementing the software design >></a> </td> |
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| 103 | </tr> |
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