Rev | Line | |
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[1370] | 1 | #FPGA Board v2.2 Clock Constraints |
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| 2 | # |
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| 3 | # The constraints using the onboard 100MHz oscillator |
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| 4 | Net sys_clk_pin LOC=AM21; |
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| 5 | Net sys_clk_pin IOSTANDARD = LVTTL; |
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| 6 | Net sys_clk_pin TNM_NET = sys_clk_pin; |
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| 7 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; |
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| 8 | # |
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| 9 | # The constraints using the Clock Board generated 40MHz |
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| 10 | # clock for the design. NOTE: The clock_board_configurator |
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| 11 | # must be instantiated to configure the clock board |
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| 12 | Net sys_clk_pin LOC=AN20; |
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| 13 | Net sys_clk_pin IOSTANDARD = LVTTL; |
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| 14 | Net sys_clk_pin TNM_NET = sys_clk_pin; |
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| 15 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 ps; |
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