#FPGA Board v2.2 I/O constraints for Other I/O Devices
#
#16-bits of Digital I/O at 20-pin 0.1" header (component J20)
# 4 corner pins of 20-pin header are ground
# Bit 0 is pin 0, as labeled on the board
Net DIGITAL_IO<0> LOC = L20 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<1> LOC = J21 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<2> LOC = G20 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<3> LOC = J20 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<4> LOC = K21 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<5> LOC = F20 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<6> LOC = H20 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<7> LOC = L21 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<8> LOC = H18 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<9> LOC = H19 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<10> LOC = K19 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<11> LOC = G18 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<12> LOC = F19 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<13> LOC = L19 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<14> LOC = J19 | IOSTANDARD = LVTTL;
Net DIGITAL_IO<15> LOC = F18 | IOSTANDARD = LVTTL;
#
#RS-232 UART Interface (DB9 connector J50)
# Rx is FPGA input, Tx is FPGA output
Net UART_DB9_RX LOC = L24 | IOSTANDARD = LVCMOS25;
Net UART_DB9_TX	LOC = K24 | IOSTANDARD = LVCMOS25;
#
#USB-UART Interface (USB connector J58)
# Rx is FPGA input, Tx is FPGA output
Net UART_USB_RX	LOC = C23 | IOSTANDARD = LVTTL;
Net UART_USB_TX	LOC = AA23 | IOSTANDARD = LVTTL;