| 1 | The WARP v3 configuration CPLD code implements two functions: |
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| 2 | * SPI flash configuration: The CPLD passes through the signals for the Virtex-6 |
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| 3 | "Master SPI" configuration mode, connecting them to the 128Mb SPI flash chip. |
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| 4 | * SD card configuration: The CPLD implmenets an SPI master for reading .bin files from |
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| 5 | the SD card and writing the configuration data to the Vitex-6 via "Slave Serial" mode |
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| 6 | |
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| 7 | The code for the SD card configuration mode is based on the SPI Boot project at Open Cores |
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| 8 | (http://opencores.org/project,spi_boot). The original SPI boot source on which we based our design |
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| 9 | is included in the spi_boot_OpenCores_src subdirectory of our source folder. |
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| 10 | |
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| 11 | The source code for the WARP v3 config CPLD design is organized as: |
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| 12 | |
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| 13 | w3_cpld_sd_config.v - top-level module |
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| 14 | |-spi_boot.vhd - top-level of SPI boot core |
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| 15 | |-spi_boot_pack-p.vhd |
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| 16 | |-spi_counter.vhd |
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| 17 | |
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| 18 | Our verison of spi_boot.vhd has very minor changes realtive to the Open Cores version. Our |
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| 19 | version includes two extra lines (diff output below) to explicitly drive the FPGA's PROG |
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| 20 | signal high when the Virtex-6 state machine requires it. |
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| 21 | |
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| 22 | ==================================================================================================== |
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| 23 | Unified diff between original spi_boot.vhd and the verison used in the WARP v3 config CPLD design |
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| 24 | |
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| 25 | --- /WARP/Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot.vhd Sat Jun 23 22:44:34 2012 |
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| 26 | +++ /WARP/Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot_OpenCores_src/rtl/vhdl/spi_boot.vhd Sat Jun 23 12:28:00 2012 |
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| 27 | @@ -582,9 +582,6 @@ |
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| 28 | when WAIT_START => |
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| 29 | spi_cs_n_s <= '1'; |
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| 30 | |
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| 31 | - --POM 2012-06-23: Adding de-assertion of PROG |
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| 32 | - config_n_o <= '1'; |
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| 33 | - |
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| 34 | -- detect rising edge of start_i |
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| 35 | if start_i = '1' and start_q = '0' then |
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| 36 | -- decide which mode is requested |
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| 37 | @@ -621,9 +618,6 @@ |
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| 38 | when WAIT_INIT_HIGH => |
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| 39 | spi_cs_n_s <= '1'; |
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| 40 | |
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| 41 | - --POM 2012-06-23: Adding de-assertion of PROG |
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| 42 | - config_n_o <= '1'; |
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| 43 | - |
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| 44 | if cfg_init_n_i = '1' and cmd_finished_s then |
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| 45 | ctrl_fsm_s <= CMD18; |
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| 46 | else |
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| 47 | ==================================================================================================== |
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| 48 | |
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| 49 | |
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| 50 | Licensing: |
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| 51 | |
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| 52 | It is unclear udner which license the Open Cores spi_boot project is distributed. The source |
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| 53 | code includes a copy of the GPL v2, but the source file headers don't mention the GPL in thier |
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| 54 | copyright sections (instead they include BSD-like distribution terms). |
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| 55 | |
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| 56 | Just to be safe, we'll assume the author intended his code be distributed under the GPL v2. As such, |
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| 57 | our full config CPLD design is likewise made available under GPL v2. The Mango-owned code (w3_cpld_sd_config.v) |
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| 58 | is dual-licensed, also available under the standard WAPR license (http://warp.rice.edu/license). |
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| 59 | |
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| 60 | Our adoption of the GPL v2 for the CPLD design does not extend to any designs running in the Virtex-6 FPGA. |
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| 61 | These designs will continue to be licensed under the BSD-based WARP license (http://warp.rice.edu/license). |
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| 62 | |
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| 63 | If you have any questions or concerns, please contact Patrick Murphy at Mango (patrick [at] mangocomm.com). |
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