source: Hardware/WARP_v3/Rev1.1/Config_CPLD/Readme.txt

Last change on this file was 1799, checked in by murphpo, 9 years ago

Adding WARP v3 hardware files (schematics, FPGA pinout, configuration CPLD source)

File size: 3.1 KB
Line 
1The WARP v3 configuration CPLD code implements two functions:
2 * SPI flash configuration: The CPLD passes through the signals for the Virtex-6
3    "Master SPI" configuration mode, connecting them to the 128Mb SPI flash chip.
4 * SD card configuration: The CPLD implmenets an SPI master for reading .bin files from
5    the SD card and writing the configuration data to the Vitex-6 via "Slave Serial" mode
6
7The code for the SD card configuration mode is based on the SPI Boot project at Open Cores
8(http://opencores.org/project,spi_boot).  The original SPI boot source on which we based our design
9is included in the spi_boot_OpenCores_src subdirectory of our source folder.
10
11The source code for the WARP v3 config CPLD design is organized as:
12
13w3_cpld_sd_config.v - top-level module
14 |-spi_boot.vhd - top-level of SPI boot core
15    |-spi_boot_pack-p.vhd
16    |-spi_counter.vhd
17
18Our verison of spi_boot.vhd has very minor changes realtive to the Open Cores version. Our
19version includes two extra lines (diff output below) to explicitly drive the FPGA's PROG
20signal high when the Virtex-6 state machine requires it.
21
22====================================================================================================
23Unified diff between original spi_boot.vhd and the verison used in the WARP v3 config CPLD design
24
25--- /WARP/Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot.vhd  Sat Jun 23 22:44:34 2012
26+++ /WARP/Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot_OpenCores_src/rtl/vhdl/spi_boot.vhd  Sat Jun 23 12:28:00 2012
27@@ -582,9 +582,6 @@
28       when WAIT_START =>
29         spi_cs_n_s     <= '1';
30 
31-       --POM 2012-06-23: Adding de-assertion of PROG
32-        config_n_o   <= '1';
33-
34         -- detect rising edge of start_i
35         if start_i = '1' and start_q = '0' then
36           -- decide which mode is requested
37@@ -621,9 +618,6 @@
38       when WAIT_INIT_HIGH =>
39         spi_cs_n_s   <= '1';
40 
41-       --POM 2012-06-23: Adding de-assertion of PROG
42-        config_n_o   <= '1';
43-
44         if cfg_init_n_i = '1' and cmd_finished_s then
45           ctrl_fsm_s <= CMD18;
46         else
47====================================================================================================
48
49
50Licensing:
51
52It is unclear udner which license the Open Cores spi_boot project is distributed. The source
53code includes a copy of the GPL v2, but the source file headers don't mention the GPL in thier
54copyright sections (instead they include BSD-like distribution terms).
55
56Just to be safe, we'll assume the author intended his code be distributed under the GPL v2. As such,
57our full config CPLD design is likewise made available under GPL v2. The Mango-owned code (w3_cpld_sd_config.v)
58is dual-licensed, also available under the standard WAPR license (http://warp.rice.edu/license).
59
60Our adoption of the GPL v2 for the CPLD design does not extend to any designs running in the Virtex-6 FPGA.
61These designs will continue to be licensed under the BSD-based WARP license (http://warp.rice.edu/license).
62
63If you have any questions or concerns, please contact Patrick Murphy at Mango (patrick [at] mangocomm.com).
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