1 | ------------------------------------------------------------------------------- |
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2 | -- |
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3 | -- SD/MMC Bootloader |
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4 | -- Testbench |
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5 | -- |
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6 | -- $Id: tb.vhd 77 2009-04-01 19:53:14Z arniml $ |
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7 | -- |
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8 | -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) |
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9 | -- |
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10 | -- All rights reserved, see COPYING. |
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11 | -- |
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12 | -- Redistribution and use in source and synthezised forms, with or without |
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13 | -- modification, are permitted provided that the following conditions are met: |
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14 | -- |
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15 | -- Redistributions of source code must retain the above copyright notice, |
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16 | -- this list of conditions and the following disclaimer. |
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17 | -- |
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18 | -- Redistributions in synthesized form must reproduce the above copyright |
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19 | -- notice, this list of conditions and the following disclaimer in the |
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20 | -- documentation and/or other materials provided with the distribution. |
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21 | -- |
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22 | -- Neither the name of the author nor the names of other contributors may |
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23 | -- be used to endorse or promote products derived from this software without |
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24 | -- specific prior written permission. |
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25 | -- |
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26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
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30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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36 | -- POSSIBILITY OF SUCH DAMAGE. |
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37 | -- |
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38 | -- Please report bugs to the author, but before you do so, please |
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39 | -- make sure that this is not a derivative work and that |
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40 | -- you have the latest version of this file. |
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41 | -- |
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42 | -- The latest version of this file can be found at: |
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43 | -- http://www.opencores.org/projects.cgi/web/spi_boot/overview |
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44 | -- |
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45 | ------------------------------------------------------------------------------- |
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46 | |
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47 | entity tb is |
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48 | |
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49 | end tb; |
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50 | |
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51 | |
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52 | library ieee; |
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53 | use ieee.std_logic_1164.all; |
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54 | |
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55 | architecture behav of tb is |
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56 | |
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57 | component tb_elem |
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58 | generic ( |
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59 | chip_type_g : string := "none"; |
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60 | has_sd_card_g : integer := 1 |
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61 | ); |
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62 | port ( |
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63 | clk_i : in std_logic; |
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64 | reset_i : in std_logic; |
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65 | eos_o : out boolean |
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66 | ); |
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67 | end component; |
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68 | |
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69 | constant period_c : time := 100 ns; |
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70 | constant reset_level_c : integer := 0; |
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71 | |
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72 | signal clk_s : std_logic; |
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73 | signal reset_s : std_logic; |
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74 | |
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75 | signal eos_full_s, |
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76 | eos_mmc_s, |
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77 | eos_sd_s, |
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78 | eos_minimal_s : boolean; |
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79 | |
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80 | begin |
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81 | |
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82 | |
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83 | ----------------------------------------------------------------------------- |
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84 | -- Testbench element including full featured chip |
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85 | ----------------------------------------------------------------------------- |
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86 | tb_elem_full_b : tb_elem |
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87 | generic map ( |
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88 | chip_type_g => "Full Chip", |
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89 | has_sd_card_g => 1 |
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90 | ) |
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91 | port map ( |
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92 | clk_i => clk_s, |
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93 | reset_i => reset_s, |
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94 | eos_o => eos_full_s |
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95 | ); |
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96 | |
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97 | |
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98 | ----------------------------------------------------------------------------- |
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99 | -- Testbench element including MMC chip |
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100 | ----------------------------------------------------------------------------- |
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101 | tb_elem_mmc_b : tb_elem |
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102 | generic map ( |
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103 | chip_type_g => "MMC Chip", |
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104 | has_sd_card_g => 0 |
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105 | ) |
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106 | port map ( |
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107 | clk_i => clk_s, |
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108 | reset_i => reset_s, |
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109 | eos_o => eos_mmc_s |
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110 | ); |
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111 | |
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112 | |
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113 | ----------------------------------------------------------------------------- |
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114 | -- Testbench element including SD chip |
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115 | ----------------------------------------------------------------------------- |
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116 | tb_elem_sd_b : tb_elem |
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117 | generic map ( |
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118 | chip_type_g => "SD Chip", |
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119 | has_sd_card_g => 1 |
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120 | ) |
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121 | port map ( |
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122 | clk_i => clk_s, |
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123 | reset_i => reset_s, |
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124 | eos_o => eos_sd_s |
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125 | ); |
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126 | |
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127 | |
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128 | ----------------------------------------------------------------------------- |
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129 | -- Testbench element including cip with minimal features |
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130 | ----------------------------------------------------------------------------- |
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131 | tb_elem_minimal_b : tb_elem |
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132 | generic map ( |
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133 | chip_type_g => "Minimal Chip", |
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134 | has_sd_card_g => 0 |
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135 | ) |
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136 | port map ( |
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137 | clk_i => clk_s, |
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138 | reset_i => reset_s, |
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139 | eos_o => eos_minimal_s |
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140 | ); |
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141 | |
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142 | |
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143 | ----------------------------------------------------------------------------- |
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144 | -- Clock Generator |
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145 | ----------------------------------------------------------------------------- |
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146 | clk: process |
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147 | begin |
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148 | clk_s <= '0'; |
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149 | wait for period_c / 2; |
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150 | clk_s <= '1'; |
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151 | wait for period_c / 2; |
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152 | end process clk; |
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153 | |
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154 | |
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155 | ----------------------------------------------------------------------------- |
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156 | -- Reset Generator |
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157 | ----------------------------------------------------------------------------- |
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158 | reset: process |
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159 | begin |
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160 | if reset_level_c = 0 then |
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161 | reset_s <= '0'; |
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162 | else |
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163 | reset_s <= '1'; |
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164 | end if; |
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165 | |
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166 | wait for period_c * 4 + 10 ns; |
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167 | |
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168 | reset_s <= not reset_s; |
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169 | |
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170 | wait; |
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171 | end process reset; |
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172 | |
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173 | |
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174 | ----------------------------------------------------------------------------- |
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175 | -- End Of Simulation Detection |
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176 | ----------------------------------------------------------------------------- |
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177 | eos: process (eos_full_s, |
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178 | eos_mmc_s, |
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179 | eos_sd_s, |
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180 | eos_minimal_s) |
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181 | begin |
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182 | |
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183 | if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then |
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184 | assert false |
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185 | report "End of Simulation." |
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186 | severity failure; |
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187 | end if; |
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188 | |
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189 | end process eos; |
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190 | |
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191 | end behav; |
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