1 | ------------------------------------------------------------------------------- |
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2 | -- |
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3 | -- SD/MMC Bootloader |
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4 | -- Generic testbench element for a specific feature set |
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5 | -- |
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6 | -- $Id: tb_elem.vhd 77 2009-04-01 19:53:14Z arniml $ |
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7 | -- |
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8 | -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) |
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9 | -- |
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10 | -- All rights reserved, see COPYING. |
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11 | -- |
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12 | -- Redistribution and use in source and synthezised forms, with or without |
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13 | -- modification, are permitted provided that the following conditions are met: |
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14 | -- |
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15 | -- Redistributions of source code must retain the above copyright notice, |
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16 | -- this list of conditions and the following disclaimer. |
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17 | -- |
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18 | -- Redistributions in synthesized form must reproduce the above copyright |
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19 | -- notice, this list of conditions and the following disclaimer in the |
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20 | -- documentation and/or other materials provided with the distribution. |
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21 | -- |
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22 | -- Neither the name of the author nor the names of other contributors may |
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23 | -- be used to endorse or promote products derived from this software without |
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24 | -- specific prior written permission. |
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25 | -- |
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26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
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30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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36 | -- POSSIBILITY OF SUCH DAMAGE. |
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37 | -- |
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38 | -- Please report bugs to the author, but before you do so, please |
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39 | -- make sure that this is not a derivative work and that |
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40 | -- you have the latest version of this file. |
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41 | -- |
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42 | -- The latest version of this file can be found at: |
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43 | -- http://www.opencores.org/projects.cgi/web/spi_boot/overview |
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44 | -- |
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45 | ------------------------------------------------------------------------------- |
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46 | |
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47 | library ieee; |
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48 | use ieee.std_logic_1164.all; |
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49 | |
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50 | |
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51 | entity tb_elem is |
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52 | |
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53 | generic ( |
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54 | chip_type_g : string := "none"; |
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55 | has_sd_card_g : integer := 1 |
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56 | ); |
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57 | port ( |
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58 | clk_i : in std_logic; |
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59 | reset_i : in std_logic; |
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60 | eos_o : out boolean |
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61 | ); |
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62 | |
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63 | end tb_elem; |
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64 | |
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65 | |
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66 | library ieee; |
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67 | use ieee.numeric_std.all; |
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68 | library std; |
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69 | use std.textio.all; |
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70 | |
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71 | use work.spi_boot_pack.all; |
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72 | use work.tb_pack.all; |
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73 | |
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74 | architecture behav of tb_elem is |
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75 | |
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76 | component chip |
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77 | port ( |
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78 | clk_i : in std_logic; |
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79 | reset_i : in std_logic; |
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80 | set_sel_n_i : in std_logic_vector(3 downto 0); |
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81 | spi_clk_o : out std_logic; |
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82 | spi_cs_n_o : out std_logic; |
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83 | spi_data_in_i : in std_logic; |
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84 | spi_data_out_o : out std_logic; |
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85 | start_i : in std_logic; |
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86 | mode_i : in std_logic; |
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87 | config_n_o : out std_logic; |
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88 | detached_o : out std_logic; |
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89 | cfg_init_n_i : in std_logic; |
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90 | cfg_done_i : in std_logic; |
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91 | dat_done_i : in std_logic; |
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92 | cfg_clk_o : out std_logic; |
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93 | cfg_dat_o : out std_logic |
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94 | ); |
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95 | end component; |
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96 | |
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97 | component card |
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98 | generic ( |
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99 | card_type_g : string := "none"; |
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100 | is_sd_card_g : integer := 1 |
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101 | ); |
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102 | port ( |
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103 | spi_clk_i : in std_logic; |
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104 | spi_cs_n_i : in std_logic; |
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105 | spi_data_i : in std_logic; |
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106 | spi_data_o : out std_logic |
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107 | ); |
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108 | end component; |
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109 | |
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110 | signal reset_s : std_logic; |
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111 | |
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112 | -- SPI interface signals |
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113 | signal spi_clk_s : std_logic; |
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114 | signal spi_data_to_card_s : std_logic; |
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115 | signal spi_data_from_card_s : std_logic; |
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116 | signal spi_cs_n_s : std_logic; |
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117 | |
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118 | -- config related signals |
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119 | signal start_s : std_logic; |
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120 | signal mode_s : std_logic; |
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121 | signal config_n_s : std_logic; |
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122 | signal cfg_init_n_s : std_logic; |
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123 | signal cfg_done_s : std_logic; |
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124 | signal dat_done_s : std_logic; |
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125 | signal cfg_clk_s : std_logic; |
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126 | signal cfg_dat_s : std_logic; |
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127 | signal data_s : unsigned(7 downto 0); |
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128 | |
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129 | signal set_sel_n_s : std_logic_vector(3 downto 0); |
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130 | |
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131 | constant verbose_c : boolean := false; |
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132 | |
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133 | begin |
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134 | |
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135 | -- weak pull-ups |
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136 | spi_clk_s <= 'H'; |
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137 | spi_cs_n_s <= 'H'; |
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138 | spi_data_to_card_s <= 'H'; |
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139 | |
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140 | ----------------------------------------------------------------------------- |
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141 | -- DUT |
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142 | ----------------------------------------------------------------------------- |
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143 | dut_b : chip |
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144 | port map ( |
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145 | clk_i => clk_i, |
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146 | reset_i => reset_s, |
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147 | set_sel_n_i => set_sel_n_s, |
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148 | spi_clk_o => spi_clk_s, |
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149 | spi_cs_n_o => spi_cs_n_s, |
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150 | spi_data_in_i => spi_data_from_card_s, |
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151 | spi_data_out_o => spi_data_to_card_s, |
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152 | start_i => start_s, |
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153 | mode_i => mode_s, |
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154 | config_n_o => config_n_s, |
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155 | detached_o => open, |
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156 | cfg_init_n_i => cfg_init_n_s, |
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157 | cfg_done_i => cfg_done_s, |
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158 | dat_done_i => dat_done_s, |
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159 | cfg_clk_o => cfg_clk_s, |
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160 | cfg_dat_o => cfg_dat_s |
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161 | ); |
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162 | |
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163 | card_b : card |
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164 | generic map ( |
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165 | card_type_g => chip_type_g, |
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166 | is_sd_card_g => has_sd_card_g |
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167 | ) |
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168 | port map ( |
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169 | spi_clk_i => spi_clk_s, |
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170 | spi_cs_n_i => spi_cs_n_s, |
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171 | spi_data_i => spi_data_to_card_s, |
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172 | spi_data_o => spi_data_from_card_s |
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173 | ); |
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174 | |
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175 | |
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176 | ----------------------------------------------------------------------------- |
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177 | -- DUT Stimuli |
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178 | -- |
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179 | stim: process |
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180 | |
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181 | procedure rise_cfg_clk(num : integer) is |
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182 | begin |
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183 | for i in 1 to num loop |
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184 | wait until cfg_clk_s'event and cfg_clk_s = '1'; |
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185 | end loop; |
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186 | end rise_cfg_clk; |
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187 | |
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188 | -- procedure fall_cfg_clk(num : integer) is |
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189 | -- begin |
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190 | -- for i in 1 to num loop |
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191 | -- wait until cfg_clk_s'event and cfg_clk_s = '0'; |
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192 | -- end loop; |
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193 | -- end fall_cfg_clk; |
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194 | |
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195 | procedure rise_clk(num : integer) is |
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196 | begin |
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197 | for i in 1 to num loop |
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198 | wait until clk_i'event and clk_i = '1'; |
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199 | end loop; |
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200 | end rise_clk; |
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201 | |
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202 | procedure read_check_byte(ref : unsigned(7 downto 0)) is |
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203 | variable byte_v : unsigned(7 downto 0); |
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204 | variable dump_line : line; |
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205 | begin |
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206 | for bit in 7 downto 0 loop |
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207 | rise_cfg_clk(1); |
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208 | byte_v(bit) := cfg_dat_s; |
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209 | end loop; |
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210 | data_s <= byte_v; |
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211 | |
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212 | if byte_v /= ref then |
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213 | write(dump_line, chip_type_g); |
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214 | write(dump_line, string'(" at ")); |
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215 | write(dump_line, now); |
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216 | write(dump_line, string'(": read_check_byte failed ")); |
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217 | write(dump_line, to_integer(byte_v)); |
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218 | write(dump_line, string'(" ")); |
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219 | write(dump_line, to_integer(ref)); |
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220 | writeline(output, dump_line); |
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221 | end if; |
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222 | end read_check_byte; |
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223 | |
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224 | variable dump_line : line; |
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225 | variable addr_v : unsigned(31 downto 0); |
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226 | variable temp_v : unsigned( 7 downto 0); |
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227 | variable set_sel_v : unsigned(3 downto 0); |
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228 | |
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229 | begin |
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230 | -- default assignments |
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231 | -- these defaults show the required pull resistors |
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232 | -- except start_i as this must be pulled high for automatic start |
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233 | start_s <= '0'; |
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234 | mode_s <= '1'; |
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235 | cfg_init_n_s <= '1'; |
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236 | cfg_done_s <= '0'; |
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237 | dat_done_s <= '1'; |
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238 | data_s <= (others => '1'); |
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239 | addr_v := (others => '0'); |
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240 | eos_o <= false; |
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241 | set_sel_n_s <= (others => '1'); |
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242 | reset_s <= '0'; |
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243 | |
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244 | -- loop through some sets |
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245 | for set in 0 to 3 loop |
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246 | set_sel_v := to_unsigned(set, 4); |
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247 | addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g |
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248 | -- plus width_img_cnt_g |
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249 | set_sel_n_s <= not std_logic_vector(set_sel_v); |
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250 | |
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251 | assert not verbose_c |
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252 | report chip_type_g & ": Processing set " & to_string(set) |
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253 | severity note; |
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254 | |
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255 | wait for 100 us; |
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256 | reset_s <= '1'; |
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257 | |
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258 | assert not verbose_c |
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259 | report chip_type_g & ": Requesting image 0" |
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260 | severity note; |
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261 | |
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262 | -- signal start |
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263 | start_s <= '1'; |
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264 | mode_s <= '1'; |
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265 | cfg_done_s <= '0'; |
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266 | addr_v(19 downto 0) := (others => '0'); |
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267 | wait until config_n_s = '0'; |
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268 | -- run through configuration sequence |
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269 | rise_clk(1); |
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270 | cfg_init_n_s <= '0'; |
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271 | rise_clk(3); |
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272 | cfg_init_n_s <= '1'; |
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273 | |
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274 | -- and receive 32 bytes from image 0 |
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275 | for i in 1 to 32 loop |
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276 | temp_v := addr_v(0) & calc_crc(addr_v); |
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277 | read_check_byte(temp_v); |
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278 | addr_v := addr_v + 1; |
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279 | end loop; |
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280 | start_s <= '0'; |
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281 | cfg_done_s <= '1'; |
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282 | |
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283 | rise_clk(10); |
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284 | |
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285 | assert not verbose_c |
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286 | report chip_type_g & ": Requesting image 1" |
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287 | severity note; |
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288 | |
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289 | -- request next image |
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290 | mode_s <= '0'; |
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291 | start_s <= '1'; |
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292 | addr_v(17 downto 0) := (others => '0'); |
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293 | addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd |
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294 | dat_done_s <= '0'; |
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295 | |
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296 | -- receive another 32 bytes from image 1 |
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297 | for i in 1 to 32 loop |
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298 | temp_v := addr_v(0) & calc_crc(addr_v); |
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299 | read_check_byte(temp_v); |
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300 | addr_v := addr_v + 1; |
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301 | end loop; |
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302 | start_s <= '0'; |
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303 | dat_done_s <= '1'; |
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304 | |
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305 | |
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306 | rise_clk(10); |
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307 | |
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308 | assert not verbose_c |
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309 | report chip_type_g & ": Requesting image 2" |
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310 | severity note; |
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311 | |
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312 | -- request next image |
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313 | mode_s <= '1'; |
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314 | start_s <= '1'; |
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315 | addr_v(17 downto 0) := (others => '0'); |
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316 | addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd |
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317 | |
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318 | wait until config_n_s = '0'; |
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319 | -- run through configuration sequence |
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320 | rise_clk(1); |
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321 | cfg_done_s <= '0'; |
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322 | cfg_init_n_s <= '0'; |
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323 | rise_clk(3); |
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324 | cfg_init_n_s <= '1'; |
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325 | |
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326 | -- receive another 32 bytes from image 2 |
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327 | for i in 1 to 32 loop |
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328 | temp_v := addr_v(0) & calc_crc(addr_v); |
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329 | read_check_byte(temp_v); |
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330 | addr_v := addr_v + 1; |
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331 | end loop; |
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332 | start_s <= '0'; |
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333 | cfg_done_s <= '1'; |
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334 | |
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335 | -- give dut a chance to stop current transfer |
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336 | wait until spi_cs_n_s = '1'; |
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337 | rise_clk(10); |
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338 | |
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339 | reset_s <= '0'; |
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340 | end loop; |
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341 | |
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342 | eos_o <= true; |
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343 | wait; |
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344 | end process stim; |
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345 | -- |
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346 | ----------------------------------------------------------------------------- |
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347 | |
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348 | end behav; |
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