source: Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot_OpenCores_src/bench/vhdl/tb_rl-c.vhd

Last change on this file was 1799, checked in by murphpo, 12 years ago

Adding WARP v3 hardware files (schematics, FPGA pinout, configuration CPLD source)

File size: 577 bytes
RevLine 
[1799]1-------------------------------------------------------------------------------
2--
3-- SD/MMC Bootloader
4--
5-- $Id: tb_rl-c.vhd 77 2009-04-01 19:53:14Z arniml $
6--
7-------------------------------------------------------------------------------
8
9configuration tb_rl_behav_c0 of tb_rl is
10
11  for behav
12
13    for dut_b : chip
14      use configuration work.chip_full_c0;
15    end for;
16
17    for card_b : card
18      use configuration work.card_behav_c0;
19    end for;
20
21    for rl_b : ram_loader
22      use configuration work.ram_loader_rtl_c0;
23    end for;
24
25  end for;
26
27end tb_rl_behav_c0;
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