1 | ------------------------------------------------------------------------------- |
---|
2 | -- |
---|
3 | -- SD/MMC Bootloader |
---|
4 | -- Testbench for ram_loader |
---|
5 | -- |
---|
6 | -- $Id: tb_rl.vhd 77 2009-04-01 19:53:14Z arniml $ |
---|
7 | -- |
---|
8 | -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) |
---|
9 | -- |
---|
10 | -- All rights reserved, see COPYING. |
---|
11 | -- |
---|
12 | -- Redistribution and use in source and synthezised forms, with or without |
---|
13 | -- modification, are permitted provided that the following conditions are met: |
---|
14 | -- |
---|
15 | -- Redistributions of source code must retain the above copyright notice, |
---|
16 | -- this list of conditions and the following disclaimer. |
---|
17 | -- |
---|
18 | -- Redistributions in synthesized form must reproduce the above copyright |
---|
19 | -- notice, this list of conditions and the following disclaimer in the |
---|
20 | -- documentation and/or other materials provided with the distribution. |
---|
21 | -- |
---|
22 | -- Neither the name of the author nor the names of other contributors may |
---|
23 | -- be used to endorse or promote products derived from this software without |
---|
24 | -- specific prior written permission. |
---|
25 | -- |
---|
26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
---|
27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
---|
28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
---|
29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
---|
30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
---|
31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
---|
32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
---|
33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
---|
34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
---|
35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
---|
36 | -- POSSIBILITY OF SUCH DAMAGE. |
---|
37 | -- |
---|
38 | -- Please report bugs to the author, but before you do so, please |
---|
39 | -- make sure that this is not a derivative work and that |
---|
40 | -- you have the latest version of this file. |
---|
41 | -- |
---|
42 | -- The latest version of this file can be found at: |
---|
43 | -- http://www.opencores.org/projects.cgi/web/spi_boot/overview |
---|
44 | -- |
---|
45 | ------------------------------------------------------------------------------- |
---|
46 | |
---|
47 | entity tb_rl is |
---|
48 | |
---|
49 | end tb_rl; |
---|
50 | |
---|
51 | |
---|
52 | library ieee; |
---|
53 | use ieee.std_logic_1164.all; |
---|
54 | |
---|
55 | architecture behav of tb_rl is |
---|
56 | |
---|
57 | component chip |
---|
58 | port ( |
---|
59 | clk_i : in std_logic; |
---|
60 | reset_i : in std_logic; |
---|
61 | set_sel_n_i : in std_logic_vector(3 downto 0); |
---|
62 | spi_clk_o : out std_logic; |
---|
63 | spi_cs_n_o : out std_logic; |
---|
64 | spi_data_in_i : in std_logic; |
---|
65 | spi_data_out_o : out std_logic; |
---|
66 | start_i : in std_logic; |
---|
67 | mode_i : in std_logic; |
---|
68 | config_n_o : out std_logic; |
---|
69 | detached_o : out std_logic; |
---|
70 | cfg_init_n_i : in std_logic; |
---|
71 | cfg_done_i : in std_logic; |
---|
72 | dat_done_i : in std_logic; |
---|
73 | cfg_clk_o : out std_logic; |
---|
74 | cfg_dat_o : out std_logic |
---|
75 | ); |
---|
76 | end component; |
---|
77 | |
---|
78 | component card |
---|
79 | generic ( |
---|
80 | card_type_g : string := "none"; |
---|
81 | is_sd_card_g : integer := 1 |
---|
82 | ); |
---|
83 | port ( |
---|
84 | spi_clk_i : in std_logic; |
---|
85 | spi_cs_n_i : in std_logic; |
---|
86 | spi_data_i : in std_logic; |
---|
87 | spi_data_o : out std_logic |
---|
88 | ); |
---|
89 | end component; |
---|
90 | |
---|
91 | component ram_loader |
---|
92 | port ( |
---|
93 | clk_i : in std_logic; |
---|
94 | reset_i : in std_logic; |
---|
95 | lamp_o : out std_logic; |
---|
96 | cfg_clk_i : in std_logic; |
---|
97 | cfg_data_i : in std_logic; |
---|
98 | start_o : out std_logic; |
---|
99 | mode_o : out std_logic; |
---|
100 | done_o : out std_logic; |
---|
101 | detached_i : in std_logic; |
---|
102 | ram_addr_o : out std_logic_vector(15 downto 0); |
---|
103 | ram_data_b : out std_logic_vector( 7 downto 0); |
---|
104 | ram_ce_no : out std_logic_vector( 3 downto 0); |
---|
105 | ram_oe_no : out std_logic; |
---|
106 | ram_we_no : out std_logic |
---|
107 | ); |
---|
108 | end component; |
---|
109 | |
---|
110 | constant period_c : time := 100 ns; |
---|
111 | constant rl_period_c : time := 20 ns; |
---|
112 | constant reset_level_c : integer := 0; |
---|
113 | |
---|
114 | signal clk_s : std_logic; |
---|
115 | signal rl_clk_s: std_logic; |
---|
116 | signal reset_s : std_logic; |
---|
117 | |
---|
118 | -- SPI interface signals |
---|
119 | signal spi_clk_s : std_logic; |
---|
120 | signal spi_data_to_card_s : std_logic; |
---|
121 | signal spi_data_from_card_s : std_logic; |
---|
122 | signal spi_cs_n_s : std_logic; |
---|
123 | |
---|
124 | -- config related signals |
---|
125 | signal start_s : std_logic; |
---|
126 | signal mode_s : std_logic; |
---|
127 | signal config_n_s : std_logic; |
---|
128 | signal cfg_init_n_s : std_logic; |
---|
129 | signal cfg_done_s : std_logic; |
---|
130 | signal dat_done_s : std_logic; |
---|
131 | signal cfg_clk_s : std_logic; |
---|
132 | signal cfg_dat_s : std_logic; |
---|
133 | signal detached_s : std_logic; |
---|
134 | |
---|
135 | signal set_sel_n_s : std_logic_vector(3 downto 0); |
---|
136 | |
---|
137 | begin |
---|
138 | |
---|
139 | set_sel_n_s <= (others => '1'); |
---|
140 | cfg_init_n_s <= '1'; |
---|
141 | cfg_done_s <= '1'; |
---|
142 | |
---|
143 | ----------------------------------------------------------------------------- |
---|
144 | -- DUT |
---|
145 | ----------------------------------------------------------------------------- |
---|
146 | dut_b : chip |
---|
147 | port map ( |
---|
148 | clk_i => clk_s, |
---|
149 | reset_i => reset_s, |
---|
150 | set_sel_n_i => set_sel_n_s, |
---|
151 | spi_clk_o => spi_clk_s, |
---|
152 | spi_cs_n_o => spi_cs_n_s, |
---|
153 | spi_data_in_i => spi_data_from_card_s, |
---|
154 | spi_data_out_o => spi_data_to_card_s, |
---|
155 | start_i => start_s, |
---|
156 | mode_i => mode_s, |
---|
157 | config_n_o => config_n_s, |
---|
158 | detached_o => detached_s, |
---|
159 | cfg_init_n_i => cfg_init_n_s, |
---|
160 | cfg_done_i => cfg_done_s, |
---|
161 | dat_done_i => dat_done_s, |
---|
162 | cfg_clk_o => cfg_clk_s, |
---|
163 | cfg_dat_o => cfg_dat_s |
---|
164 | ); |
---|
165 | |
---|
166 | card_b : card |
---|
167 | generic map ( |
---|
168 | card_type_g => "Full Chip", |
---|
169 | is_sd_card_g => 1 |
---|
170 | ) |
---|
171 | port map ( |
---|
172 | spi_clk_i => spi_clk_s, |
---|
173 | spi_cs_n_i => spi_cs_n_s, |
---|
174 | spi_data_i => spi_data_to_card_s, |
---|
175 | spi_data_o => spi_data_from_card_s |
---|
176 | ); |
---|
177 | |
---|
178 | rl_b : ram_loader |
---|
179 | port map ( |
---|
180 | clk_i => rl_clk_s, |
---|
181 | reset_i => reset_s, |
---|
182 | lamp_o => open, |
---|
183 | cfg_clk_i => cfg_clk_s, |
---|
184 | cfg_data_i => cfg_dat_s, |
---|
185 | start_o => start_s, |
---|
186 | mode_o => mode_s, |
---|
187 | done_o => dat_done_s, |
---|
188 | detached_i => detached_s, |
---|
189 | ram_addr_o => open, |
---|
190 | ram_data_b => open, |
---|
191 | ram_ce_no => open, |
---|
192 | ram_oe_no => open, |
---|
193 | ram_we_no => open |
---|
194 | ); |
---|
195 | |
---|
196 | ----------------------------------------------------------------------------- |
---|
197 | -- Clock Generator |
---|
198 | ----------------------------------------------------------------------------- |
---|
199 | clk: process |
---|
200 | begin |
---|
201 | clk_s <= '0'; |
---|
202 | wait for period_c / 2; |
---|
203 | clk_s <= '1'; |
---|
204 | wait for period_c / 2; |
---|
205 | end process clk; |
---|
206 | |
---|
207 | rl_clk: process |
---|
208 | begin |
---|
209 | rl_clk_s <= '0'; |
---|
210 | wait for rl_period_c / 2; |
---|
211 | rl_clk_s <= '1'; |
---|
212 | wait for rl_period_c / 2; |
---|
213 | end process rl_clk; |
---|
214 | |
---|
215 | |
---|
216 | ----------------------------------------------------------------------------- |
---|
217 | -- Reset Generator |
---|
218 | ----------------------------------------------------------------------------- |
---|
219 | reset: process |
---|
220 | begin |
---|
221 | if reset_level_c = 0 then |
---|
222 | reset_s <= '0'; |
---|
223 | else |
---|
224 | reset_s <= '1'; |
---|
225 | end if; |
---|
226 | |
---|
227 | wait for period_c * 4 + 10 ns; |
---|
228 | |
---|
229 | reset_s <= not reset_s; |
---|
230 | |
---|
231 | wait; |
---|
232 | end process reset; |
---|
233 | |
---|
234 | |
---|
235 | ----------------------------------------------------------------------------- |
---|
236 | -- End of Simulation |
---|
237 | ----------------------------------------------------------------------------- |
---|
238 | eos: process |
---|
239 | begin |
---|
240 | wait for 4 ms; |
---|
241 | assert false |
---|
242 | report "No checks have been performed. Investigate waveforms." |
---|
243 | severity note; |
---|
244 | assert false |
---|
245 | report "End of simulation." |
---|
246 | severity failure; |
---|
247 | end process eos; |
---|
248 | |
---|
249 | end behav; |
---|