source: Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot_OpenCores_src/rtl/vhdl/chip-mmc-a.vhd

Last change on this file was 1799, checked in by murphpo, 12 years ago

Adding WARP v3 hardware files (schematics, FPGA pinout, configuration CPLD source)

File size: 5.6 KB
Line 
1-------------------------------------------------------------------------------
2--
3-- SD/MMC Bootloader
4-- Chip toplevel design with MMC feature set
5--
6-- $Id: chip-mmc-a.vhd 77 2009-04-01 19:53:14Z arniml $
7--
8-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
9--
10-- All rights reserved, see COPYING.
11--
12-- Redistribution and use in source and synthezised forms, with or without
13-- modification, are permitted provided that the following conditions are met:
14--
15-- Redistributions of source code must retain the above copyright notice,
16-- this list of conditions and the following disclaimer.
17--
18-- Redistributions in synthesized form must reproduce the above copyright
19-- notice, this list of conditions and the following disclaimer in the
20-- documentation and/or other materials provided with the distribution.
21--
22-- Neither the name of the author nor the names of other contributors may
23-- be used to endorse or promote products derived from this software without
24-- specific prior written permission.
25--
26-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
30-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36-- POSSIBILITY OF SUCH DAMAGE.
37--
38-- Please report bugs to the author, but before you do so, please
39-- make sure that this is not a derivative work and that
40-- you have the latest version of this file.
41--
42-- The latest version of this file can be found at:
43--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
44--
45-------------------------------------------------------------------------------
46
47library ieee;
48use ieee.std_logic_1164.all;
49
50
51architecture mmc of chip is
52
53  component spi_boot
54    generic (
55      width_bit_cnt_g      : integer := 6;
56      width_img_cnt_g      : integer := 2;
57      num_bits_per_img_g   : integer := 18;
58      sd_init_g            : integer := 0;
59      mmc_compat_clk_div_g : integer := 0;
60      width_mmc_clk_div_g  : integer := 0;
61      reset_level_g        : integer := 0
62    );
63    port (
64      clk_i          : in  std_logic;
65      reset_i        : in  std_logic;
66      set_sel_i      : in  std_logic_vector(31-width_img_cnt_g-num_bits_per_img_g
67                                            downto 0);
68      spi_clk_o      : out std_logic;
69      spi_cs_n_o     : out std_logic;
70      spi_data_in_i  : in  std_logic;
71      spi_data_out_o : out std_logic;
72      spi_en_outs_o  : out std_logic;
73      start_i        : in  std_logic;
74      mode_i         : in  std_logic;
75      config_n_o     : out std_logic;
76      detached_o     : out std_logic;
77      cfg_init_n_i   : in  std_logic;
78      cfg_done_i     : in  std_logic;
79      dat_done_i     : in  std_logic;
80      cfg_clk_o      : out std_logic;
81      cfg_dat_o      : out std_logic
82    );
83  end component;
84
85  signal spi_clk_s      : std_logic;
86  signal spi_cs_n_s     : std_logic;
87  signal spi_data_out_s : std_logic;
88  signal spi_en_outs_s  : std_logic;
89
90  constant width_img_cnt_c    : integer := 2;   -- 4 images
91  constant num_bits_per_img_c : integer := 18;  -- 256 kByte per image
92  constant set_sel_width_c    : integer := 31-width_img_cnt_c-num_bits_per_img_c;
93  signal   set_sel_s          : std_logic_vector(set_sel_width_c downto 0);
94
95begin
96
97  set_sel_s <= (3 => not set_sel_n_i(3),
98                2 => not set_sel_n_i(2),
99                1 => not set_sel_n_i(1),
100                0 => not set_sel_n_i(0),
101                others => '0');
102
103  spi_boot_b : spi_boot
104    generic map (
105      width_bit_cnt_g      => 12,       -- 512 bytes per block
106      width_img_cnt_g      => width_img_cnt_c,
107      num_bits_per_img_g   => num_bits_per_img_c,
108      sd_init_g            => 0,        -- no SD specific initialization
109      mmc_compat_clk_div_g => 13,       -- MMC compat 400 kHz > 10 MHz / (13*2)
110      width_mmc_clk_div_g  => 4         -- need 5 bits for MMC compat divider
111    )
112    port map (
113      clk_i                => clk_i,
114      reset_i              => reset_i,
115      set_sel_i            => set_sel_s,
116      spi_clk_o            => spi_clk_s,
117      spi_cs_n_o           => spi_cs_n_s,
118      spi_data_in_i        => spi_data_in_i,
119      spi_data_out_o       => spi_data_out_s,
120      spi_en_outs_o        => spi_en_outs_s,
121      start_i              => start_i,
122      mode_i               => mode_i,
123      config_n_o           => config_n_o,
124      detached_o           => detached_o,
125      cfg_init_n_i         => cfg_init_n_i,
126      cfg_done_i           => cfg_done_i,
127      dat_done_i           => dat_done_i,
128      cfg_clk_o            => cfg_clk_o,
129      cfg_dat_o            => cfg_dat_o
130    );
131
132  -----------------------------------------------------------------------------
133  -- Three state drivers for SPI outputs.
134  -----------------------------------------------------------------------------
135  spi_clk_o      <=   spi_clk_s
136                    when spi_en_outs_s = '1' else
137                      'Z';
138  spi_cs_n_o     <=   spi_cs_n_s
139                    when spi_en_outs_s = '1' else
140                      'Z';
141  spi_data_out_o <=   spi_data_out_s
142                    when spi_en_outs_s = '1' else
143                      'Z';
144
145end mmc;
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