source: Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_counter.vhd

Last change on this file was 1799, checked in by murphpo, 12 years ago

Adding WARP v3 hardware files (schematics, FPGA pinout, configuration CPLD source)

File size: 3.3 KB
Line 
1-------------------------------------------------------------------------------
2--
3-- SD/MMC Bootloader
4-- Generic counter module
5--
6-- $Id: spi_counter.vhd 77 2009-04-01 19:53:14Z arniml $
7--
8-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
9--
10-- All rights reserved, see COPYING.
11--
12-- Redistribution and use in source and synthezised forms, with or without
13-- modification, are permitted provided that the following conditions are met:
14--
15-- Redistributions of source code must retain the above copyright notice,
16-- this list of conditions and the following disclaimer.
17--
18-- Redistributions in synthesized form must reproduce the above copyright
19-- notice, this list of conditions and the following disclaimer in the
20-- documentation and/or other materials provided with the distribution.
21--
22-- Neither the name of the author nor the names of other contributors may
23-- be used to endorse or promote products derived from this software without
24-- specific prior written permission.
25--
26-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
30-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36-- POSSIBILITY OF SUCH DAMAGE.
37--
38-- Please report bugs to the author, but before you do so, please
39-- make sure that this is not a derivative work and that
40-- you have the latest version of this file.
41--
42-- The latest version of this file can be found at:
43--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
44--
45-------------------------------------------------------------------------------
46
47library ieee;
48use ieee.std_logic_1164.all;
49
50
51entity spi_counter is
52
53  generic (
54    cnt_width_g   : integer := 4;
55    cnt_max_g     : integer := 15
56  );
57
58  port (
59    clk_i      : in  std_logic;
60    reset_i    : in  boolean;
61    cnt_en_i   : in  boolean;
62    cnt_o      : out std_logic_vector(cnt_width_g-1 downto 0);
63    cnt_ovfl_o : out boolean
64  );
65
66end spi_counter;
67
68
69library ieee;
70use ieee.numeric_std.all;
71use work.spi_boot_pack.all;
72
73architecture rtl of spi_counter is
74
75  signal cnt_q      : unsigned(cnt_width_g-1 downto 0);
76  signal cnt_ovfl_s : boolean;
77
78begin
79
80  cnt: process (clk_i, reset_i)
81  begin
82    if reset_i then
83      cnt_q <= (others => '0');
84
85    elsif clk_i'event and clk_i = '1' then
86      if cnt_en_i then
87        if not cnt_ovfl_s then
88          cnt_q <= cnt_q + 1;
89        else
90          cnt_q <= (others => '0');
91        end if;
92      end if;
93    end if;
94  end process cnt;
95
96  cnt_ovfl_s <= cnt_q = cnt_max_g;
97
98
99  -----------------------------------------------------------------------------
100  -- Output Mapping
101  -----------------------------------------------------------------------------
102  cnt_ovfl_o <= cnt_ovfl_s;
103  cnt_o      <= std_logic_vector(cnt_q);
104
105end rtl;
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