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| 2 | NET "osc_clk" TNM_NET = osc_clk;
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| 3 | TIMESPEC TS_osc_clk = PERIOD "osc_clk" 55 MHz HIGH 50%;
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| 4 |
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| 5 | #WARP v3 rev 1.0
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| 6 | #NET "osc_clk" LOC = "P22" | IOSTANDARD = LVTTL;
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| 7 | #NET "pb" LOC = "P27" | IOSTANDARD = LVTTL;
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| 8 |
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| 9 | #WARP v3 rev 1.1
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| 10 | NET "osc_clk" LOC = "P27" | IOSTANDARD = LVTTL;
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| 11 | NET "pb" LOC = "P28" | IOSTANDARD = LVTTL;
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| 12 |
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| 13 | NET "dip_sw<0>" LOC = "P33" | IOSTANDARD = LVTTL;
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| 14 | NET "dip_sw<1>" LOC = "P32" | IOSTANDARD = LVTTL;
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| 15 | NET "dip_sw<2>" LOC = "P30" | IOSTANDARD = LVTTL;
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| 16 | NET "dip_sw<3>" LOC = "P29" | IOSTANDARD = LVTTL;
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| 17 |
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| 18 | NET "led_stat" LOC = "P13" | IOSTANDARD = LVCMOS25;
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| 19 | NET "led_error" LOC = "P12" | IOSTANDARD = LVCMOS25;
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| 20 |
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| 21 | NET "fpga_done" LOC = "P96" | IOSTANDARD = LVCMOS25;
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| 22 | NET "fpga_init" LOC = "P95" | IOSTANDARD = LVCMOS25;
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| 23 | NET "fpga_prog" LOC = "P94" | IOSTANDARD = LVCMOS25;
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| 24 | NET "fpga_m0" LOC = "P10" | IOSTANDARD = LVCMOS25;
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| 25 | NET "fpga_m1" LOC = "P8" | IOSTANDARD = LVCMOS25;
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| 26 | NET "fpga_m2" LOC = "P9" | IOSTANDARD = LVCMOS25;
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| 27 | NET "fpga_cclk" LOC = "P78" | IOSTANDARD = LVCMOS25;
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| 28 | NET "fpga_din" LOC = "P76" | IOSTANDARD = LVCMOS25;
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| 29 |
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| 30 | NET "sd_mosi" LOC = "P46" | IOSTANDARD = LVTTL;
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| 31 | NET "sd_miso" LOC = "P43" | IOSTANDARD = LVTTL;
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| 32 | NET "sd_sclk" LOC = "P44" | IOSTANDARD = LVTTL;
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| 33 | NET "sd_cs_n" LOC = "P49" | IOSTANDARD = LVTTL;
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| 34 | NET "sd_sw_det" LOC = "P41" | IOSTANDARD = LVTTL | PULLUP;
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| 35 | NET "sd_sw_prot" LOC = "P40" | IOSTANDARD = LVTTL | PULLUP;
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| 36 |
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| 37 | NET "fpga_spi_mosi" LOC = "P99" | IOSTANDARD = LVCMOS25;
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| 38 | NET "fpga_spi_fcs" LOC = "P97" | IOSTANDARD = LVCMOS25;
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| 39 |
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| 40 | NET "spi_flash_miso" LOC = "P19" | IOSTANDARD = LVTTL;
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| 41 | NET "spi_flash_clk" LOC = "P17" | IOSTANDARD = LVTTL;
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| 42 | NET "spi_flash_cs" LOC = "P18" | IOSTANDARD = LVTTL | PULLUP;
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| 43 | NET "spi_flash_mosi" LOC = "P16" | IOSTANDARD = LVTTL;
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