NET "osc_clk" TNM_NET = osc_clk;
TIMESPEC TS_osc_clk = PERIOD "osc_clk" 55 MHz HIGH 50%;

#WARP v3 rev 1.0
#NET "osc_clk" LOC = "P22" | IOSTANDARD = LVTTL;
#NET "pb" LOC = "P27" | IOSTANDARD = LVTTL;

#WARP v3 rev 1.1
NET "osc_clk" LOC = "P27" | IOSTANDARD = LVTTL;
NET "pb" LOC = "P28" | IOSTANDARD = LVTTL;

NET "dip_sw<0>" LOC = "P33" | IOSTANDARD = LVTTL;
NET "dip_sw<1>" LOC = "P32" | IOSTANDARD = LVTTL;
NET "dip_sw<2>" LOC = "P30" | IOSTANDARD = LVTTL;
NET "dip_sw<3>" LOC = "P29" | IOSTANDARD = LVTTL;

NET "led_stat" LOC = "P13" | IOSTANDARD = LVCMOS25;
NET "led_error" LOC = "P12" | IOSTANDARD = LVCMOS25;

NET "fpga_done" LOC = "P96" | IOSTANDARD = LVCMOS25;
NET "fpga_init" LOC = "P95" | IOSTANDARD = LVCMOS25;
NET "fpga_prog" LOC = "P94" | IOSTANDARD = LVCMOS25;
NET "fpga_m0" LOC = "P10" | IOSTANDARD = LVCMOS25;
NET "fpga_m1" LOC = "P8" | IOSTANDARD = LVCMOS25;
NET "fpga_m2" LOC = "P9" | IOSTANDARD = LVCMOS25;
NET "fpga_cclk" LOC = "P78" | IOSTANDARD = LVCMOS25;
NET "fpga_din" LOC = "P76" | IOSTANDARD = LVCMOS25;

NET "sd_mosi" LOC = "P46" | IOSTANDARD = LVTTL;
NET "sd_miso" LOC = "P43" | IOSTANDARD = LVTTL;
NET "sd_sclk" LOC = "P44" | IOSTANDARD = LVTTL;
NET "sd_cs_n" LOC = "P49" | IOSTANDARD = LVTTL;
NET "sd_sw_det" LOC = "P41" | IOSTANDARD = LVTTL | PULLUP;
NET "sd_sw_prot" LOC = "P40" | IOSTANDARD = LVTTL | PULLUP;

NET "fpga_spi_mosi" LOC = "P99" | IOSTANDARD = LVCMOS25;
NET "fpga_spi_fcs" LOC = "P97" | IOSTANDARD = LVCMOS25;

NET "spi_flash_miso" LOC = "P19" | IOSTANDARD = LVTTL;
NET "spi_flash_clk" LOC = "P17" | IOSTANDARD = LVTTL;
NET "spi_flash_cs" LOC = "P18" | IOSTANDARD = LVTTL | PULLUP;
NET "spi_flash_mosi" LOC = "P16" | IOSTANDARD = LVTTL;