source: PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_a/data/fmc_bb_4da_bridge_v2_1_0.mpd

###################################################################
# Copyright (c) 2013 Mango Communications
# All Rights Reserved
# This code is covered by the Rice-WARP license
# See http://warp.rice.edu/license/ for details
###################################################################

BEGIN fmc_bb_4da_bridge

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
OPTION USAGE_LEVEL = BASE_USER
OPTION DESC = Mango FMC-BB-4DA bridge
OPTION IP_GROUP = USER
OPTION RUN_NGCBUILD = FALSE
OPTION STYLE = HDL

IO_INTERFACE IO_IF = ext_dac_ports, IO_TYPE = MANGO_4DABRIDGE_V1
IO_INTERFACE IO_IF = user_ports, IO_TYPE = MANGO_4DABRIDGE_V1

PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER INCLUDE_IDELAYCTRL = 1, DT = INTEGER, RANGE = (0,1), DESC = "Include IDELAYCTRL (enable for design without any other IDELAYCTRL blocks)", VALUES = (0=FALSE, 1=TRUE), PERMIT=BASE_USER 
PARAMETER DAC_AB_CLK_ODELAY_TAPS = 31, DT = INTEGER, RANGE = (0:31), DESC = "IODELAY tap value for DAC A/B clock output delay", PERMIT=BASE_USER
PARAMETER DAC_CD_CLK_ODELAY_TAPS = 31, DT = INTEGER, RANGE = (0:31), DESC = "IODELAY tap value for DAC C/D clock output delay", PERMIT=BASE_USER

####################################################################################
## User Ports
## The user must connect sources to these ports in XPS in order to use
##  the 4DA board. The rest of the board's connections are made automatically
####################################################################################
PORT clk200 = "", DIR = I, IO_IF = user_ports, IO_IS = idelayCtrlClk, SIGIS = CLK, CLK_FREQ = 200000000

PORT sys_samp_clk = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTx, SIGIS = CLK, ASSIGNMENT = REQUIRE
PORT sys_samp_clk_90 = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTx90, SIGIS = CLK, ASSIGNMENT = REQUIRE

PORT user_DAC_A = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = user_DAC_A
PORT user_DAC_B = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = user_DAC_B

PORT user_DAC_C = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = user_DAC_C
PORT user_DAC_D = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = user_DAC_D

####
# Bridge -> Board ports
####
PORT DAC_AB_DB = "", DIR = O, VEC = [13:0], IO_IS = DAC_AB_DB, ENDIAN = LITTLE, IO_IF = ext_dac_ports
PORT DAC_CD_DB = "", DIR = O, VEC = [13:0], IO_IS = DAC_AB_DB, ENDIAN = LITTLE, IO_IF = ext_dac_ports

PORT DAC_AB_CLK = "", DIR = O, IO_IS = DAC_AB_CLK, IO_IF = ext_dac_ports
PORT DAC_CD_CLK = "", DIR = O, IO_IS = DAC_AB_CLK, IO_IF = ext_dac_ports

END