[1893] | 1 | module fmc_bb_4da_bridge |
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[1878] | 2 | ( |
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| 3 | //Ref clk for IDELAYCTRL |
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| 4 | input clk200, |
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| 5 | |
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| 6 | //Input sampling clocks - User design must provide these clock signals |
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| 7 | |
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| 8 | // sys_samp_clk_Tx requirements: |
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| 9 | // -Synchronous to and valid for capturing user_RFx_TXD ports |
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| 10 | // -Frequency must match AD9963 input data rate configuration (DAC clock / interpolation rate) |
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[1893] | 11 | input sys_samp_clk, |
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[1878] | 12 | |
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| 13 | // sys_samp_clk_Tx_90 must be 90 degree phase shift of sys_samp_clk_Tx (used to generate TXCLK output) |
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[1897] | 14 | input sys_samp_clk_90, |
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[1878] | 15 | |
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[1893] | 16 | input [0:11] user_DAC_A, |
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| 17 | input [0:11] user_DAC_B, |
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| 18 | input [0:11] user_DAC_C, |
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| 19 | input [0:11] user_DAC_D, |
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[1878] | 20 | |
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[1893] | 21 | output [0:13] DAC_AB_DB, |
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| 22 | output [0:13] DAC_CD_DB, |
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| 23 | output DAC_AB_CLK, |
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| 24 | output DAC_CD_CLK |
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[1878] | 25 | ); |
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| 26 | |
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| 27 | parameter C_FAMILY = "virtex6"; |
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| 28 | parameter INCLUDE_IDELAYCTRL = 1; |
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| 29 | |
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[1893] | 30 | parameter DAC_AB_CLK_ODELAY_TAPS = 31; |
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| 31 | parameter DAC_CD_CLK_ODELAY_TAPS = 31; |
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[1878] | 32 | |
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| 33 | generate |
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| 34 | if(INCLUDE_IDELAYCTRL==1) begin |
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| 35 | IDELAYCTRL IDELAYCTRL_inst ( |
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| 36 | .RDY(), // 1-bit Ready output |
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| 37 | .REFCLK(clk200), // 1-bit Reference clock input |
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| 38 | .RST(1'b0) // 1-bit Reset input |
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| 39 | ); |
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| 40 | end |
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| 41 | endgenerate |
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| 42 | |
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[1893] | 43 | /* DAC Clocks are delayed here to give enough separation from clock and data transitions |
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| 44 | Signal flow is: (OPADs inferred by tools, when user ties DAC_ ports to top-level ports) |
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| 45 | CLK: sys_samp_clk -> ODDR -> DAC_X_CLK_unDelayed -> ODELAY -> DAC_X_CLK PAD |
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| 46 | Data: user_DAC_X -> ODDR -> DAC_X_DB PADs |
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| 47 | */ |
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[1878] | 48 | ODDR #( |
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| 49 | .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
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| 50 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
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| 51 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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[1893] | 52 | ) OBUFDDR_DACCLK_AB ( |
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[1897] | 53 | .Q(DAC_AB_CLK), // 1-bit DDR output |
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| 54 | .C(sys_samp_clk_90), // 1-bit clock input |
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[1878] | 55 | .CE(1'b1), // 1-bit clock enable input |
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| 56 | .D1(1'b1), // 1-bit data input (positive edge) |
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| 57 | .D2(1'b0), // 1-bit data input (negative edge) |
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| 58 | .R(1'b0), // 1-bit reset |
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| 59 | .S(1'b0) // 1-bit set |
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| 60 | ); |
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| 61 | |
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| 62 | ODDR #( |
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| 63 | .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
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| 64 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
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| 65 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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[1897] | 66 | ) OBUFDDR_DACCLK_CD ( |
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| 67 | .Q(DAC_CD_CLK), // 1-bit DDR output |
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| 68 | .C(sys_samp_clk_90), // 1-bit clock input |
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[1878] | 69 | .CE(1'b1), // 1-bit clock enable input |
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| 70 | .D1(1'b1), // 1-bit data input (positive edge) |
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| 71 | .D2(1'b0), // 1-bit data input (negative edge) |
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| 72 | .R(1'b0), // 1-bit reset |
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| 73 | .S(1'b0) // 1-bit set |
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| 74 | ); |
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| 75 | |
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[1893] | 76 | //Instantiate all the DDR registers for DAC DB outputs |
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[1897] | 77 | // User-supplied 12-bit values become 12MSB of 14-bit outputs |
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| 78 | // 2 LSB tied to zero (NC on AD9116) |
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[1878] | 79 | genvar ii; |
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| 80 | generate |
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| 81 | for(ii=0; ii<12; ii=ii+1) begin: DDR_REGS_RFA_RFB |
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| 82 | ODDR #( |
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| 83 | .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
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| 84 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
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| 85 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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[1893] | 86 | ) ODDR_DAC_AB_DB ( |
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| 87 | .Q(DAC_AB_DB[ii]), // 1-bit DDR output |
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| 88 | .C(sys_samp_clk), // 1-bit clock input |
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[1878] | 89 | .CE(1'b1), // 1-bit clock enable input |
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[1893] | 90 | .D1(user_DAC_A[ii]), // 1-bit data input (positive edge) |
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| 91 | .D2(user_DAC_B[ii]), // 1-bit data input (negative edge) |
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[1878] | 92 | .R(1'b0), // 1-bit reset |
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| 93 | .S(1'b0) // 1-bit set |
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| 94 | ); |
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| 95 | ODDR #( |
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| 96 | .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
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| 97 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
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| 98 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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[1893] | 99 | ) ODDR_DAC_CD_DB ( |
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| 100 | .Q(DAC_CD_DB[ii]), // 1-bit DDR output |
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| 101 | .C(sys_samp_clk), // 1-bit clock input |
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[1878] | 102 | .CE(1'b1), // 1-bit clock enable input |
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[1893] | 103 | .D1(user_DAC_C[ii]), // 1-bit data input (positive edge) |
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| 104 | .D2(user_DAC_D[ii]), // 1-bit data input (negative edge) |
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[1878] | 105 | .R(1'b0), // 1-bit reset |
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| 106 | .S(1'b0) // 1-bit set |
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| 107 | ); |
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| 108 | end |
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| 109 | endgenerate |
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| 110 | |
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[1893] | 111 | //Just in case a 4DA board gets built with the AD9117 (14-bit DACs) in the future, ensure the 2MBS are tied low |
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| 112 | // Actual users for the AD9117 should modify this core to have 14-bit user ports (future feature, maybe) |
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| 113 | assign DAC_AB_DB[12:13] = 2'b0; |
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| 114 | assign DAC_CD_DB[12:13] = 2'b0; |
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| 115 | |
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[1878] | 116 | endmodule |
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