[1927] | 1 | ------------------------------------------------------------------------------ |
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| 2 | -- radio_controller_axi.vhd - entity/architecture pair |
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| 3 | ------------------------------------------------------------------------------ |
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| 4 | -- IMPORTANT: |
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| 5 | -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. |
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| 6 | -- |
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| 7 | -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. |
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| 8 | -- |
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| 9 | -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW |
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| 10 | -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION |
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| 11 | -- OF THE USER_LOGIC ENTITY. |
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| 12 | ------------------------------------------------------------------------------ |
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| 13 | -- |
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| 14 | -- *************************************************************************** |
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| 15 | -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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| 16 | -- ** ** |
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| 17 | -- ** Xilinx, Inc. ** |
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| 18 | -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 19 | -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 20 | -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 21 | -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 22 | -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 23 | -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 24 | -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 25 | -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 26 | -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 27 | -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 28 | -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 29 | -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 30 | -- ** FOR A PARTICULAR PURPOSE. ** |
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| 31 | -- ** ** |
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| 32 | -- *************************************************************************** |
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| 33 | -- |
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| 34 | ------------------------------------------------------------------------------ |
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| 35 | -- Filename: radio_controller_axi.vhd |
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| 36 | -- Version: 3.00.c |
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| 37 | -- Description: Top level design, instantiates library components and user logic. |
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| 38 | -- Date: Tue Feb 26 20:52:28 2013 (by Create and Import Peripheral Wizard) |
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| 39 | -- VHDL Standard: VHDL'93 |
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| 40 | ------------------------------------------------------------------------------ |
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| 41 | -- Naming Conventions: |
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| 42 | -- active low signals: "*_n" |
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| 43 | -- clock signals: "clk", "clk_div#", "clk_#x" |
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| 44 | -- reset signals: "rst", "rst_n" |
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| 45 | -- generics: "C_*" |
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| 46 | -- user defined types: "*_TYPE" |
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| 47 | -- state machine next state: "*_ns" |
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| 48 | -- state machine current state: "*_cs" |
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| 49 | -- combinatorial signals: "*_com" |
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| 50 | -- pipelined or register delay signals: "*_d#" |
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| 51 | -- counter signals: "*cnt*" |
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| 52 | -- clock enable signals: "*_ce" |
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| 53 | -- internal version of output port: "*_i" |
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| 54 | -- device pins: "*_pin" |
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| 55 | -- ports: "- Names begin with Uppercase" |
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| 56 | -- processes: "*_PROCESS" |
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| 57 | -- component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 58 | ------------------------------------------------------------------------------ |
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| 59 | |
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| 60 | library ieee; |
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| 61 | use ieee.std_logic_1164.all; |
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| 62 | use ieee.std_logic_arith.all; |
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| 63 | use ieee.std_logic_unsigned.all; |
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| 64 | |
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| 65 | library proc_common_v3_00_a; |
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| 66 | use proc_common_v3_00_a.proc_common_pkg.all; |
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| 67 | use proc_common_v3_00_a.ipif_pkg.all; |
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| 68 | |
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| 69 | library axi_lite_ipif_v1_01_a; |
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| 70 | use axi_lite_ipif_v1_01_a.axi_lite_ipif; |
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| 71 | |
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| 72 | ------------------------------------------------------------------------------ |
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| 73 | -- Entity section |
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| 74 | ------------------------------------------------------------------------------ |
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| 75 | -- Definition of Generics: |
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| 76 | -- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width |
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| 77 | -- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width |
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| 78 | -- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size |
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| 79 | -- C_USE_WSTRB -- AXI4LITE slave: Write Strobe |
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| 80 | -- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout |
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| 81 | -- C_BASEADDR -- AXI4LITE slave: base address |
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| 82 | -- C_HIGHADDR -- AXI4LITE slave: high address |
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| 83 | -- C_FAMILY -- FPGA Family |
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| 84 | -- C_NUM_REG -- Number of software accessible registers |
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| 85 | -- C_NUM_MEM -- Number of address-ranges |
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| 86 | -- C_SLV_AWIDTH -- Slave interface address bus width |
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| 87 | -- C_SLV_DWIDTH -- Slave interface data bus width |
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| 88 | -- |
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| 89 | -- Definition of Ports: |
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| 90 | -- S_AXI_ACLK -- AXI4LITE slave: Clock |
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| 91 | -- S_AXI_ARESETN -- AXI4LITE slave: Reset |
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| 92 | -- S_AXI_AWADDR -- AXI4LITE slave: Write address |
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| 93 | -- S_AXI_AWVALID -- AXI4LITE slave: Write address valid |
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| 94 | -- S_AXI_WDATA -- AXI4LITE slave: Write data |
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| 95 | -- S_AXI_WSTRB -- AXI4LITE slave: Write strobe |
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| 96 | -- S_AXI_WVALID -- AXI4LITE slave: Write data valid |
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| 97 | -- S_AXI_BREADY -- AXI4LITE slave: Response ready |
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| 98 | -- S_AXI_ARADDR -- AXI4LITE slave: Read address |
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| 99 | -- S_AXI_ARVALID -- AXI4LITE slave: Read address valid |
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| 100 | -- S_AXI_RREADY -- AXI4LITE slave: Read data ready |
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| 101 | -- S_AXI_ARREADY -- AXI4LITE slave: read addres ready |
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| 102 | -- S_AXI_RDATA -- AXI4LITE slave: Read data |
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| 103 | -- S_AXI_RRESP -- AXI4LITE slave: Read data response |
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| 104 | -- S_AXI_RVALID -- AXI4LITE slave: Read data valid |
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| 105 | -- S_AXI_WREADY -- AXI4LITE slave: Write data ready |
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| 106 | -- S_AXI_BRESP -- AXI4LITE slave: Response |
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| 107 | -- S_AXI_BVALID -- AXI4LITE slave: Resonse valid |
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| 108 | -- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready |
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| 109 | ------------------------------------------------------------------------------ |
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| 110 | |
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| 111 | entity radio_controller_axi is |
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| 112 | generic |
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| 113 | ( |
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| 114 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
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| 115 | --USER generics added here |
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| 116 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
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| 117 | |
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| 118 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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| 119 | -- Bus protocol parameters, do not add to or delete |
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| 120 | C_S_AXI_DATA_WIDTH : integer := 32; |
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| 121 | C_S_AXI_ADDR_WIDTH : integer := 32; |
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| 122 | C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; |
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| 123 | C_USE_WSTRB : integer := 0; |
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| 124 | C_DPHASE_TIMEOUT : integer := 8; |
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| 125 | C_BASEADDR : std_logic_vector := X"FFFFFFFF"; |
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| 126 | C_HIGHADDR : std_logic_vector := X"00000000"; |
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| 127 | C_FAMILY : string := "virtex6"; |
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| 128 | C_NUM_REG : integer := 1; |
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| 129 | C_NUM_MEM : integer := 1; |
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| 130 | C_SLV_AWIDTH : integer := 32; |
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| 131 | C_SLV_DWIDTH : integer := 32 |
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| 132 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 133 | ); |
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| 134 | port |
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| 135 | ( |
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| 136 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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| 137 | RFA_TxEn : out std_logic; |
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| 138 | RFB_TxEn : out std_logic; |
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| 139 | RFC_TxEn : out std_logic; |
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| 140 | RFD_TxEn : out std_logic; |
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| 141 | |
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| 142 | RFA_RxEn : out std_logic; |
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| 143 | RFB_RxEn : out std_logic; |
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| 144 | RFC_RxEn : out std_logic; |
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| 145 | RFD_RxEn : out std_logic; |
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| 146 | |
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| 147 | RFA_RxHP : out std_logic; |
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| 148 | RFB_RxHP : out std_logic; |
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| 149 | RFC_RxHP : out std_logic; |
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| 150 | RFD_RxHP : out std_logic; |
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| 151 | |
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| 152 | RFA_SHDN : out std_logic; |
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| 153 | RFB_SHDN : out std_logic; |
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| 154 | RFC_SHDN : out std_logic; |
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| 155 | RFD_SHDN : out std_logic; |
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| 156 | |
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| 157 | RFA_SPI_SCLK : out std_logic; |
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| 158 | RFB_SPI_SCLK : out std_logic; |
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| 159 | RFC_SPI_SCLK : out std_logic; |
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| 160 | RFD_SPI_SCLK : out std_logic; |
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| 161 | |
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| 162 | RFA_SPI_MOSI : out std_logic; |
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| 163 | RFB_SPI_MOSI : out std_logic; |
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| 164 | RFC_SPI_MOSI : out std_logic; |
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| 165 | RFD_SPI_MOSI : out std_logic; |
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| 166 | |
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| 167 | RFA_SPI_CSn : out std_logic; |
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| 168 | RFB_SPI_CSn : out std_logic; |
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| 169 | RFC_SPI_CSn : out std_logic; |
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| 170 | RFD_SPI_CSn : out std_logic; |
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| 171 | |
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| 172 | RFA_B : out std_logic_vector(6 downto 0); |
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| 173 | RFB_B : out std_logic_vector(6 downto 0); |
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| 174 | RFC_B : out std_logic_vector(6 downto 0); |
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| 175 | RFD_B : out std_logic_vector(6 downto 0); |
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| 176 | |
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| 177 | RFA_LD : in std_logic; |
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| 178 | RFB_LD : in std_logic; |
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| 179 | RFC_LD : in std_logic; |
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| 180 | RFD_LD : in std_logic; |
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| 181 | |
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| 182 | RFA_PAEn_24 : out std_logic; |
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| 183 | RFB_PAEn_24 : out std_logic; |
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| 184 | RFC_PAEn_24 : out std_logic; |
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| 185 | RFD_PAEn_24 : out std_logic; |
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| 186 | |
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| 187 | RFA_PAEn_5 : out std_logic; |
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| 188 | RFB_PAEn_5 : out std_logic; |
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| 189 | RFC_PAEn_5 : out std_logic; |
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| 190 | RFD_PAEn_5 : out std_logic; |
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| 191 | |
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| 192 | RFA_AntSw : out std_logic_vector(1 downto 0); |
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| 193 | RFB_AntSw : out std_logic_vector(1 downto 0); |
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| 194 | RFC_AntSw : out std_logic_vector(1 downto 0); |
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| 195 | RFD_AntSw : out std_logic_vector(1 downto 0); |
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| 196 | |
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| 197 | usr_RFA_TxEn : in std_logic; |
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| 198 | usr_RFB_TxEn : in std_logic; |
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| 199 | usr_RFC_TxEn : in std_logic; |
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| 200 | usr_RFD_TxEn : in std_logic; |
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| 201 | |
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| 202 | usr_RFA_RxEn : in std_logic; |
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| 203 | usr_RFB_RxEn : in std_logic; |
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| 204 | usr_RFC_RxEn : in std_logic; |
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| 205 | usr_RFD_RxEn : in std_logic; |
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| 206 | |
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| 207 | usr_RFA_RxHP : in std_logic; |
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| 208 | usr_RFB_RxHP : in std_logic; |
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| 209 | usr_RFC_RxHP : in std_logic; |
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| 210 | usr_RFD_RxHP : in std_logic; |
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| 211 | |
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| 212 | usr_RFA_SHDN : in std_logic; |
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| 213 | usr_RFB_SHDN : in std_logic; |
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| 214 | usr_RFC_SHDN : in std_logic; |
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| 215 | usr_RFD_SHDN : in std_logic; |
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| 216 | |
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| 217 | usr_RFA_RxGainRF : in std_logic_vector(1 downto 0); |
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| 218 | usr_RFB_RxGainRF : in std_logic_vector(1 downto 0); |
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| 219 | usr_RFC_RxGainRF : in std_logic_vector(1 downto 0); |
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| 220 | usr_RFD_RxGainRF : in std_logic_vector(1 downto 0); |
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| 221 | |
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| 222 | usr_RFA_RxGainBB : in std_logic_vector(4 downto 0); |
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| 223 | usr_RFB_RxGainBB : in std_logic_vector(4 downto 0); |
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| 224 | usr_RFC_RxGainBB : in std_logic_vector(4 downto 0); |
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| 225 | usr_RFD_RxGainBB : in std_logic_vector(4 downto 0); |
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| 226 | |
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| 227 | usr_RFA_TxGain : in std_logic_vector(5 downto 0); |
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| 228 | usr_RFB_TxGain : in std_logic_vector(5 downto 0); |
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| 229 | usr_RFC_TxGain : in std_logic_vector(5 downto 0); |
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| 230 | usr_RFD_TxGain : in std_logic_vector(5 downto 0); |
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| 231 | |
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| 232 | usr_SPI_ctrlSrc : in std_logic; |
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| 233 | usr_SPI_go : in std_logic; |
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| 234 | usr_SPI_active : out std_logic; |
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| 235 | usr_SPI_rfsel : in std_logic_vector(3 downto 0); |
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| 236 | usr_SPI_regaddr : in std_logic_vector(3 downto 0); |
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| 237 | usr_SPI_regdata : in std_logic_vector(13 downto 0); |
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| 238 | |
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| 239 | usr_RFA_PHYStart : out std_logic; |
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| 240 | usr_RFB_PHYStart : out std_logic; |
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| 241 | usr_RFC_PHYStart : out std_logic; |
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| 242 | usr_RFD_PHYStart : out std_logic; |
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| 243 | |
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| 244 | usr_any_PHYStart : out std_logic; |
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| 245 | |
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| 246 | usr_RFA_statLED_Tx : out std_logic; |
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| 247 | usr_RFA_statLED_Rx : out std_logic; |
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| 248 | usr_RFB_statLED_Tx : out std_logic; |
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| 249 | usr_RFB_statLED_Rx : out std_logic; |
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| 250 | usr_RFC_statLED_Tx : out std_logic; |
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| 251 | usr_RFC_statLED_Rx : out std_logic; |
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| 252 | usr_RFD_statLED_Tx : out std_logic; |
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| 253 | usr_RFD_statLED_Rx : out std_logic; |
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| 254 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
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| 255 | |
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| 256 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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| 257 | -- Bus protocol ports, do not add to or delete |
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| 258 | S_AXI_ACLK : in std_logic; |
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| 259 | S_AXI_ARESETN : in std_logic; |
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| 260 | S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
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| 261 | S_AXI_AWVALID : in std_logic; |
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| 262 | S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); |
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| 263 | S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); |
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| 264 | S_AXI_WVALID : in std_logic; |
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| 265 | S_AXI_BREADY : in std_logic; |
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| 266 | S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
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| 267 | S_AXI_ARVALID : in std_logic; |
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| 268 | S_AXI_RREADY : in std_logic; |
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| 269 | S_AXI_ARREADY : out std_logic; |
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| 270 | S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); |
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| 271 | S_AXI_RRESP : out std_logic_vector(1 downto 0); |
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| 272 | S_AXI_RVALID : out std_logic; |
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| 273 | S_AXI_WREADY : out std_logic; |
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| 274 | S_AXI_BRESP : out std_logic_vector(1 downto 0); |
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| 275 | S_AXI_BVALID : out std_logic; |
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| 276 | S_AXI_AWREADY : out std_logic |
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| 277 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 278 | ); |
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| 279 | |
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| 280 | attribute MAX_FANOUT : string; |
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| 281 | attribute SIGIS : string; |
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| 282 | attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; |
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| 283 | attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; |
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| 284 | attribute SIGIS of S_AXI_ACLK : signal is "Clk"; |
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| 285 | attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; |
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| 286 | end entity radio_controller_axi; |
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| 287 | |
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| 288 | ------------------------------------------------------------------------------ |
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| 289 | -- Architecture section |
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| 290 | ------------------------------------------------------------------------------ |
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| 291 | |
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| 292 | architecture IMP of radio_controller_axi is |
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| 293 | |
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| 294 | constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; |
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| 295 | |
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| 296 | constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; |
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| 297 | |
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| 298 | constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); |
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| 299 | constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; |
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| 300 | constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; |
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| 301 | |
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| 302 | constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := |
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| 303 | ( |
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| 304 | ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address |
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| 305 | ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address |
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| 306 | ); |
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| 307 | |
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| 308 | -- constant USER_SLV_NUM_REG : integer := 30;--ORIG FROM CIP |
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| 309 | constant USER_SLV_NUM_REG : integer := 64; |
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| 310 | constant USER_NUM_REG : integer := USER_SLV_NUM_REG; |
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| 311 | constant TOTAL_IPIF_CE : integer := USER_NUM_REG; |
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| 312 | |
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| 313 | constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := |
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| 314 | ( |
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| 315 | 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space |
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| 316 | ); |
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| 317 | |
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| 318 | ------------------------------------------ |
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| 319 | -- Index for CS/CE |
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| 320 | ------------------------------------------ |
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| 321 | constant USER_SLV_CS_INDEX : integer := 0; |
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| 322 | constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); |
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| 323 | |
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| 324 | constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; |
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| 325 | |
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| 326 | ------------------------------------------ |
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| 327 | -- IP Interconnect (IPIC) signal declarations |
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| 328 | ------------------------------------------ |
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| 329 | signal ipif_Bus2IP_Clk : std_logic; |
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| 330 | signal ipif_Bus2IP_Resetn : std_logic; |
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| 331 | signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
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| 332 | signal ipif_Bus2IP_RNW : std_logic; |
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| 333 | signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0); |
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| 334 | signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); |
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| 335 | signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); |
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| 336 | signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); |
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| 337 | signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); |
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| 338 | signal ipif_IP2Bus_WrAck : std_logic; |
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| 339 | signal ipif_IP2Bus_RdAck : std_logic; |
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| 340 | signal ipif_IP2Bus_Error : std_logic; |
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| 341 | signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); |
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| 342 | signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0); |
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| 343 | signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0); |
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| 344 | signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0); |
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| 345 | signal user_IP2Bus_RdAck : std_logic; |
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| 346 | signal user_IP2Bus_WrAck : std_logic; |
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| 347 | signal user_IP2Bus_Error : std_logic; |
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| 348 | |
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| 349 | ------------------------------------------ |
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| 350 | -- Component declaration for verilog user logic |
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| 351 | ------------------------------------------ |
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| 352 | component user_logic is |
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| 353 | generic |
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| 354 | ( |
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| 355 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
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| 356 | --USER generics added here |
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| 357 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
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| 358 | |
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| 359 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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| 360 | -- Bus protocol parameters, do not add to or delete |
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| 361 | -- C_NUM_REG : integer := 30;--ORIG FROM CIP |
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| 362 | C_NUM_REG : integer := 64; |
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| 363 | C_SLV_DWIDTH : integer := 32 |
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| 364 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 365 | ); |
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| 366 | port |
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| 367 | ( |
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| 368 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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| 369 | RFA_TxEn : out std_logic; |
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| 370 | RFB_TxEn : out std_logic; |
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| 371 | RFC_TxEn : out std_logic; |
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| 372 | RFD_TxEn : out std_logic; |
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| 373 | |
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| 374 | RFA_RxEn : out std_logic; |
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| 375 | RFB_RxEn : out std_logic; |
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| 376 | RFC_RxEn : out std_logic; |
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| 377 | RFD_RxEn : out std_logic; |
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| 378 | |
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| 379 | RFA_RxHP : out std_logic; |
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| 380 | RFB_RxHP : out std_logic; |
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| 381 | RFC_RxHP : out std_logic; |
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| 382 | RFD_RxHP : out std_logic; |
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| 383 | |
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| 384 | RFA_SHDN : out std_logic; |
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| 385 | RFB_SHDN : out std_logic; |
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| 386 | RFC_SHDN : out std_logic; |
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| 387 | RFD_SHDN : out std_logic; |
---|
| 388 | |
---|
| 389 | RFA_SPI_SCLK : out std_logic; |
---|
| 390 | RFB_SPI_SCLK : out std_logic; |
---|
| 391 | RFC_SPI_SCLK : out std_logic; |
---|
| 392 | RFD_SPI_SCLK : out std_logic; |
---|
| 393 | |
---|
| 394 | RFA_SPI_MOSI : out std_logic; |
---|
| 395 | RFB_SPI_MOSI : out std_logic; |
---|
| 396 | RFC_SPI_MOSI : out std_logic; |
---|
| 397 | RFD_SPI_MOSI : out std_logic; |
---|
| 398 | |
---|
| 399 | RFA_SPI_CSn : out std_logic; |
---|
| 400 | RFB_SPI_CSn : out std_logic; |
---|
| 401 | RFC_SPI_CSn : out std_logic; |
---|
| 402 | RFD_SPI_CSn : out std_logic; |
---|
| 403 | |
---|
| 404 | RFA_B : out std_logic_vector(6 downto 0); |
---|
| 405 | RFB_B : out std_logic_vector(6 downto 0); |
---|
| 406 | RFC_B : out std_logic_vector(6 downto 0); |
---|
| 407 | RFD_B : out std_logic_vector(6 downto 0); |
---|
| 408 | |
---|
| 409 | RFA_LD : in std_logic; |
---|
| 410 | RFB_LD : in std_logic; |
---|
| 411 | RFC_LD : in std_logic; |
---|
| 412 | RFD_LD : in std_logic; |
---|
| 413 | |
---|
| 414 | RFA_PAEn_24 : out std_logic; |
---|
| 415 | RFB_PAEn_24 : out std_logic; |
---|
| 416 | RFC_PAEn_24 : out std_logic; |
---|
| 417 | RFD_PAEn_24 : out std_logic; |
---|
| 418 | |
---|
| 419 | RFA_PAEn_5 : out std_logic; |
---|
| 420 | RFB_PAEn_5 : out std_logic; |
---|
| 421 | RFC_PAEn_5 : out std_logic; |
---|
| 422 | RFD_PAEn_5 : out std_logic; |
---|
| 423 | |
---|
| 424 | RFA_AntSw : out std_logic_vector(1 downto 0); |
---|
| 425 | RFB_AntSw : out std_logic_vector(1 downto 0); |
---|
| 426 | RFC_AntSw : out std_logic_vector(1 downto 0); |
---|
| 427 | RFD_AntSw : out std_logic_vector(1 downto 0); |
---|
| 428 | |
---|
| 429 | usr_RFA_TxEn : in std_logic; |
---|
| 430 | usr_RFB_TxEn : in std_logic; |
---|
| 431 | usr_RFC_TxEn : in std_logic; |
---|
| 432 | usr_RFD_TxEn : in std_logic; |
---|
| 433 | |
---|
| 434 | usr_RFA_RxEn : in std_logic; |
---|
| 435 | usr_RFB_RxEn : in std_logic; |
---|
| 436 | usr_RFC_RxEn : in std_logic; |
---|
| 437 | usr_RFD_RxEn : in std_logic; |
---|
| 438 | |
---|
| 439 | usr_RFA_RxHP : in std_logic; |
---|
| 440 | usr_RFB_RxHP : in std_logic; |
---|
| 441 | usr_RFC_RxHP : in std_logic; |
---|
| 442 | usr_RFD_RxHP : in std_logic; |
---|
| 443 | |
---|
| 444 | usr_RFA_SHDN : in std_logic; |
---|
| 445 | usr_RFB_SHDN : in std_logic; |
---|
| 446 | usr_RFC_SHDN : in std_logic; |
---|
| 447 | usr_RFD_SHDN : in std_logic; |
---|
| 448 | |
---|
| 449 | usr_RFA_RxGainRF : in std_logic_vector(1 downto 0); |
---|
| 450 | usr_RFB_RxGainRF : in std_logic_vector(1 downto 0); |
---|
| 451 | usr_RFC_RxGainRF : in std_logic_vector(1 downto 0); |
---|
| 452 | usr_RFD_RxGainRF : in std_logic_vector(1 downto 0); |
---|
| 453 | |
---|
| 454 | usr_RFA_RxGainBB : in std_logic_vector(4 downto 0); |
---|
| 455 | usr_RFB_RxGainBB : in std_logic_vector(4 downto 0); |
---|
| 456 | usr_RFC_RxGainBB : in std_logic_vector(4 downto 0); |
---|
| 457 | usr_RFD_RxGainBB : in std_logic_vector(4 downto 0); |
---|
| 458 | |
---|
| 459 | usr_RFA_TxGain : in std_logic_vector(5 downto 0); |
---|
| 460 | usr_RFB_TxGain : in std_logic_vector(5 downto 0); |
---|
| 461 | usr_RFC_TxGain : in std_logic_vector(5 downto 0); |
---|
| 462 | usr_RFD_TxGain : in std_logic_vector(5 downto 0); |
---|
| 463 | |
---|
| 464 | usr_SPI_ctrlSrc : in std_logic; |
---|
| 465 | usr_SPI_go : in std_logic; |
---|
| 466 | usr_SPI_active : out std_logic; |
---|
| 467 | usr_SPI_rfsel : in std_logic_vector(3 downto 0); |
---|
| 468 | usr_SPI_regaddr : in std_logic_vector(3 downto 0); |
---|
| 469 | usr_SPI_regdata : in std_logic_vector(13 downto 0); |
---|
| 470 | |
---|
| 471 | usr_RFA_PHYStart : out std_logic; |
---|
| 472 | usr_RFB_PHYStart : out std_logic; |
---|
| 473 | usr_RFC_PHYStart : out std_logic; |
---|
| 474 | usr_RFD_PHYStart : out std_logic; |
---|
| 475 | |
---|
| 476 | usr_any_PHYStart : out std_logic; |
---|
| 477 | |
---|
| 478 | usr_RFA_statLED_Tx : out std_logic; |
---|
| 479 | usr_RFA_statLED_Rx : out std_logic; |
---|
| 480 | usr_RFB_statLED_Tx : out std_logic; |
---|
| 481 | usr_RFB_statLED_Rx : out std_logic; |
---|
| 482 | usr_RFC_statLED_Tx : out std_logic; |
---|
| 483 | usr_RFC_statLED_Rx : out std_logic; |
---|
| 484 | usr_RFD_statLED_Tx : out std_logic; |
---|
| 485 | usr_RFD_statLED_Rx : out std_logic; |
---|
| 486 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
---|
| 487 | |
---|
| 488 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
---|
| 489 | -- Bus protocol ports, do not add to or delete |
---|
| 490 | Bus2IP_Clk : in std_logic; |
---|
| 491 | Bus2IP_Resetn : in std_logic; |
---|
| 492 | Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); |
---|
| 493 | Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); |
---|
| 494 | Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); |
---|
| 495 | Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); |
---|
| 496 | IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); |
---|
| 497 | IP2Bus_RdAck : out std_logic; |
---|
| 498 | IP2Bus_WrAck : out std_logic; |
---|
| 499 | IP2Bus_Error : out std_logic |
---|
| 500 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
---|
| 501 | ); |
---|
| 502 | end component user_logic; |
---|
| 503 | |
---|
| 504 | begin |
---|
| 505 | |
---|
| 506 | ------------------------------------------ |
---|
| 507 | -- instantiate axi_lite_ipif |
---|
| 508 | ------------------------------------------ |
---|
| 509 | AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif |
---|
| 510 | generic map |
---|
| 511 | ( |
---|
| 512 | C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH, |
---|
| 513 | C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, |
---|
| 514 | C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, |
---|
| 515 | C_USE_WSTRB => C_USE_WSTRB, |
---|
| 516 | C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, |
---|
| 517 | C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, |
---|
| 518 | C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, |
---|
| 519 | C_FAMILY => C_FAMILY |
---|
| 520 | ) |
---|
| 521 | port map |
---|
| 522 | ( |
---|
| 523 | S_AXI_ACLK => S_AXI_ACLK, |
---|
| 524 | S_AXI_ARESETN => S_AXI_ARESETN, |
---|
| 525 | S_AXI_AWADDR => S_AXI_AWADDR, |
---|
| 526 | S_AXI_AWVALID => S_AXI_AWVALID, |
---|
| 527 | S_AXI_WDATA => S_AXI_WDATA, |
---|
| 528 | S_AXI_WSTRB => S_AXI_WSTRB, |
---|
| 529 | S_AXI_WVALID => S_AXI_WVALID, |
---|
| 530 | S_AXI_BREADY => S_AXI_BREADY, |
---|
| 531 | S_AXI_ARADDR => S_AXI_ARADDR, |
---|
| 532 | S_AXI_ARVALID => S_AXI_ARVALID, |
---|
| 533 | S_AXI_RREADY => S_AXI_RREADY, |
---|
| 534 | S_AXI_ARREADY => S_AXI_ARREADY, |
---|
| 535 | S_AXI_RDATA => S_AXI_RDATA, |
---|
| 536 | S_AXI_RRESP => S_AXI_RRESP, |
---|
| 537 | S_AXI_RVALID => S_AXI_RVALID, |
---|
| 538 | S_AXI_WREADY => S_AXI_WREADY, |
---|
| 539 | S_AXI_BRESP => S_AXI_BRESP, |
---|
| 540 | S_AXI_BVALID => S_AXI_BVALID, |
---|
| 541 | S_AXI_AWREADY => S_AXI_AWREADY, |
---|
| 542 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
---|
| 543 | Bus2IP_Resetn => ipif_Bus2IP_Resetn, |
---|
| 544 | Bus2IP_Addr => ipif_Bus2IP_Addr, |
---|
| 545 | Bus2IP_RNW => ipif_Bus2IP_RNW, |
---|
| 546 | Bus2IP_BE => ipif_Bus2IP_BE, |
---|
| 547 | Bus2IP_CS => ipif_Bus2IP_CS, |
---|
| 548 | Bus2IP_RdCE => ipif_Bus2IP_RdCE, |
---|
| 549 | Bus2IP_WrCE => ipif_Bus2IP_WrCE, |
---|
| 550 | Bus2IP_Data => ipif_Bus2IP_Data, |
---|
| 551 | IP2Bus_WrAck => ipif_IP2Bus_WrAck, |
---|
| 552 | IP2Bus_RdAck => ipif_IP2Bus_RdAck, |
---|
| 553 | IP2Bus_Error => ipif_IP2Bus_Error, |
---|
| 554 | IP2Bus_Data => ipif_IP2Bus_Data |
---|
| 555 | ); |
---|
| 556 | |
---|
| 557 | ------------------------------------------ |
---|
| 558 | -- instantiate User Logic |
---|
| 559 | ------------------------------------------ |
---|
| 560 | USER_LOGIC_I : component user_logic |
---|
| 561 | generic map |
---|
| 562 | ( |
---|
| 563 | -- MAP USER GENERICS BELOW THIS LINE --------------- |
---|
| 564 | --USER generics mapped here |
---|
| 565 | -- MAP USER GENERICS ABOVE THIS LINE --------------- |
---|
| 566 | |
---|
| 567 | C_NUM_REG => USER_NUM_REG, |
---|
| 568 | C_SLV_DWIDTH => USER_SLV_DWIDTH |
---|
| 569 | ) |
---|
| 570 | port map |
---|
| 571 | ( |
---|
| 572 | -- MAP USER PORTS BELOW THIS LINE ------------------ |
---|
| 573 | RFA_TxEn => RFA_TxEn, |
---|
| 574 | RFB_TxEn => RFB_TxEn, |
---|
| 575 | RFC_TxEn => RFC_TxEn, |
---|
| 576 | RFD_TxEn => RFD_TxEn, |
---|
| 577 | |
---|
| 578 | RFA_RxEn => RFA_RxEn, |
---|
| 579 | RFB_RxEn => RFB_RxEn, |
---|
| 580 | RFC_RxEn => RFC_RxEn, |
---|
| 581 | RFD_RxEn => RFD_RxEn, |
---|
| 582 | |
---|
| 583 | RFA_RxHP => RFA_RxHP, |
---|
| 584 | RFB_RxHP => RFB_RxHP, |
---|
| 585 | RFC_RxHP => RFC_RxHP, |
---|
| 586 | RFD_RxHP => RFD_RxHP, |
---|
| 587 | |
---|
| 588 | RFA_SHDN => RFA_SHDN, |
---|
| 589 | RFB_SHDN => RFB_SHDN, |
---|
| 590 | RFC_SHDN => RFC_SHDN, |
---|
| 591 | RFD_SHDN => RFD_SHDN, |
---|
| 592 | |
---|
| 593 | RFA_SPI_SCLK => RFA_SPI_SCLK, |
---|
| 594 | RFB_SPI_SCLK => RFB_SPI_SCLK, |
---|
| 595 | RFC_SPI_SCLK => RFC_SPI_SCLK, |
---|
| 596 | RFD_SPI_SCLK => RFD_SPI_SCLK, |
---|
| 597 | |
---|
| 598 | RFA_SPI_MOSI => RFA_SPI_MOSI, |
---|
| 599 | RFB_SPI_MOSI => RFB_SPI_MOSI, |
---|
| 600 | RFC_SPI_MOSI => RFC_SPI_MOSI, |
---|
| 601 | RFD_SPI_MOSI => RFD_SPI_MOSI, |
---|
| 602 | |
---|
| 603 | RFA_SPI_CSn => RFA_SPI_CSn, |
---|
| 604 | RFB_SPI_CSn => RFB_SPI_CSn, |
---|
| 605 | RFC_SPI_CSn => RFC_SPI_CSn, |
---|
| 606 | RFD_SPI_CSn => RFD_SPI_CSn, |
---|
| 607 | |
---|
| 608 | RFA_B => RFA_B, |
---|
| 609 | RFB_B => RFB_B, |
---|
| 610 | RFC_B => RFC_B, |
---|
| 611 | RFD_B => RFD_B, |
---|
| 612 | |
---|
| 613 | RFA_LD => RFA_LD, |
---|
| 614 | RFB_LD => RFB_LD, |
---|
| 615 | RFC_LD => RFC_LD, |
---|
| 616 | RFD_LD => RFD_LD, |
---|
| 617 | |
---|
| 618 | RFA_PAEn_24 => RFA_PAEn_24, |
---|
| 619 | RFB_PAEn_24 => RFB_PAEn_24, |
---|
| 620 | RFC_PAEn_24 => RFC_PAEn_24, |
---|
| 621 | RFD_PAEn_24 => RFD_PAEn_24, |
---|
| 622 | |
---|
| 623 | RFA_PAEn_5 => RFA_PAEn_5, |
---|
| 624 | RFB_PAEn_5 => RFB_PAEn_5, |
---|
| 625 | RFC_PAEn_5 => RFC_PAEn_5, |
---|
| 626 | RFD_PAEn_5 => RFD_PAEn_5, |
---|
| 627 | |
---|
| 628 | RFA_AntSw => RFA_AntSw, |
---|
| 629 | RFB_AntSw => RFB_AntSw, |
---|
| 630 | RFC_AntSw => RFC_AntSw, |
---|
| 631 | RFD_AntSw => RFD_AntSw, |
---|
| 632 | |
---|
| 633 | usr_RFA_TxEn => usr_RFA_TxEn, |
---|
| 634 | usr_RFB_TxEn => usr_RFB_TxEn, |
---|
| 635 | usr_RFC_TxEn => usr_RFC_TxEn, |
---|
| 636 | usr_RFD_TxEn => usr_RFD_TxEn, |
---|
| 637 | |
---|
| 638 | usr_RFA_RxEn => usr_RFA_RxEn, |
---|
| 639 | usr_RFB_RxEn => usr_RFB_RxEn, |
---|
| 640 | usr_RFC_RxEn => usr_RFC_RxEn, |
---|
| 641 | usr_RFD_RxEn => usr_RFD_RxEn, |
---|
| 642 | |
---|
| 643 | usr_RFA_RxHP => usr_RFA_RxHP, |
---|
| 644 | usr_RFB_RxHP => usr_RFB_RxHP, |
---|
| 645 | usr_RFC_RxHP => usr_RFC_RxHP, |
---|
| 646 | usr_RFD_RxHP => usr_RFD_RxHP, |
---|
| 647 | |
---|
| 648 | usr_RFA_SHDN => usr_RFA_SHDN, |
---|
| 649 | usr_RFB_SHDN => usr_RFB_SHDN, |
---|
| 650 | usr_RFC_SHDN => usr_RFC_SHDN, |
---|
| 651 | usr_RFD_SHDN => usr_RFD_SHDN, |
---|
| 652 | |
---|
| 653 | usr_RFA_RxGainRF => usr_RFA_RxGainRF, |
---|
| 654 | usr_RFB_RxGainRF => usr_RFB_RxGainRF, |
---|
| 655 | usr_RFC_RxGainRF => usr_RFC_RxGainRF, |
---|
| 656 | usr_RFD_RxGainRF => usr_RFD_RxGainRF, |
---|
| 657 | |
---|
| 658 | usr_RFA_RxGainBB => usr_RFA_RxGainBB, |
---|
| 659 | usr_RFB_RxGainBB => usr_RFB_RxGainBB, |
---|
| 660 | usr_RFC_RxGainBB => usr_RFC_RxGainBB, |
---|
| 661 | usr_RFD_RxGainBB => usr_RFD_RxGainBB, |
---|
| 662 | |
---|
| 663 | usr_RFA_TxGain => usr_RFA_TxGain, |
---|
| 664 | usr_RFB_TxGain => usr_RFB_TxGain, |
---|
| 665 | usr_RFC_TxGain => usr_RFC_TxGain, |
---|
| 666 | usr_RFD_TxGain => usr_RFD_TxGain, |
---|
| 667 | |
---|
| 668 | usr_SPI_ctrlSrc => usr_SPI_ctrlSrc, |
---|
| 669 | usr_SPI_go => usr_SPI_go, |
---|
| 670 | usr_SPI_active => usr_SPI_active, |
---|
| 671 | usr_SPI_rfsel => usr_SPI_rfsel, |
---|
| 672 | usr_SPI_regaddr => usr_SPI_regaddr, |
---|
| 673 | usr_SPI_regdata => usr_SPI_regdata, |
---|
| 674 | |
---|
| 675 | usr_RFA_PHYStart => usr_RFA_PHYStart, |
---|
| 676 | usr_RFB_PHYStart => usr_RFB_PHYStart, |
---|
| 677 | usr_RFC_PHYStart => usr_RFC_PHYStart, |
---|
| 678 | usr_RFD_PHYStart => usr_RFD_PHYStart, |
---|
| 679 | |
---|
| 680 | usr_any_PHYStart => usr_any_PHYStart, |
---|
| 681 | |
---|
| 682 | usr_RFA_statLED_Tx => usr_RFA_statLED_Tx, |
---|
| 683 | usr_RFA_statLED_Rx => usr_RFA_statLED_Rx, |
---|
| 684 | usr_RFB_statLED_Tx => usr_RFB_statLED_Tx, |
---|
| 685 | usr_RFB_statLED_Rx => usr_RFB_statLED_Rx, |
---|
| 686 | usr_RFC_statLED_Tx => usr_RFC_statLED_Tx, |
---|
| 687 | usr_RFC_statLED_Rx => usr_RFC_statLED_Rx, |
---|
| 688 | usr_RFD_statLED_Tx => usr_RFD_statLED_Tx, |
---|
| 689 | usr_RFD_statLED_Rx => usr_RFD_statLED_Rx, |
---|
| 690 | -- MAP USER PORTS ABOVE THIS LINE ------------------ |
---|
| 691 | |
---|
| 692 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
---|
| 693 | Bus2IP_Resetn => ipif_Bus2IP_Resetn, |
---|
| 694 | Bus2IP_Data => ipif_Bus2IP_Data, |
---|
| 695 | Bus2IP_BE => ipif_Bus2IP_BE, |
---|
| 696 | Bus2IP_RdCE => user_Bus2IP_RdCE, |
---|
| 697 | Bus2IP_WrCE => user_Bus2IP_WrCE, |
---|
| 698 | IP2Bus_Data => user_IP2Bus_Data, |
---|
| 699 | IP2Bus_RdAck => user_IP2Bus_RdAck, |
---|
| 700 | IP2Bus_WrAck => user_IP2Bus_WrAck, |
---|
| 701 | IP2Bus_Error => user_IP2Bus_Error |
---|
| 702 | ); |
---|
| 703 | |
---|
| 704 | ------------------------------------------ |
---|
| 705 | -- connect internal signals |
---|
| 706 | ------------------------------------------ |
---|
| 707 | ipif_IP2Bus_Data <= user_IP2Bus_Data; |
---|
| 708 | ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; |
---|
| 709 | ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; |
---|
| 710 | ipif_IP2Bus_Error <= user_IP2Bus_Error; |
---|
| 711 | |
---|
| 712 | user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0); |
---|
| 713 | user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0); |
---|
| 714 | |
---|
| 715 | end IMP; |
---|