1 | ////////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// spi_top.v //// |
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4 | //// //// |
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5 | //// This file is part of the SPI IP core project //// |
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6 | //// http://www.opencores.org/projects/spi/ //// |
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7 | //// //// |
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8 | //// Author(s): //// |
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9 | //// - Simon Srot (simons@opencores.org) //// |
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10 | //// //// |
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11 | //// All additional information is avaliable in the Readme.txt //// |
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12 | //// file. //// |
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13 | //// //// |
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14 | ////////////////////////////////////////////////////////////////////// |
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15 | //// //// |
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16 | //// Copyright (C) 2002 Authors //// |
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17 | //// //// |
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18 | //// This source file may be used and distributed without //// |
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19 | //// restriction provided that this copyright statement is not //// |
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20 | //// removed from the file and that any derivative work contains //// |
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21 | //// the original copyright notice and the associated disclaimer. //// |
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22 | //// //// |
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23 | //// This source file is free software; you can redistribute it //// |
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24 | //// and/or modify it under the terms of the GNU Lesser General //// |
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25 | //// Public License as published by the Free Software Foundation; //// |
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26 | //// either version 2.1 of the License, or (at your option) any //// |
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27 | //// later version. //// |
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28 | //// //// |
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29 | //// This source is distributed in the hope that it will be //// |
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30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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32 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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33 | //// details. //// |
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34 | //// //// |
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35 | //// You should have received a copy of the GNU Lesser General //// |
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36 | //// Public License along with this source; if not, download it //// |
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37 | //// from http://www.opencores.org/lgpl.shtml //// |
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38 | //// //// |
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39 | ////////////////////////////////////////////////////////////////////// |
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40 | //// |
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41 | //// /* Modifications to spi_top.v */ |
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42 | //// /* Copyright (c) 2006 Rice University */ |
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43 | //// /* All Rights Reserved */ |
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44 | //// /* This code is covered by the Rice-WARP license */ |
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45 | //// /* See http://warp.rice.edu/license/ for details */ |
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46 | |
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47 | |
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48 | module spi_top |
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49 | ( |
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50 | // OPB signals |
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51 | opb_clk_i, opb_rst_i, |
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52 | |
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53 | // SPI registers |
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54 | reg_ctrl, reg_ss, reg_divider, reg_tx, ctrlwrite, busval, go, |
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55 | |
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56 | // SPI signals |
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57 | ss_pad_o, sclk_pad_o, mosi_pad_o |
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58 | ); |
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59 | |
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60 | parameter Tp = 1; |
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61 | |
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62 | |
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63 | |
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64 | // OPB signals |
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65 | input opb_clk_i; // master clock input |
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66 | input opb_rst_i; // synchronous active high reset |
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67 | |
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68 | // SPI registers |
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69 | input [13:0] reg_ctrl; |
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70 | input [7:0] reg_ss; |
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71 | input [3:0] reg_divider; |
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72 | input [17:0] reg_tx; |
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73 | input ctrlwrite; |
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74 | input busval; |
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75 | output go; |
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76 | |
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77 | // SPI signals |
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78 | output [8-1:0] ss_pad_o; // slave select |
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79 | output sclk_pad_o; // serial clock |
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80 | output mosi_pad_o; // master out slave in |
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81 | |
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82 | // Internal signals |
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83 | |
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84 | wire [17:0] rx; // Rx register |
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85 | wire rx_negedge; // miso is sampled on negative edge |
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86 | wire tx_negedge; // mosi is driven on negative edge |
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87 | wire [4:0] char_len; // char len |
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88 | //wire go; // go |
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89 | wire lsb; // lsb first on line |
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90 | wire ie; // interrupt enable |
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91 | wire ass; // automatic slave select |
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92 | wire spi_divider_sel; // divider register select |
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93 | wire spi_ctrl_sel; // ctrl register select |
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94 | wire [3:0] spi_tx_sel; // tx_l register select |
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95 | wire spi_ss_sel; // ss register select |
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96 | wire tip; // transfer in progress |
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97 | wire pos_edge; // recognize posedge of sclk |
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98 | wire neg_edge; // recognize negedge of sclk |
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99 | wire last_bit; // marks last character bit |
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100 | reg ctrlbitgo; |
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101 | |
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102 | |
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103 | assign rx_negedge = reg_ctrl[9]; |
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104 | assign tx_negedge = reg_ctrl[10]; |
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105 | assign go = ctrlbitgo; |
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106 | assign char_len = reg_ctrl[6:0]; |
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107 | assign lsb = reg_ctrl[11]; |
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108 | assign ie = reg_ctrl[12]; |
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109 | assign ass = reg_ctrl[13]; |
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110 | |
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111 | always @(posedge opb_clk_i or posedge opb_rst_i) |
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112 | begin |
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113 | if (opb_rst_i) |
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114 | ctrlbitgo <= #Tp 1'b0; |
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115 | else if(ctrlwrite && !tip) |
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116 | ctrlbitgo <= #Tp busval; |
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117 | else if(tip && last_bit && pos_edge) |
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118 | ctrlbitgo <= #Tp 1'b0; |
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119 | end |
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120 | |
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121 | assign ss_pad_o = ~((reg_ss & {8{tip & ass}}) | (reg_ss & {8{!ass}})); |
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122 | |
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123 | spi_clgen clgen (.clk_in(opb_clk_i), .rst(opb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), |
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124 | .divider(reg_divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), |
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125 | .neg_edge(neg_edge)); |
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126 | |
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127 | spi_shift shift (.clk(opb_clk_i), .rst(opb_rst_i), .len(char_len[5-1:0]), |
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128 | .lsb(lsb), .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), |
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129 | .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), |
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130 | .tip(tip), .last(last_bit), |
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131 | .p_in(reg_tx), .p_out(rx), |
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132 | .s_clk(sclk_pad_o), .s_out(mosi_pad_o)); |
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133 | endmodule |
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134 | |
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