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user_logic.v

Last change on this file was 1410, checked in by sgupta, 14 years ago
updated radio controller and bridge without the rate change filters
File size: 35.9 KB

Line
1	//----------------------------------------------------------------------------
2	// user_logic.vhd - module
3	//----------------------------------------------------------------------------
4	//
5	// ***************************************************************************
6	// Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
7	//
8	// Xilinx, Inc.
9	// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
10	// AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
11	// SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
12	// OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
13	// APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
14	// THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
15	// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
16	// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
17	// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
18	// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
19	// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
20	// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21	// FOR A PARTICULAR PURPOSE.
22	//
23	// ***************************************************************************
24	//
25	//----------------------------------------------------------------------------
26	// Filename: user_logic.vhd
27	// Version: 1.20.a
28	// Description: User logic module.
29	// Date: Wed Feb 06 13:11:10 2008 (by Create and Import Peripheral Wizard)
30	// Verilog Standard: Verilog-2001
31	//----------------------------------------------------------------------------
32	// Naming Conventions:
33	// active low signals: "*_n"
34	// clock signals: "clk", "clk_div#", "clk_#x"
35	// reset signals: "rst", "rst_n"
36	// generics: "C_*"
37	// user defined types: "*_TYPE"
38	// state machine next state: "*_ns"
39	// state machine current state: "*_cs"
40	// combinatorial signals: "*_com"
41	// pipelined or register delay signals: "*_d#"
42	// counter signals: "cnt"
43	// clock enable signals: "*_ce"
44	// internal version of output port: "*_i"
45	// device pins: "*_pin"
46	// ports: "- Names begin with Uppercase"
47	// processes: "*_PROCESS"
48	// component instantiations: "<ENTITY_>I_<#\|FUNC>"
49	//----------------------------------------------------------------------------
50
51	module user_logic
52	(
53	// -- ADD USER PORTS BELOW THIS LINE ---------------
54	controller_logic_clk,
55	spi_clk,
56	data_out,
57	Radio1_cs,
58	Radio2_cs,
59	Radio3_cs,
60	Radio4_cs,
61	Dac1_cs,
62	Dac2_cs,
63	Dac3_cs,
64	Dac4_cs,
65	Radio1_SHDN,
66	Radio1_TxEn,
67	Radio1_RxEn,
68	Radio1_RxHP,
69	Radio1_LD,
70	Radio1_24PA,
71	Radio1_5PA,
72	Radio1_ANTSW,
73	Radio1_LED,
74	Radio1_ADC_RX_DCS,
75	Radio1_ADC_RX_DFS,
76	Radio1_ADC_RX_OTRA,
77	Radio1_ADC_RX_OTRB,
78	Radio1_ADC_RX_PWDNA,
79	Radio1_ADC_RX_PWDNB,
80	Radio1_DIPSW,
81	Radio1_RSSI_ADC_CLAMP,
82	Radio1_RSSI_ADC_HIZ,
83	Radio1_RSSI_ADC_OTR,
84	Radio1_RSSI_ADC_SLEEP,
85	Radio1_RSSI_ADC_D,
86	Radio1_TX_DAC_PLL_LOCK,
87	Radio1_TX_DAC_RESET,
88	Radio1_SHDN_external,
89	Radio1_TxEn_external,
90	Radio1_RxEn_external,
91	Radio1_RxHP_external,
92	Radio1_TxGain,
93	Radio1_TxStart,
94	Radio2_SHDN,
95	Radio2_TxEn,
96	Radio2_RxEn,
97	Radio2_RxHP,
98	Radio2_LD,
99	Radio2_24PA,
100	Radio2_5PA,
101	Radio2_ANTSW,
102	Radio2_LED,
103	Radio2_ADC_RX_DCS,
104	Radio2_ADC_RX_DFS,
105	Radio2_ADC_RX_OTRA,
106	Radio2_ADC_RX_OTRB,
107	Radio2_ADC_RX_PWDNA,
108	Radio2_ADC_RX_PWDNB,
109	Radio2_DIPSW,
110	Radio2_RSSI_ADC_CLAMP,
111	Radio2_RSSI_ADC_HIZ,
112	Radio2_RSSI_ADC_OTR,
113	Radio2_RSSI_ADC_SLEEP,
114	Radio2_RSSI_ADC_D,
115	Radio2_TX_DAC_PLL_LOCK,
116	Radio2_TX_DAC_RESET,
117	Radio2_SHDN_external,
118	Radio2_TxEn_external,
119	Radio2_RxEn_external,
120	Radio2_RxHP_external,
121	Radio2_TxGain,
122	Radio2_TxStart,
123	Radio3_SHDN,
124	Radio3_TxEn,
125	Radio3_RxEn,
126	Radio3_RxHP,
127	Radio3_LD,
128	Radio3_24PA,
129	Radio3_5PA,
130	Radio3_ANTSW,
131	Radio3_LED,
132	Radio3_ADC_RX_DCS,
133	Radio3_ADC_RX_DFS,
134	Radio3_ADC_RX_OTRA,
135	Radio3_ADC_RX_OTRB,
136	Radio3_ADC_RX_PWDNA,
137	Radio3_ADC_RX_PWDNB,
138	Radio3_DIPSW,
139	Radio3_RSSI_ADC_CLAMP,
140	Radio3_RSSI_ADC_HIZ,
141	Radio3_RSSI_ADC_OTR,
142	Radio3_RSSI_ADC_SLEEP,
143	Radio3_RSSI_ADC_D,
144	Radio3_TX_DAC_PLL_LOCK,
145	Radio3_TX_DAC_RESET,
146	Radio3_SHDN_external,
147	Radio3_TxEn_external,
148	Radio3_RxEn_external,
149	Radio3_RxHP_external,
150	Radio3_TxGain,
151	Radio3_TxStart,
152	Radio4_SHDN,
153	Radio4_TxEn,
154	Radio4_RxEn,
155	Radio4_RxHP,
156	Radio4_LD,
157	Radio4_24PA,
158	Radio4_5PA,
159	Radio4_ANTSW,
160	Radio4_LED,
161	Radio4_ADC_RX_DCS,
162	Radio4_ADC_RX_DFS,
163	Radio4_ADC_RX_OTRA,
164	Radio4_ADC_RX_OTRB,
165	Radio4_ADC_RX_PWDNA,
166	Radio4_ADC_RX_PWDNB,
167	Radio4_DIPSW,
168	Radio4_RSSI_ADC_CLAMP,
169	Radio4_RSSI_ADC_HIZ,
170	Radio4_RSSI_ADC_OTR,
171	Radio4_RSSI_ADC_SLEEP,
172	Radio4_RSSI_ADC_D,
173	Radio4_TX_DAC_PLL_LOCK,
174	Radio4_TX_DAC_RESET,
175	Radio4_SHDN_external,
176	Radio4_TxEn_external,
177	Radio4_RxEn_external,
178	Radio4_RxHP_external,
179	Radio4_TxGain,
180	Radio4_TxStart,
181	// -- ADD USER PORTS ABOVE THIS LINE ---------------
182
183	// -- DO NOT EDIT BELOW THIS LINE ------------------
184	// -- Bus protocol ports, do not add to or delete
185	Bus2IP_Clk, // Bus to IP clock
186	Bus2IP_Reset, // Bus to IP reset
187	Bus2IP_Data, // Bus to IP data bus
188	Bus2IP_BE, // Bus to IP byte enables
189	Bus2IP_RdCE, // Bus to IP read chip enable
190	Bus2IP_WrCE, // Bus to IP write chip enable
191	IP2Bus_Data, // IP to Bus data bus
192	IP2Bus_RdAck, // IP to Bus read transfer acknowledgement
193	IP2Bus_WrAck, // IP to Bus write transfer acknowledgement
194	IP2Bus_Error // IP to Bus error response
195	// -- DO NOT EDIT ABOVE THIS LINE ------------------
196	); // user_logic
197
198	// -- ADD USER PARAMETERS BELOW THIS LINE ------------
199	// --USER parameters added here
200	// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
201
202	// -- DO NOT EDIT BELOW THIS LINE --------------------
203	// -- Bus protocol parameters, do not add to or delete
204	parameter C_SLV_DWIDTH = 32;
205	parameter C_NUM_REG = 17;
206	// -- DO NOT EDIT ABOVE THIS LINE --------------------
207
208	// -- ADD USER PORTS BELOW THIS LINE -----------------
209	output controller_logic_clk;
210	output spi_clk;
211	output data_out;
212	output Radio1_cs;
213	output Radio2_cs;
214	output Radio3_cs;
215	output Radio4_cs;
216	output Dac1_cs;
217	output Dac2_cs;
218	output Dac3_cs;
219	output Dac4_cs;
220
221	output Radio1_SHDN;
222	output Radio1_TxEn;
223	output Radio1_RxEn;
224	output Radio1_RxHP;
225	input Radio1_LD;
226	output Radio1_24PA;
227	output Radio1_5PA;
228	output [0 : 1] Radio1_ANTSW;
229	output [0 : 2] Radio1_LED;
230	output Radio1_ADC_RX_DCS;
231	output Radio1_ADC_RX_DFS;
232	input Radio1_ADC_RX_OTRA;
233	input Radio1_ADC_RX_OTRB;
234	output Radio1_ADC_RX_PWDNA;
235	output Radio1_ADC_RX_PWDNB;
236	input [0 : 3] Radio1_DIPSW;
237	output Radio1_RSSI_ADC_CLAMP;
238	output Radio1_RSSI_ADC_HIZ;
239	input Radio1_RSSI_ADC_OTR;
240	output Radio1_RSSI_ADC_SLEEP;
241	input [0 : 9] Radio1_RSSI_ADC_D;
242	input Radio1_TX_DAC_PLL_LOCK;
243	output Radio1_TX_DAC_RESET;
244	input Radio1_SHDN_external;
245	input Radio1_TxEn_external;
246	input Radio1_RxEn_external;
247	input Radio1_RxHP_external;
248	output [0 : 5] Radio1_TxGain;
249	output Radio1_TxStart;
250
251	output Radio2_SHDN;
252	output Radio2_TxEn;
253	output Radio2_RxEn;
254	output Radio2_RxHP;
255	input Radio2_LD;
256	output Radio2_24PA;
257	output Radio2_5PA;
258	output [0 : 1] Radio2_ANTSW;
259	output [0 : 2] Radio2_LED;
260	output Radio2_ADC_RX_DCS;
261	output Radio2_ADC_RX_DFS;
262	input Radio2_ADC_RX_OTRA;
263	input Radio2_ADC_RX_OTRB;
264	output Radio2_ADC_RX_PWDNA;
265	output Radio2_ADC_RX_PWDNB;
266	input [0 : 3] Radio2_DIPSW;
267	output Radio2_RSSI_ADC_CLAMP;
268	output Radio2_RSSI_ADC_HIZ;
269	input Radio2_RSSI_ADC_OTR;
270	output Radio2_RSSI_ADC_SLEEP;
271	input [0 : 9] Radio2_RSSI_ADC_D;
272	input Radio2_TX_DAC_PLL_LOCK;
273	output Radio2_TX_DAC_RESET;
274	input Radio2_SHDN_external;
275	input Radio2_TxEn_external;
276	input Radio2_RxEn_external;
277	input Radio2_RxHP_external;
278	output [0 : 5] Radio2_TxGain;
279	output Radio2_TxStart;
280
281	output Radio3_SHDN;
282	output Radio3_TxEn;
283	output Radio3_RxEn;
284	output Radio3_RxHP;
285	input Radio3_LD;
286	output Radio3_24PA;
287	output Radio3_5PA;
288	output [0 : 1] Radio3_ANTSW;
289	output [0 : 2] Radio3_LED;
290	output Radio3_ADC_RX_DCS;
291	output Radio3_ADC_RX_DFS;
292	input Radio3_ADC_RX_OTRA;
293	input Radio3_ADC_RX_OTRB;
294	output Radio3_ADC_RX_PWDNA;
295	output Radio3_ADC_RX_PWDNB;
296	input [0 : 3] Radio3_DIPSW;
297	output Radio3_RSSI_ADC_CLAMP;
298	output Radio3_RSSI_ADC_HIZ;
299	input Radio3_RSSI_ADC_OTR;
300	output Radio3_RSSI_ADC_SLEEP;
301	input [0 : 9] Radio3_RSSI_ADC_D;
302	input Radio3_TX_DAC_PLL_LOCK;
303	output Radio3_TX_DAC_RESET;
304	input Radio3_SHDN_external;
305	input Radio3_TxEn_external;
306	input Radio3_RxEn_external;
307	input Radio3_RxHP_external;
308	output [0 : 5] Radio3_TxGain;
309	output Radio3_TxStart;
310
311	output Radio4_SHDN;
312	output Radio4_TxEn;
313	output Radio4_RxEn;
314	output Radio4_RxHP;
315	input Radio4_LD;
316	output Radio4_24PA;
317	output Radio4_5PA;
318	output [0 : 1] Radio4_ANTSW;
319	output [0 : 2] Radio4_LED;
320	output Radio4_ADC_RX_DCS;
321	output Radio4_ADC_RX_DFS;
322	input Radio4_ADC_RX_OTRA;
323	input Radio4_ADC_RX_OTRB;
324	output Radio4_ADC_RX_PWDNA;
325	output Radio4_ADC_RX_PWDNB;
326	input [0 : 3] Radio4_DIPSW;
327	output Radio4_RSSI_ADC_CLAMP;
328	output Radio4_RSSI_ADC_HIZ;
329	input Radio4_RSSI_ADC_OTR;
330	output Radio4_RSSI_ADC_SLEEP;
331	input [0 : 9] Radio4_RSSI_ADC_D;
332	input Radio4_TX_DAC_PLL_LOCK;
333	output Radio4_TX_DAC_RESET;
334	input Radio4_SHDN_external;
335	input Radio4_TxEn_external;
336	input Radio4_RxEn_external;
337	input Radio4_RxHP_external;
338	output [0 : 5] Radio4_TxGain;
339	output Radio4_TxStart;// -- ADD USER PORTS ABOVE THIS LINE -----------------
340
341	// -- DO NOT EDIT BELOW THIS LINE --------------------
342	// -- Bus protocol ports, do not add to or delete
343	input Bus2IP_Clk;
344	input Bus2IP_Reset;
345	input [0 : C_SLV_DWIDTH-1] Bus2IP_Data;
346	input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE;
347	input [0 : C_NUM_REG-1] Bus2IP_RdCE;
348	input [0 : C_NUM_REG-1] Bus2IP_WrCE;
349	output [0 : C_SLV_DWIDTH-1] IP2Bus_Data;
350	output IP2Bus_RdAck;
351	output IP2Bus_WrAck;
352	output IP2Bus_Error;
353	// -- DO NOT EDIT ABOVE THIS LINE --------------------
354
355	//----------------------------------------------------------------------------
356	// Implementation
357	//----------------------------------------------------------------------------
358
359	// --USER nets declarations added here, as needed for user logic
360
361	// Nets for user logic slave model s/w accessible register example
362	reg [0 : C_SLV_DWIDTH-1] slv_reg0;
363	reg [0 : C_SLV_DWIDTH-1] slv_reg1;
364	reg [0 : C_SLV_DWIDTH-1] slv_reg2;
365	reg [0 : C_SLV_DWIDTH-1] slv_reg3;
366	reg [0 : C_SLV_DWIDTH-1] slv_reg4;
367	reg [0 : C_SLV_DWIDTH-1] slv_reg5;
368	reg [0 : C_SLV_DWIDTH-1] slv_reg6;
369	reg [0 : C_SLV_DWIDTH-1] slv_reg7;
370	reg [0 : C_SLV_DWIDTH-1] slv_reg8;
371	reg [0 : C_SLV_DWIDTH-1] slv_reg9;
372	reg [0 : C_SLV_DWIDTH-1] slv_reg10;
373	reg [0 : C_SLV_DWIDTH-1] slv_reg11;
374	reg [0 : C_SLV_DWIDTH-1] slv_reg12;
375	reg [0 : C_SLV_DWIDTH-1] slv_reg13;
376	reg [0 : C_SLV_DWIDTH-1] slv_reg14;
377	reg [0 : C_SLV_DWIDTH-1] slv_reg15;
378	reg [0 : C_SLV_DWIDTH-1] slv_reg16;
379	wire [0 : 16] slv_reg_write_sel;
380	wire [0 : 16] slv_reg_read_sel;
381	reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data;
382	wire slv_read_ack;
383	wire slv_write_ack;
384	integer byte_index, bit_index;
385
386	// Nets for SPI interface connected to user_logic
387	wire [7:0] ss_pad_o;
388	wire mytip;
389	wire [13:0] reg_ctrl;
390	wire [7:0] reg_ss;
391	wire [3:0] reg_divider;
392	wire [17:0] reg_tx;
393
394	// Intermediate signals for transmit gain state machine
395	wire Radio1_PowerAmpEnable, Radio1_swTxEn, Radio1_sw24PAEn, Radio1_sw5PAEn;
396	wire Radio2_PowerAmpEnable, Radio2_swTxEn, Radio2_sw24PAEn, Radio2_sw5PAEn;
397	wire Radio3_PowerAmpEnable, Radio3_swTxEn, Radio3_sw24PAEn, Radio3_sw5PAEn;
398	wire Radio4_PowerAmpEnable, Radio4_swTxEn, Radio4_sw24PAEn, Radio4_sw5PAEn;
399
400	// Internal signals for calculating Tx gains
401	wire [0:5] Radio1_TargetTxGain, Radio2_TargetTxGain, Radio3_TargetTxGain, Radio4_TargetTxGain;
402	wire [0:3] Radio1_TxGainStep, Radio2_TxGainStep, Radio3_TxGainStep, Radio4_TxGainStep;
403	wire [0:3] Radio1_TxGainTimeStep, Radio2_TxGainTimeStep, Radio3_TxGainTimeStep, Radio4_TxGainTimeStep;
404
405	// Internal signals setting delays used to control Tx timing
406	wire [0:7] Radio1_GainRampThresh, Radio1_PAThresh, Radio1_TxEnThresh;
407	wire [0:7] Radio2_GainRampThresh, Radio2_PAThresh, Radio2_TxEnThresh;
408	wire [0:7] Radio3_GainRampThresh, Radio3_PAThresh, Radio3_TxEnThresh;
409	wire [0:7] Radio4_GainRampThresh, Radio4_PAThresh, Radio4_TxEnThresh;
410
411	wire [0:11] Radio1_TxStartThresh, Radio2_TxStartThresh, Radio3_TxStartThresh, Radio4_TxStartThresh;
412
413	// SPI Interface signals
414	assign Radio1_cs = ss_pad_o[0];
415	assign Radio2_cs = ss_pad_o[1];
416	assign Radio3_cs = ss_pad_o[2];
417	assign Radio4_cs = ss_pad_o[3];
418	assign Dac1_cs = ss_pad_o[4];
419	assign Dac2_cs = ss_pad_o[5];
420	assign Dac3_cs = ss_pad_o[6];
421	assign Dac4_cs = ss_pad_o[7];
422
423	assign reg_ctrl = slv_reg5[18:31];
424	assign reg_divider = slv_reg6[28:31];
425	assign reg_ss = slv_reg7[24:31];
426	assign reg_tx = slv_reg8[14:31];
427
428	// Instantiate the SPI controller top-level
429	spi_top spi_top(
430	.opb_clk_i(Bus2IP_Clk),
431	.opb_rst_i(Bus2IP_Reset),
432	.reg_ctrl(reg_ctrl),
433	.reg_ss(reg_ss),
434	.reg_divider(reg_divider),
435	.reg_tx(reg_tx),
436	.ctrlwrite(Bus2IP_WrCE[5]),
437	.busval(Bus2IP_Data[23]),
438	.go(mytip),
439	.ss_pad_o(ss_pad_o),
440	.sclk_pad_o(spi_clk),
441	.mosi_pad_o(data_out)
442	);
443
444	// Copy the bus clock to the logic_clk output
445	// The bridges use this to latch the signals used here that become top-level I/O
446	assign controller_logic_clk = Bus2IP_Clk;
447
448	//// Signals and Tx state machine for Radio 1
449
450	assign Radio1_SHDN = (slv_reg0[27])?~Radio1_SHDN_external:~slv_reg0[31];
451	assign Radio1_swTxEn = (slv_reg0[19])?Radio1_TxEn_external:slv_reg0[23];
452	assign Radio1_RxEn = (slv_reg0[11])?Radio1_RxEn_external:slv_reg0[15];
453	assign Radio1_RxHP = (slv_reg0[3])?Radio1_RxHP_external:slv_reg0[7];
454
455	assign Radio1_sw24PAEn = slv_reg1[31];
456	assign Radio1_sw5PAEn = slv_reg1[27];
457
458	assign Radio1_24PA = ~(Radio1_sw24PAEn & Radio1_PowerAmpEnable); //active low output
459	assign Radio1_5PA = ~(Radio1_sw5PAEn & Radio1_PowerAmpEnable); //active low output
460
461	assign Radio1_ANTSW[0] = (slv_reg0[19])? Radio1_TxEn_external : slv_reg1[15]; //slv_reg1[15];
462	assign Radio1_ANTSW[1] = (slv_reg0[11])? Radio1_RxEn_external : ~slv_reg1[15]; //~slv_reg1[15];
463	assign Radio1_ADC_RX_DCS = slv_reg1[7];
464	assign Radio1_LED[0] = Radio1_RxEn;
465	assign Radio1_LED[1] = Radio1_TxEn;
466	assign Radio1_LED[2] = ~Radio1_LD;
467	assign Radio1_ADC_RX_PWDNA = slv_reg2[23];
468	assign Radio1_ADC_RX_PWDNB = slv_reg2[19];
469	assign Radio1_RSSI_ADC_SLEEP = slv_reg2[15];
470	assign Radio1_TX_DAC_RESET = slv_reg1[11];
471
472	assign Radio1_ADC_RX_DFS = 1'b1; //slv_reg1[3];
473	assign Radio1_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[3];
474	assign Radio1_RSSI_ADC_HIZ = 1'b0; //slv_reg2[7];
475
476	//Read the user register for programmed target Tx gain
477	assign Radio1_TargetTxGain = slv_reg9[0:5];
478
479	//Read the user regsiter for programmed Tx gain ramp increment
480	assign Radio1_TxGainStep = slv_reg9[6:9];
481
482	//Read the user register for programmed delay between gain steps
483	assign Radio1_TxGainTimeStep = slv_reg9[10:13];
484
485	//slv_reg9[28:31] available for future use
486
487	//Read the user registers for the the delays before each Tx event
488	assign Radio1_GainRampThresh = slv_reg13[0:7];
489	assign Radio1_PAThresh = slv_reg13[8:15];
490	assign Radio1_TxEnThresh = slv_reg13[16:23];
491	assign Radio1_TxStartThresh = slv_reg9[16:27];
492
493	radio_controller_TxTiming Radio1_TxTiming (
494	.clk(Bus2IP_Clk),
495	.reset(Bus2IP_Reset),
496
497	.Tx_swEnable(Radio1_swTxEn),
498
499	.TxGain_target(Radio1_TargetTxGain),
500	.TxGain_rampGainStep(Radio1_TxGainStep),
501	.TxGain_rampTimeStep(Radio1_TxGainTimeStep),
502
503	.dly_hwTxEn(Radio1_TxEnThresh),
504	.dly_TxStart(Radio1_TxStartThresh),
505	.dly_PowerAmpEn(Radio1_PAThresh),
506	.dly_RampGain(Radio1_GainRampThresh),
507
508	.hw_TxEn(Radio1_TxEn),
509	.hw_TxGain(Radio1_TxGain),
510	.hw_PAEn(Radio1_PowerAmpEnable),
511	.hw_TxStart(Radio1_TxStart)
512	);
513
514
515	//// Signals and Tx state machine for Radio 2
516
517	assign Radio2_SHDN = (slv_reg0[26])?~Radio2_SHDN_external:~slv_reg0[30];
518	assign Radio2_swTxEn = (slv_reg0[18])?Radio2_TxEn_external:slv_reg0[22];
519	assign Radio2_RxEn = (slv_reg0[10])?Radio2_RxEn_external:slv_reg0[14];
520	assign Radio2_RxHP = (slv_reg0[2])?Radio2_RxHP_external:slv_reg0[6];
521
522	assign Radio2_sw24PAEn = slv_reg1[30];
523	assign Radio2_sw5PAEn = slv_reg1[26];
524
525	assign Radio2_24PA = ~(Radio2_sw24PAEn & Radio2_PowerAmpEnable); //active low output
526	assign Radio2_5PA = ~(Radio2_sw5PAEn & Radio2_PowerAmpEnable); //active low output
527
528	assign Radio2_ANTSW[0] = (slv_reg0[18])? Radio2_TxEn_external : slv_reg1[14]; //slv_reg1[14];
529	assign Radio2_ANTSW[1] = (slv_reg0[10])? Radio2_RxEn_external : ~slv_reg1[14]; //~slv_reg1[14];
530	assign Radio2_ADC_RX_DCS = slv_reg1[6];
531	assign Radio2_LED[0] = Radio2_RxEn;
532	assign Radio2_LED[1] = Radio2_TxEn;
533	assign Radio2_LED[2] = ~Radio2_LD;
534	assign Radio2_ADC_RX_PWDNA = slv_reg2[22];
535	assign Radio2_ADC_RX_PWDNB = slv_reg2[18];
536	assign Radio2_RSSI_ADC_SLEEP = slv_reg2[14];
537	assign Radio2_TX_DAC_RESET = slv_reg1[10];
538
539	assign Radio2_ADC_RX_DFS = 1'b1; //slv_reg1[2];
540	assign Radio2_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[2];
541	assign Radio2_RSSI_ADC_HIZ = 1'b0; //slv_reg2[6];
542
543	//Read the user register for programmed target Tx gain
544	assign Radio2_TargetTxGain = slv_reg10[0:5];
545
546	//Read the user regsiter for programmed Tx gain ramp increment
547	assign Radio2_TxGainStep = slv_reg10[6:9];
548
549	//Read the user register for programmed delay between gain steps
550	assign Radio2_TxGainTimeStep = slv_reg10[10:13];
551
552	//slv_reg10[28:31] available for future use
553
554	//Read the user registers for the the delays before each Tx event
555	assign Radio2_GainRampThresh = slv_reg14[0:7];
556	assign Radio2_PAThresh = slv_reg14[8:15];
557	assign Radio2_TxEnThresh = slv_reg14[16:23];
558	assign Radio2_TxStartThresh = slv_reg10[16:27];
559
560	radio_controller_TxTiming Radio2_TxTiming (
561	.clk(Bus2IP_Clk),
562	.reset(Bus2IP_Reset),
563
564	.Tx_swEnable(Radio2_swTxEn),
565
566	.TxGain_target(Radio2_TargetTxGain),
567	.TxGain_rampGainStep(Radio2_TxGainStep),
568	.TxGain_rampTimeStep(Radio2_TxGainTimeStep),
569
570	.dly_hwTxEn(Radio2_TxEnThresh),
571	.dly_TxStart(Radio2_TxStartThresh),
572	.dly_PowerAmpEn(Radio2_PAThresh),
573	.dly_RampGain(Radio2_GainRampThresh),
574
575	.hw_TxEn(Radio2_TxEn),
576	.hw_TxGain(Radio2_TxGain),
577	.hw_PAEn(Radio2_PowerAmpEnable),
578	.hw_TxStart(Radio2_TxStart)
579	);
580
581
582	//// Signals and Tx state machine for Radio 3
583
584	assign Radio3_SHDN = (slv_reg0[25])?~Radio3_SHDN_external:~slv_reg0[29];
585	assign Radio3_swTxEn = (slv_reg0[17])?Radio3_TxEn_external:slv_reg0[21];
586	assign Radio3_RxEn = (slv_reg0[9])?Radio3_RxEn_external:slv_reg0[13];
587	assign Radio3_RxHP = (slv_reg0[1])?Radio3_RxHP_external:slv_reg0[5];
588
589	assign Radio3_sw24PAEn = slv_reg1[29];
590	assign Radio3_sw5PAEn = slv_reg1[25];
591
592	assign Radio3_24PA = ~(Radio3_sw24PAEn & Radio3_PowerAmpEnable); //active low output
593	assign Radio3_5PA = ~(Radio3_sw5PAEn & Radio3_PowerAmpEnable); //active low output
594
595	assign Radio3_ANTSW[0] = (slv_reg0[17])? Radio3_TxEn_external : slv_reg1[13]; //slv_reg1[13];
596	assign Radio3_ANTSW[1] = (slv_reg0[9])? Radio3_RxEn_external : ~slv_reg1[13]; //~slv_reg1[13];
597	assign Radio3_ADC_RX_DCS = slv_reg1[5];
598	assign Radio3_LED[0] = Radio3_RxEn;
599	assign Radio3_LED[1] = Radio3_TxEn;
600	assign Radio3_LED[2] = ~Radio3_LD;
601	assign Radio3_ADC_RX_PWDNA = slv_reg2[21];
602	assign Radio3_ADC_RX_PWDNB = slv_reg2[17];
603	assign Radio3_RSSI_ADC_SLEEP = slv_reg2[13];
604	assign Radio3_TX_DAC_RESET = slv_reg1[9];
605
606	assign Radio3_ADC_RX_DFS = 1'b1; //slv_reg1[1];
607	assign Radio3_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[1];
608	assign Radio3_RSSI_ADC_HIZ = 1'b0; //slv_reg2[5];
609
610	//Read the user register for programmed target Tx gain
611	assign Radio3_TargetTxGain = slv_reg11[0:5];
612
613	//Read the user regsiter for programmed Tx gain ramp increment
614	assign Radio3_TxGainStep = slv_reg11[6:9];
615
616	//Read the user register for programmed delay between gain steps
617	assign Radio3_TxGainTimeStep = slv_reg11[10:13];
618
619	//slv_reg11[28:31] available for future use
620
621	//Read the user registers for the the delays before each Tx event
622	assign Radio3_GainRampThresh = slv_reg15[0:7];
623	assign Radio3_PAThresh = slv_reg15[8:15];
624	assign Radio3_TxEnThresh = slv_reg15[16:23];
625	assign Radio3_TxStartThresh = slv_reg11[16:27];
626
627	radio_controller_TxTiming Radio3_TxTiming (
628	.clk(Bus2IP_Clk),
629	.reset(Bus2IP_Reset),
630
631	.Tx_swEnable(Radio3_swTxEn),
632
633	.TxGain_target(Radio3_TargetTxGain),
634	.TxGain_rampGainStep(Radio3_TxGainStep),
635	.TxGain_rampTimeStep(Radio3_TxGainTimeStep),
636
637	.dly_hwTxEn(Radio3_TxEnThresh),
638	.dly_TxStart(Radio3_TxStartThresh),
639	.dly_PowerAmpEn(Radio3_PAThresh),
640	.dly_RampGain(Radio3_GainRampThresh),
641
642	.hw_TxEn(Radio3_TxEn),
643	.hw_TxGain(Radio3_TxGain),
644	.hw_PAEn(Radio3_PowerAmpEnable),
645	.hw_TxStart(Radio3_TxStart)
646	);
647
648
649	//// Signals and Tx state machine for Radio 4
650
651	assign Radio4_SHDN = (slv_reg0[24])?~Radio4_SHDN_external:~slv_reg0[28];
652	assign Radio4_swTxEn = (slv_reg0[16])?Radio4_TxEn_external:slv_reg0[20];
653	assign Radio4_RxEn = (slv_reg0[8])?Radio4_RxEn_external:slv_reg0[12];
654	assign Radio4_RxHP = (slv_reg0[0])?Radio4_RxHP_external:slv_reg0[4];
655
656	assign Radio4_sw24PAEn = slv_reg1[28];
657	assign Radio4_sw5PAEn = slv_reg1[24];
658
659	assign Radio4_24PA = ~(Radio4_sw24PAEn & Radio4_PowerAmpEnable); //active low output
660	assign Radio4_5PA = ~(Radio4_sw5PAEn & Radio4_PowerAmpEnable); //active low output
661
662	assign Radio4_ANTSW[0] = (slv_reg0[16])? Radio4_TxEn_external : slv_reg1[12]; //slv_reg1[12];
663	assign Radio4_ANTSW[1] = (slv_reg0[8])? Radio4_RxEn_external : ~slv_reg1[12]; //~slv_reg1[12];
664	assign Radio4_ADC_RX_DCS = slv_reg1[4];
665	assign Radio4_LED[0] = Radio4_RxEn;
666	assign Radio4_LED[1] = Radio4_TxEn;
667	assign Radio4_LED[2] = ~Radio4_LD;
668	assign Radio4_ADC_RX_PWDNA = slv_reg2[20];
669	assign Radio4_ADC_RX_PWDNB = slv_reg2[16];
670	assign Radio4_RSSI_ADC_SLEEP = slv_reg2[12];
671	assign Radio4_TX_DAC_RESET = slv_reg1[8];
672
673	assign Radio4_ADC_RX_DFS = 1'b1; //slv_reg1[0];
674	assign Radio4_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[0];
675	assign Radio4_RSSI_ADC_HIZ = 1'b0; //slv_reg2[4];
676
677	//Read the user register for programmed target Tx gain
678	assign Radio4_TargetTxGain = slv_reg12[0:5];
679
680	//Read the user regsiter for programmed Tx gain ramp increment
681	assign Radio4_TxGainStep = slv_reg12[6:9];
682
683	//Read the user register for programmed delay between gain steps
684	assign Radio4_TxGainTimeStep = slv_reg12[10:13];
685
686	//slv_reg12[28:31] available for future use
687
688	//Read the user registers for the the delays before each Tx event
689	assign Radio4_GainRampThresh = slv_reg16[0:7];
690	assign Radio4_PAThresh = slv_reg16[8:15];
691	assign Radio4_TxEnThresh = slv_reg16[16:23];
692	assign Radio4_TxStartThresh = slv_reg12[16:27];
693
694	radio_controller_TxTiming Radio4_TxTiming (
695	.clk(Bus2IP_Clk),
696	.reset(Bus2IP_Reset),
697
698	.Tx_swEnable(Radio4_swTxEn),
699
700	.TxGain_target(Radio4_TargetTxGain),
701	.TxGain_rampGainStep(Radio4_TxGainStep),
702	.TxGain_rampTimeStep(Radio4_TxGainTimeStep),
703
704	.dly_hwTxEn(Radio4_TxEnThresh),
705	.dly_TxStart(Radio4_TxStartThresh),
706	.dly_PowerAmpEn(Radio4_PAThresh),
707	.dly_RampGain(Radio4_GainRampThresh),
708
709	.hw_TxEn(Radio4_TxEn),
710	.hw_TxGain(Radio4_TxGain),
711	.hw_PAEn(Radio4_PowerAmpEnable),
712	.hw_TxStart(Radio4_TxStart)
713	);
714
715	assign
716	slv_reg_write_sel = Bus2IP_WrCE[0:16],
717	slv_reg_read_sel = Bus2IP_RdCE[0:16],
718	slv_write_ack = Bus2IP_WrCE[0] \|\| Bus2IP_WrCE[1] \|\| Bus2IP_WrCE[2] \|\| Bus2IP_WrCE[3] \|\| Bus2IP_WrCE[4] \|\| Bus2IP_WrCE[5] \|\| Bus2IP_WrCE[6] \|\| Bus2IP_WrCE[7] \|\| Bus2IP_WrCE[8] \|\| Bus2IP_WrCE[9] \|\| Bus2IP_WrCE[10] \|\| Bus2IP_WrCE[11] \|\| Bus2IP_WrCE[12] \|\| Bus2IP_WrCE[13] \|\| Bus2IP_WrCE[14] \|\| Bus2IP_WrCE[15] \|\| Bus2IP_WrCE[16],
719	slv_read_ack = Bus2IP_RdCE[0] \|\| Bus2IP_RdCE[1] \|\| Bus2IP_RdCE[2] \|\| Bus2IP_RdCE[3] \|\| Bus2IP_RdCE[4] \|\| Bus2IP_RdCE[5] \|\| Bus2IP_RdCE[6] \|\| Bus2IP_RdCE[7] \|\| Bus2IP_RdCE[8] \|\| Bus2IP_RdCE[9] \|\| Bus2IP_RdCE[10] \|\| Bus2IP_RdCE[11] \|\| Bus2IP_RdCE[12] \|\| Bus2IP_RdCE[13] \|\| Bus2IP_RdCE[14] \|\| Bus2IP_RdCE[15] \|\| Bus2IP_RdCE[16];
720
721	// implement slave model register(s)
722	always @( posedge Bus2IP_Clk )
723	begin: SLAVE_REG_WRITE_PROC
724
725	if ( Bus2IP_Reset == 1 )
726	begin
727	slv_reg0 <= 0;
728	slv_reg1 <= 0;
729	slv_reg2 <= 0;
730	slv_reg3 <= 0;
731	slv_reg4 <= 0;
732	slv_reg5 <= 0;
733	slv_reg6 <= 0;
734	slv_reg7 <= 0;
735	slv_reg8 <= 0;
736	slv_reg9 <= {14'h3fff, 22'h0}; //Gain increment, targets & delays all default to max values
737	slv_reg10 <= {14'h3fff, 22'h0};
738	slv_reg11 <= {14'h3fff, 22'h0};
739	slv_reg12 <= {14'h3fff, 22'h0};
740	slv_reg13 <= 0;
741	slv_reg14 <= 0;
742	slv_reg15 <= 0;
743	slv_reg16 <= 0;
744	end
745	else
746	case ( slv_reg_write_sel )
747	17'b10000000000000000 :
748	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
749	if ( Bus2IP_BE[byte_index] == 1 )
750	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
751	slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
752	17'b01000000000000000 :
753	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
754	if ( Bus2IP_BE[byte_index] == 1 )
755	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
756	slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
757	17'b00100000000000000 :
758	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
759	if ( Bus2IP_BE[byte_index] == 1 )
760	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
761	slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
762	17'b00010000000000000 :
763	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
764	if ( Bus2IP_BE[byte_index] == 1 )
765	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
766	slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
767	17'b00001000000000000 :
768	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
769	if ( Bus2IP_BE[byte_index] == 1 )
770	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
771	slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
772	17'b00000100000000000 :
773	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
774	if ( Bus2IP_BE[byte_index] == 1 )
775	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
776	slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
777	17'b00000010000000000 :
778	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
779	if ( Bus2IP_BE[byte_index] == 1 )
780	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
781	slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
782	17'b00000001000000000 :
783	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
784	if ( Bus2IP_BE[byte_index] == 1 )
785	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
786	slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
787	17'b00000000100000000 :
788	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
789	if ( Bus2IP_BE[byte_index] == 1 )
790	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
791	slv_reg8[bit_index] <= Bus2IP_Data[bit_index];
792	17'b00000000010000000 :
793	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
794	if ( Bus2IP_BE[byte_index] == 1 )
795	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
796	slv_reg9[bit_index] <= Bus2IP_Data[bit_index];
797	17'b00000000001000000 :
798	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
799	if ( Bus2IP_BE[byte_index] == 1 )
800	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
801	slv_reg10[bit_index] <= Bus2IP_Data[bit_index];
802	17'b00000000000100000 :
803	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
804	if ( Bus2IP_BE[byte_index] == 1 )
805	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
806	slv_reg11[bit_index] <= Bus2IP_Data[bit_index];
807	17'b00000000000010000 :
808	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
809	if ( Bus2IP_BE[byte_index] == 1 )
810	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
811	slv_reg12[bit_index] <= Bus2IP_Data[bit_index];
812	17'b00000000000001000 :
813	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
814	if ( Bus2IP_BE[byte_index] == 1 )
815	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
816	slv_reg13[bit_index] <= Bus2IP_Data[bit_index];
817	17'b00000000000000100 :
818	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
819	if ( Bus2IP_BE[byte_index] == 1 )
820	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
821	slv_reg14[bit_index] <= Bus2IP_Data[bit_index];
822	17'b00000000000000010 :
823	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
824	if ( Bus2IP_BE[byte_index] == 1 )
825	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
826	slv_reg15[bit_index] <= Bus2IP_Data[bit_index];
827	17'b00000000000000001 :
828	for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
829	if ( Bus2IP_BE[byte_index] == 1 )
830	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
831	slv_reg16[bit_index] <= Bus2IP_Data[bit_index];
832	default : ;
833	endcase
834
835	end // SLAVE_REG_WRITE_PROC
836
837	// implement slave model register read mux
838	always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 or slv_reg16 )
839	begin: SLAVE_REG_READ_PROC
840
841	case ( slv_reg_read_sel )
842	17'b10000000000000000 : slv_ip2bus_data <= slv_reg0;
843	17'b01000000000000000 : slv_ip2bus_data <= {Radio4_ADC_RX_DFS,
844	Radio3_ADC_RX_DFS,
845	Radio2_ADC_RX_DFS,
846	Radio1_ADC_RX_DFS,
847	slv_reg1[4:19],
848	Radio4_LD,
849	Radio3_LD,
850	Radio2_LD,
851	Radio1_LD,
852	slv_reg1[24:31]};
853	17'b00100000000000000 : slv_ip2bus_data <= {Radio4_RSSI_ADC_CLAMP,
854	Radio3_RSSI_ADC_CLAMP,
855	Radio2_RSSI_ADC_CLAMP,
856	Radio1_RSSI_ADC_CLAMP,
857	Radio4_RSSI_ADC_HIZ,
858	Radio3_RSSI_ADC_HIZ,
859	Radio2_RSSI_ADC_HIZ,
860	Radio1_RSSI_ADC_HIZ,
861	Radio4_RSSI_ADC_OTR,
862	Radio3_RSSI_ADC_OTR,
863	Radio2_RSSI_ADC_OTR,
864	Radio1_RSSI_ADC_OTR,
865	slv_reg4[12:23],
866	Radio4_ADC_RX_OTRB,
867	Radio3_ADC_RX_OTRB,
868	Radio2_ADC_RX_OTRB,
869	Radio1_ADC_RX_OTRB,
870	Radio4_ADC_RX_OTRA,
871	Radio3_ADC_RX_OTRA,
872	Radio2_ADC_RX_OTRA,
873	Radio1_ADC_RX_OTRA};
874	17'b00010000000000000 : slv_ip2bus_data <= {Radio2_TX_DAC_PLL_LOCK,
875	slv_reg3[1],
876	Radio2_DIPSW[3],
877	Radio2_DIPSW[2],
878	Radio2_DIPSW[1],
879	Radio2_DIPSW[0],
880	Radio2_RSSI_ADC_D,
881	Radio1_TX_DAC_PLL_LOCK,
882	slv_reg3[17],
883	Radio1_DIPSW[3],
884	Radio1_DIPSW[2],
885	Radio1_DIPSW[1],
886	Radio1_DIPSW[0],
887	Radio1_RSSI_ADC_D};
888	17'b00001000000000000 : slv_ip2bus_data <= {Radio4_TX_DAC_PLL_LOCK,
889	slv_reg4[1],
890	Radio4_DIPSW[3],
891	Radio4_DIPSW[2],
892	Radio4_DIPSW[1],
893	Radio4_DIPSW[0],
894	Radio4_RSSI_ADC_D,
895	Radio3_TX_DAC_PLL_LOCK,
896	slv_reg4[17],
897	Radio3_DIPSW[3],
898	Radio3_DIPSW[2],
899	Radio3_DIPSW[1],
900	Radio3_DIPSW[0],
901	Radio3_RSSI_ADC_D};
902	17'b00000100000000000 : slv_ip2bus_data <= {slv_reg5[0:22], mytip, slv_reg5[24:31]};
903	17'b00000010000000000 : slv_ip2bus_data <= slv_reg6;
904	17'b00000001000000000 : slv_ip2bus_data <= slv_reg7;
905	17'b00000000100000000 : slv_ip2bus_data <= slv_reg8;
906	17'b00000000010000000 : slv_ip2bus_data <= slv_reg9;
907	17'b00000000001000000 : slv_ip2bus_data <= slv_reg10;
908	17'b00000000000100000 : slv_ip2bus_data <= slv_reg11;
909	17'b00000000000010000 : slv_ip2bus_data <= slv_reg12;
910	17'b00000000000001000 : slv_ip2bus_data <= slv_reg13;
911	17'b00000000000000100 : slv_ip2bus_data <= slv_reg14;
912	17'b00000000000000010 : slv_ip2bus_data <= slv_reg15;
913	17'b00000000000000001 : slv_ip2bus_data <= slv_reg16;
914	default : slv_ip2bus_data <= 0;
915	endcase
916
917	end // SLAVE_REG_READ_PROC
918
919	// ------------------------------------------------------------
920	// Example code to drive IP to Bus signals
921	// ------------------------------------------------------------
922
923	assign IP2Bus_Data = slv_ip2bus_data;
924	assign IP2Bus_WrAck = slv_write_ack;
925	assign IP2Bus_RdAck = slv_read_ack;
926	assign IP2Bus_Error = 0;
927
928	endmodule

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source: PlatformSupport/CustomPeripherals/pcores/radio_controller_v1_22_a/hdl/verilog/user_logic.v

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