[889] | 1 | ------------------------------------------------------------------------------ |
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| 2 | -- radio_controller.vhd - entity/architecture pair |
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| 3 | ------------------------------------------------------------------------------ |
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| 4 | -- IMPORTANT: |
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| 5 | -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. |
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| 6 | -- |
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| 7 | -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. |
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| 8 | -- |
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| 9 | -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW |
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| 10 | -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION |
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| 11 | -- OF THE USER_LOGIC ENTITY. |
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| 12 | ------------------------------------------------------------------------------ |
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| 13 | -- |
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| 14 | -- *************************************************************************** |
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| 15 | -- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. ** |
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| 16 | -- ** ** |
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| 17 | -- ** Xilinx, Inc. ** |
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| 18 | -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 19 | -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 20 | -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 21 | -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 22 | -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 23 | -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 24 | -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 25 | -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 26 | -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 27 | -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 28 | -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 29 | -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 30 | -- ** FOR A PARTICULAR PURPOSE. ** |
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| 31 | -- ** ** |
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| 32 | -- *************************************************************************** |
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| 33 | -- |
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| 34 | ------------------------------------------------------------------------------ |
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| 35 | -- Filename: radio_controller.vhd |
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| 36 | -- Version: 1.20.a |
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| 37 | -- Description: Top level design, instantiates library components and user logic. |
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| 38 | -- Date: Wed Feb 06 13:11:09 2008 (by Create and Import Peripheral Wizard) |
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| 39 | -- VHDL Standard: VHDL'93 |
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| 40 | ------------------------------------------------------------------------------ |
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| 41 | -- Naming Conventions: |
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| 42 | -- active low signals: "*_n" |
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| 43 | -- clock signals: "clk", "clk_div#", "clk_#x" |
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| 44 | -- reset signals: "rst", "rst_n" |
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| 45 | -- generics: "C_*" |
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| 46 | -- user defined types: "*_TYPE" |
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| 47 | -- state machine next state: "*_ns" |
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| 48 | -- state machine current state: "*_cs" |
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| 49 | -- combinatorial signals: "*_com" |
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| 50 | -- pipelined or register delay signals: "*_d#" |
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| 51 | -- counter signals: "*cnt*" |
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| 52 | -- clock enable signals: "*_ce" |
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| 53 | -- internal version of output port: "*_i" |
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| 54 | -- device pins: "*_pin" |
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| 55 | -- ports: "- Names begin with Uppercase" |
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| 56 | -- processes: "*_PROCESS" |
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| 57 | -- component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 58 | ------------------------------------------------------------------------------ |
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| 59 | |
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| 60 | library ieee; |
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| 61 | use ieee.std_logic_1164.all; |
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| 62 | use ieee.std_logic_arith.all; |
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| 63 | use ieee.std_logic_unsigned.all; |
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| 64 | |
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| 65 | library proc_common_v2_00_a; |
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| 66 | use proc_common_v2_00_a.proc_common_pkg.all; |
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| 67 | use proc_common_v2_00_a.ipif_pkg.all; |
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| 68 | |
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| 69 | library plbv46_slave_single_v1_00_a; |
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| 70 | use plbv46_slave_single_v1_00_a.plbv46_slave_single; |
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| 71 | |
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| 72 | ------------------------------------------------------------------------------ |
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| 73 | -- Entity section |
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| 74 | ------------------------------------------------------------------------------ |
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| 75 | -- Definition of Generics: |
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| 76 | -- C_BASEADDR -- PLBv46 slave: base address |
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| 77 | -- C_HIGHADDR -- PLBv46 slave: high address |
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| 78 | -- C_SPLB_AWIDTH -- PLBv46 slave: address bus width |
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| 79 | -- C_SPLB_DWIDTH -- PLBv46 slave: data bus width |
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| 80 | -- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters |
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| 81 | -- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width |
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| 82 | -- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width |
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| 83 | -- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme |
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| 84 | -- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts |
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| 85 | -- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master |
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| 86 | -- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds |
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| 87 | -- C_FAMILY -- Xilinx FPGA family |
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| 88 | -- |
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| 89 | -- Definition of Ports: |
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| 90 | -- SPLB_Clk -- PLB main bus clock |
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| 91 | -- SPLB_Rst -- PLB main bus reset |
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| 92 | -- PLB_ABus -- PLB address bus |
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| 93 | -- PLB_UABus -- PLB upper address bus |
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| 94 | -- PLB_PAValid -- PLB primary address valid indicator |
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| 95 | -- PLB_SAValid -- PLB secondary address valid indicator |
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| 96 | -- PLB_rdPrim -- PLB secondary to primary read request indicator |
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| 97 | -- PLB_wrPrim -- PLB secondary to primary write request indicator |
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| 98 | -- PLB_masterID -- PLB current master identifier |
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| 99 | -- PLB_abort -- PLB abort request indicator |
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| 100 | -- PLB_busLock -- PLB bus lock |
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| 101 | -- PLB_RNW -- PLB read/not write |
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| 102 | -- PLB_BE -- PLB byte enables |
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| 103 | -- PLB_MSize -- PLB master data bus size |
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| 104 | -- PLB_size -- PLB transfer size |
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| 105 | -- PLB_type -- PLB transfer type |
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| 106 | -- PLB_lockErr -- PLB lock error indicator |
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| 107 | -- PLB_wrDBus -- PLB write data bus |
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| 108 | -- PLB_wrBurst -- PLB burst write transfer indicator |
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| 109 | -- PLB_rdBurst -- PLB burst read transfer indicator |
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| 110 | -- PLB_wrPendReq -- PLB write pending bus request indicator |
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| 111 | -- PLB_rdPendReq -- PLB read pending bus request indicator |
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| 112 | -- PLB_wrPendPri -- PLB write pending request priority |
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| 113 | -- PLB_rdPendPri -- PLB read pending request priority |
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| 114 | -- PLB_reqPri -- PLB current request priority |
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| 115 | -- PLB_TAttribute -- PLB transfer attribute |
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| 116 | -- Sl_addrAck -- Slave address acknowledge |
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| 117 | -- Sl_SSize -- Slave data bus size |
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| 118 | -- Sl_wait -- Slave wait indicator |
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| 119 | -- Sl_rearbitrate -- Slave re-arbitrate bus indicator |
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| 120 | -- Sl_wrDAck -- Slave write data acknowledge |
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| 121 | -- Sl_wrComp -- Slave write transfer complete indicator |
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| 122 | -- Sl_wrBTerm -- Slave terminate write burst transfer |
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| 123 | -- Sl_rdDBus -- Slave read data bus |
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| 124 | -- Sl_rdWdAddr -- Slave read word address |
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| 125 | -- Sl_rdDAck -- Slave read data acknowledge |
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| 126 | -- Sl_rdComp -- Slave read transfer complete indicator |
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| 127 | -- Sl_rdBTerm -- Slave terminate read burst transfer |
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| 128 | -- Sl_MBusy -- Slave busy indicator |
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| 129 | -- Sl_MWrErr -- Slave write error indicator |
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| 130 | -- Sl_MRdErr -- Slave read error indicator |
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| 131 | -- Sl_MIRQ -- Slave interrupt indicator |
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| 132 | ------------------------------------------------------------------------------ |
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| 133 | |
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| 134 | entity radio_controller is |
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| 135 | generic |
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| 136 | ( |
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| 137 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
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| 138 | --USER generics added here |
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| 139 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
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| 140 | |
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| 141 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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| 142 | -- Bus protocol parameters, do not add to or delete |
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| 143 | C_BASEADDR : std_logic_vector := X"FFFFFFFF"; |
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| 144 | C_HIGHADDR : std_logic_vector := X"00000000"; |
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| 145 | C_SPLB_AWIDTH : integer := 32; |
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| 146 | C_SPLB_DWIDTH : integer := 128; |
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| 147 | C_SPLB_NUM_MASTERS : integer := 8; |
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| 148 | C_SPLB_MID_WIDTH : integer := 3; |
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| 149 | C_SPLB_NATIVE_DWIDTH : integer := 32; |
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| 150 | C_SPLB_P2P : integer := 0; |
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| 151 | C_SPLB_SUPPORT_BURSTS : integer := 0; |
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| 152 | C_SPLB_SMALLEST_MASTER : integer := 32; |
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| 153 | C_SPLB_CLK_PERIOD_PS : integer := 10000; |
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| 154 | C_FAMILY : string := "virtex5" |
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| 155 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 156 | ); |
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| 157 | port |
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| 158 | ( |
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| 159 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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| 160 | |
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[1056] | 161 | |
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| 162 | controller_logic_clk : out std_logic; |
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| 163 | spi_clk : out std_logic; |
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[889] | 164 | data_out : out std_logic; |
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| 165 | radio1_cs : out std_logic; |
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| 166 | radio2_cs : out std_logic; |
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| 167 | radio3_cs : out std_logic; |
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| 168 | radio4_cs : out std_logic; |
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| 169 | dac1_cs : out std_logic; |
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| 170 | dac2_cs : out std_logic; |
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| 171 | dac3_cs : out std_logic; |
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| 172 | dac4_cs : out std_logic; |
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| 173 | radio1_SHDN : out std_logic; |
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| 174 | radio1_TxEn : out std_logic; |
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| 175 | radio1_RxEn : out std_logic; |
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| 176 | radio1_RxHP : out std_logic; |
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| 177 | radio1_LD : in std_logic; |
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| 178 | radio1_24PA : out std_logic; |
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| 179 | radio1_5PA : out std_logic; |
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| 180 | radio1_ANTSW : out std_logic_vector(0 to 1); |
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| 181 | radio1_LED : out std_logic_vector(0 to 2); |
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| 182 | radio1_ADC_RX_DCS : out std_logic; |
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| 183 | radio1_ADC_RX_DFS : out std_logic; |
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| 184 | radio1_ADC_RX_OTRA : in std_logic; |
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| 185 | radio1_ADC_RX_OTRB : in std_logic; |
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| 186 | radio1_ADC_RX_PWDNA : out std_logic; |
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| 187 | radio1_ADC_RX_PWDNB : out std_logic; |
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| 188 | radio1_DIPSW : in std_logic_vector(0 to 3); |
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| 189 | radio1_RSSI_ADC_CLAMP : out std_logic; |
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| 190 | radio1_RSSI_ADC_HIZ : out std_logic; |
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| 191 | radio1_RSSI_ADC_OTR : in std_logic; |
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| 192 | radio1_RSSI_ADC_SLEEP : out std_logic; |
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| 193 | radio1_RSSI_ADC_D : in std_logic_vector(0 to 9); |
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| 194 | radio1_TX_DAC_PLL_LOCK : in std_logic; |
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| 195 | radio1_TX_DAC_RESET : out std_logic; |
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| 196 | radio1_SHDN_external : in std_logic; |
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| 197 | radio1_TxEn_external : in std_logic; |
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| 198 | radio1_RxEn_external : in std_logic; |
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| 199 | radio1_RxHP_external : in std_logic; |
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| 200 | radio1_TxGain : out std_logic_vector(0 to 5); |
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| 201 | radio1_TxStart : out std_logic; |
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| 202 | radio2_SHDN : out std_logic; |
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| 203 | radio2_TxEn : out std_logic; |
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| 204 | radio2_RxEn : out std_logic; |
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| 205 | radio2_RxHP : out std_logic; |
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| 206 | radio2_LD : in std_logic; |
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| 207 | radio2_24PA : out std_logic; |
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| 208 | radio2_5PA : out std_logic; |
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| 209 | radio2_ANTSW : out std_logic_vector(0 to 1); |
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| 210 | radio2_LED : out std_logic_vector(0 to 2); |
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| 211 | radio2_ADC_RX_DCS : out std_logic; |
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| 212 | radio2_ADC_RX_DFS : out std_logic; |
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| 213 | radio2_ADC_RX_OTRA : in std_logic; |
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| 214 | radio2_ADC_RX_OTRB : in std_logic; |
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| 215 | radio2_ADC_RX_PWDNA : out std_logic; |
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| 216 | radio2_ADC_RX_PWDNB : out std_logic; |
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| 217 | radio2_DIPSW : in std_logic_vector(0 to 3); |
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| 218 | radio2_RSSI_ADC_CLAMP : out std_logic; |
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| 219 | radio2_RSSI_ADC_HIZ : out std_logic; |
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| 220 | radio2_RSSI_ADC_OTR : in std_logic; |
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| 221 | radio2_RSSI_ADC_SLEEP : out std_logic; |
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| 222 | radio2_RSSI_ADC_D : in std_logic_vector(0 to 9); |
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| 223 | radio2_TX_DAC_PLL_LOCK : in std_logic; |
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| 224 | radio2_TX_DAC_RESET : out std_logic; |
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| 225 | radio2_SHDN_external : in std_logic; |
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| 226 | radio2_TxEn_external : in std_logic; |
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| 227 | radio2_RxEn_external : in std_logic; |
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| 228 | radio2_RxHP_external : in std_logic; |
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| 229 | radio2_TxGain : out std_logic_vector(0 to 5); |
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| 230 | radio2_TxStart : out std_logic; |
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| 231 | radio3_SHDN : out std_logic; |
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| 232 | radio3_TxEn : out std_logic; |
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| 233 | radio3_RxEn : out std_logic; |
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| 234 | radio3_RxHP : out std_logic; |
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| 235 | radio3_LD : in std_logic; |
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| 236 | radio3_24PA : out std_logic; |
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| 237 | radio3_5PA : out std_logic; |
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| 238 | radio3_ANTSW : out std_logic_vector(0 to 1); |
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| 239 | radio3_LED : out std_logic_vector(0 to 2); |
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| 240 | radio3_ADC_RX_DCS : out std_logic; |
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| 241 | radio3_ADC_RX_DFS : out std_logic; |
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| 242 | radio3_ADC_RX_OTRA : in std_logic; |
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| 243 | radio3_ADC_RX_OTRB : in std_logic; |
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| 244 | radio3_ADC_RX_PWDNA : out std_logic; |
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| 245 | radio3_ADC_RX_PWDNB : out std_logic; |
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| 246 | radio3_DIPSW : in std_logic_vector(0 to 3); |
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| 247 | radio3_RSSI_ADC_CLAMP : out std_logic; |
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| 248 | radio3_RSSI_ADC_HIZ : out std_logic; |
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| 249 | radio3_RSSI_ADC_OTR : in std_logic; |
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| 250 | radio3_RSSI_ADC_SLEEP : out std_logic; |
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| 251 | radio3_RSSI_ADC_D : in std_logic_vector(0 to 9); |
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| 252 | radio3_TX_DAC_PLL_LOCK : in std_logic; |
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| 253 | radio3_TX_DAC_RESET : out std_logic; |
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| 254 | radio3_SHDN_external : in std_logic; |
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| 255 | radio3_TxEn_external : in std_logic; |
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| 256 | radio3_RxEn_external : in std_logic; |
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| 257 | radio3_RxHP_external : in std_logic; |
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| 258 | radio3_TxGain : out std_logic_vector(0 to 5); |
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| 259 | radio3_TxStart : out std_logic; |
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| 260 | radio4_SHDN : out std_logic; |
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| 261 | radio4_TxEn : out std_logic; |
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| 262 | radio4_RxEn : out std_logic; |
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| 263 | radio4_RxHP : out std_logic; |
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| 264 | radio4_LD : in std_logic; |
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| 265 | radio4_24PA : out std_logic; |
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| 266 | radio4_5PA : out std_logic; |
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| 267 | radio4_ANTSW : out std_logic_vector(0 to 1); |
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| 268 | radio4_LED : out std_logic_vector(0 to 2); |
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| 269 | radio4_ADC_RX_DCS : out std_logic; |
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| 270 | radio4_ADC_RX_DFS : out std_logic; |
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| 271 | radio4_ADC_RX_OTRA : in std_logic; |
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| 272 | radio4_ADC_RX_OTRB : in std_logic; |
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| 273 | radio4_ADC_RX_PWDNA : out std_logic; |
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| 274 | radio4_ADC_RX_PWDNB : out std_logic; |
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| 275 | radio4_DIPSW : in std_logic_vector(0 to 3); |
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| 276 | radio4_RSSI_ADC_CLAMP : out std_logic; |
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| 277 | radio4_RSSI_ADC_HIZ : out std_logic; |
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| 278 | radio4_RSSI_ADC_OTR : in std_logic; |
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| 279 | radio4_RSSI_ADC_SLEEP : out std_logic; |
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| 280 | radio4_RSSI_ADC_D : in std_logic_vector(0 to 9); |
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| 281 | radio4_TX_DAC_PLL_LOCK : in std_logic; |
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| 282 | radio4_TX_DAC_RESET : out std_logic; |
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| 283 | radio4_SHDN_external : in std_logic; |
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| 284 | radio4_TxEn_external : in std_logic; |
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| 285 | radio4_RxEn_external : in std_logic; |
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| 286 | radio4_RxHP_external : in std_logic; |
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| 287 | radio4_TxGain : out std_logic_vector(0 to 5); |
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| 288 | radio4_TxStart : out std_logic; |
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| 289 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
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| 290 | |
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| 291 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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| 292 | -- Bus protocol ports, do not add to or delete |
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| 293 | SPLB_Clk : in std_logic; |
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| 294 | SPLB_Rst : in std_logic; |
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| 295 | PLB_ABus : in std_logic_vector(0 to 31); |
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| 296 | PLB_UABus : in std_logic_vector(0 to 31); |
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| 297 | PLB_PAValid : in std_logic; |
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| 298 | PLB_SAValid : in std_logic; |
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| 299 | PLB_rdPrim : in std_logic; |
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| 300 | PLB_wrPrim : in std_logic; |
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| 301 | PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); |
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| 302 | PLB_abort : in std_logic; |
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| 303 | PLB_busLock : in std_logic; |
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| 304 | PLB_RNW : in std_logic; |
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| 305 | PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); |
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| 306 | PLB_MSize : in std_logic_vector(0 to 1); |
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| 307 | PLB_size : in std_logic_vector(0 to 3); |
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| 308 | PLB_type : in std_logic_vector(0 to 2); |
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| 309 | PLB_lockErr : in std_logic; |
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| 310 | PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 311 | PLB_wrBurst : in std_logic; |
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| 312 | PLB_rdBurst : in std_logic; |
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| 313 | PLB_wrPendReq : in std_logic; |
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| 314 | PLB_rdPendReq : in std_logic; |
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| 315 | PLB_wrPendPri : in std_logic_vector(0 to 1); |
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| 316 | PLB_rdPendPri : in std_logic_vector(0 to 1); |
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| 317 | PLB_reqPri : in std_logic_vector(0 to 1); |
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| 318 | PLB_TAttribute : in std_logic_vector(0 to 15); |
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| 319 | Sl_addrAck : out std_logic; |
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| 320 | Sl_SSize : out std_logic_vector(0 to 1); |
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| 321 | Sl_wait : out std_logic; |
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| 322 | Sl_rearbitrate : out std_logic; |
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| 323 | Sl_wrDAck : out std_logic; |
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| 324 | Sl_wrComp : out std_logic; |
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| 325 | Sl_wrBTerm : out std_logic; |
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| 326 | Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 327 | Sl_rdWdAddr : out std_logic_vector(0 to 3); |
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| 328 | Sl_rdDAck : out std_logic; |
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| 329 | Sl_rdComp : out std_logic; |
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| 330 | Sl_rdBTerm : out std_logic; |
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| 331 | Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); |
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| 332 | Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); |
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| 333 | Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); |
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| 334 | Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1) |
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| 335 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 336 | ); |
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| 337 | |
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| 338 | attribute SIGIS : string; |
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| 339 | attribute SIGIS of SPLB_Clk : signal is "CLK"; |
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| 340 | attribute SIGIS of SPLB_Rst : signal is "RST"; |
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| 341 | |
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| 342 | end entity radio_controller; |
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| 343 | |
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| 344 | ------------------------------------------------------------------------------ |
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| 345 | -- Architecture section |
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| 346 | ------------------------------------------------------------------------------ |
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| 347 | |
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| 348 | architecture IMP of radio_controller is |
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| 349 | |
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| 350 | ------------------------------------------ |
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| 351 | -- Array of base/high address pairs for each address range |
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| 352 | ------------------------------------------ |
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| 353 | constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); |
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| 354 | constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; |
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| 355 | constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; |
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| 356 | |
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| 357 | constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := |
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| 358 | ( |
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| 359 | ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address |
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| 360 | ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address |
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| 361 | ); |
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| 362 | |
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| 363 | ------------------------------------------ |
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| 364 | -- Array of desired number of chip enables for each address range |
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| 365 | ------------------------------------------ |
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| 366 | constant USER_SLV_NUM_REG : integer := 17; |
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| 367 | constant USER_NUM_REG : integer := USER_SLV_NUM_REG; |
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| 368 | |
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| 369 | constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := |
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| 370 | ( |
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| 371 | 0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space |
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| 372 | ); |
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| 373 | |
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| 374 | ------------------------------------------ |
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| 375 | -- Ratio of bus clock to core clock (for use in dual clock systems) |
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| 376 | -- 1 = ratio is 1:1 |
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| 377 | -- 2 = ratio is 2:1 |
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| 378 | ------------------------------------------ |
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| 379 | constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; |
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| 380 | |
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| 381 | ------------------------------------------ |
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| 382 | -- Width of the slave data bus (32 only) |
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| 383 | ------------------------------------------ |
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| 384 | constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; |
---|
| 385 | |
---|
| 386 | constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; |
---|
| 387 | |
---|
| 388 | ------------------------------------------ |
---|
| 389 | -- Index for CS/CE |
---|
| 390 | ------------------------------------------ |
---|
| 391 | constant USER_SLV_CS_INDEX : integer := 0; |
---|
| 392 | constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); |
---|
| 393 | |
---|
| 394 | constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; |
---|
| 395 | |
---|
| 396 | ------------------------------------------ |
---|
| 397 | -- IP Interconnect (IPIC) signal declarations |
---|
| 398 | ------------------------------------------ |
---|
| 399 | signal ipif_Bus2IP_Clk : std_logic; |
---|
| 400 | signal ipif_Bus2IP_Reset : std_logic; |
---|
| 401 | signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); |
---|
| 402 | signal ipif_IP2Bus_WrAck : std_logic; |
---|
| 403 | signal ipif_IP2Bus_RdAck : std_logic; |
---|
| 404 | signal ipif_IP2Bus_Error : std_logic; |
---|
| 405 | signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); |
---|
| 406 | signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); |
---|
| 407 | signal ipif_Bus2IP_RNW : std_logic; |
---|
| 408 | signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); |
---|
| 409 | signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); |
---|
| 410 | signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); |
---|
| 411 | signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); |
---|
| 412 | signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); |
---|
| 413 | signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); |
---|
| 414 | signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); |
---|
| 415 | signal user_IP2Bus_RdAck : std_logic; |
---|
| 416 | signal user_IP2Bus_WrAck : std_logic; |
---|
| 417 | signal user_IP2Bus_Error : std_logic; |
---|
| 418 | |
---|
| 419 | ------------------------------------------ |
---|
| 420 | -- Component declaration for verilog user logic |
---|
| 421 | ------------------------------------------ |
---|
| 422 | component user_logic is |
---|
| 423 | generic |
---|
| 424 | ( |
---|
| 425 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
---|
| 426 | --USER generics added here |
---|
| 427 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
---|
| 428 | |
---|
| 429 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
---|
| 430 | -- Bus protocol parameters, do not add to or delete |
---|
| 431 | C_SLV_DWIDTH : integer := 32; |
---|
| 432 | C_NUM_REG : integer := 17 |
---|
| 433 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
---|
| 434 | ); |
---|
| 435 | port |
---|
| 436 | ( |
---|
| 437 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
---|
[1056] | 438 | controller_logic_clk : out std_logic; |
---|
[889] | 439 | spi_clk : out std_logic; |
---|
| 440 | data_out : out std_logic; |
---|
| 441 | Radio1_cs : out std_logic; |
---|
| 442 | Radio2_cs : out std_logic; |
---|
| 443 | Radio3_cs : out std_logic; |
---|
| 444 | Radio4_cs : out std_logic; |
---|
| 445 | Dac1_cs : out std_logic; |
---|
| 446 | Dac2_cs : out std_logic; |
---|
| 447 | Dac3_cs : out std_logic; |
---|
| 448 | Dac4_cs : out std_logic; |
---|
| 449 | Radio1_SHDN : out std_logic; |
---|
| 450 | Radio1_TxEn : out std_logic; |
---|
| 451 | Radio1_RxEn : out std_logic; |
---|
| 452 | Radio1_RxHP : out std_logic; |
---|
| 453 | Radio1_LD : in std_logic; |
---|
| 454 | Radio1_24PA : out std_logic; |
---|
| 455 | Radio1_5PA : out std_logic; |
---|
| 456 | Radio1_ANTSW : out std_logic_vector(0 to 1); |
---|
| 457 | Radio1_LED : out std_logic_vector(0 to 2); |
---|
| 458 | Radio1_ADC_RX_DCS : out std_logic; |
---|
| 459 | Radio1_ADC_RX_DFS : out std_logic; |
---|
| 460 | Radio1_ADC_RX_OTRA : in std_logic; |
---|
| 461 | Radio1_ADC_RX_OTRB : in std_logic; |
---|
| 462 | Radio1_ADC_RX_PWDNA : out std_logic; |
---|
| 463 | Radio1_ADC_RX_PWDNB : out std_logic; |
---|
| 464 | Radio1_DIPSW : in std_logic_vector(0 to 3); |
---|
| 465 | Radio1_RSSI_ADC_CLAMP : out std_logic; |
---|
| 466 | Radio1_RSSI_ADC_HIZ : out std_logic; |
---|
| 467 | Radio1_RSSI_ADC_OTR : in std_logic; |
---|
| 468 | Radio1_RSSI_ADC_SLEEP : out std_logic; |
---|
| 469 | Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
| 470 | Radio1_TX_DAC_PLL_LOCK : in std_logic; |
---|
| 471 | Radio1_TX_DAC_RESET : out std_logic; |
---|
| 472 | Radio1_SHDN_external : in std_logic; |
---|
| 473 | Radio1_TxEn_external : in std_logic; |
---|
| 474 | Radio1_RxEn_external : in std_logic; |
---|
| 475 | Radio1_RxHP_external : in std_logic; |
---|
| 476 | Radio1_TxGain : out std_logic_vector(0 to 5); |
---|
| 477 | Radio1_TxStart : out std_logic; |
---|
| 478 | Radio2_SHDN : out std_logic; |
---|
| 479 | Radio2_TxEn : out std_logic; |
---|
| 480 | Radio2_RxEn : out std_logic; |
---|
| 481 | Radio2_RxHP : out std_logic; |
---|
| 482 | Radio2_LD : in std_logic; |
---|
| 483 | Radio2_24PA : out std_logic; |
---|
| 484 | Radio2_5PA : out std_logic; |
---|
| 485 | Radio2_ANTSW : out std_logic_vector(0 to 1); |
---|
| 486 | Radio2_LED : out std_logic_vector(0 to 2); |
---|
| 487 | Radio2_ADC_RX_DCS : out std_logic; |
---|
| 488 | Radio2_ADC_RX_DFS : out std_logic; |
---|
| 489 | Radio2_ADC_RX_OTRA : in std_logic; |
---|
| 490 | Radio2_ADC_RX_OTRB : in std_logic; |
---|
| 491 | Radio2_ADC_RX_PWDNA : out std_logic; |
---|
| 492 | Radio2_ADC_RX_PWDNB : out std_logic; |
---|
| 493 | Radio2_DIPSW : in std_logic_vector(0 to 3); |
---|
| 494 | Radio2_RSSI_ADC_CLAMP : out std_logic; |
---|
| 495 | Radio2_RSSI_ADC_HIZ : out std_logic; |
---|
| 496 | Radio2_RSSI_ADC_OTR : in std_logic; |
---|
| 497 | Radio2_RSSI_ADC_SLEEP : out std_logic; |
---|
| 498 | Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
| 499 | Radio2_TX_DAC_PLL_LOCK : in std_logic; |
---|
| 500 | Radio2_TX_DAC_RESET : out std_logic; |
---|
| 501 | Radio2_SHDN_external : in std_logic; |
---|
| 502 | Radio2_TxEn_external : in std_logic; |
---|
| 503 | Radio2_RxEn_external : in std_logic; |
---|
| 504 | Radio2_RxHP_external : in std_logic; |
---|
| 505 | Radio2_TxGain : out std_logic_vector(0 to 5); |
---|
| 506 | Radio2_TxStart : out std_logic; |
---|
| 507 | Radio3_SHDN : out std_logic; |
---|
| 508 | Radio3_TxEn : out std_logic; |
---|
| 509 | Radio3_RxEn : out std_logic; |
---|
| 510 | Radio3_RxHP : out std_logic; |
---|
| 511 | Radio3_LD : in std_logic; |
---|
| 512 | Radio3_24PA : out std_logic; |
---|
| 513 | Radio3_5PA : out std_logic; |
---|
| 514 | Radio3_ANTSW : out std_logic_vector(0 to 1); |
---|
| 515 | Radio3_LED : out std_logic_vector(0 to 2); |
---|
| 516 | Radio3_ADC_RX_DCS : out std_logic; |
---|
| 517 | Radio3_ADC_RX_DFS : out std_logic; |
---|
| 518 | Radio3_ADC_RX_OTRA : in std_logic; |
---|
| 519 | Radio3_ADC_RX_OTRB : in std_logic; |
---|
| 520 | Radio3_ADC_RX_PWDNA : out std_logic; |
---|
| 521 | Radio3_ADC_RX_PWDNB : out std_logic; |
---|
| 522 | Radio3_DIPSW : in std_logic_vector(0 to 3); |
---|
| 523 | Radio3_RSSI_ADC_CLAMP : out std_logic; |
---|
| 524 | Radio3_RSSI_ADC_HIZ : out std_logic; |
---|
| 525 | Radio3_RSSI_ADC_OTR : in std_logic; |
---|
| 526 | Radio3_RSSI_ADC_SLEEP : out std_logic; |
---|
| 527 | Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
| 528 | Radio3_TX_DAC_PLL_LOCK : in std_logic; |
---|
| 529 | Radio3_TX_DAC_RESET : out std_logic; |
---|
| 530 | Radio3_SHDN_external : in std_logic; |
---|
| 531 | Radio3_TxEn_external : in std_logic; |
---|
| 532 | Radio3_RxEn_external : in std_logic; |
---|
| 533 | Radio3_RxHP_external : in std_logic; |
---|
| 534 | Radio3_TxGain : out std_logic_vector(0 to 5); |
---|
| 535 | Radio3_TxStart : out std_logic; |
---|
| 536 | Radio4_SHDN : out std_logic; |
---|
| 537 | Radio4_TxEn : out std_logic; |
---|
| 538 | Radio4_RxEn : out std_logic; |
---|
| 539 | Radio4_RxHP : out std_logic; |
---|
| 540 | Radio4_LD : in std_logic; |
---|
| 541 | Radio4_24PA : out std_logic; |
---|
| 542 | Radio4_5PA : out std_logic; |
---|
| 543 | Radio4_ANTSW : out std_logic_vector(0 to 1); |
---|
| 544 | Radio4_LED : out std_logic_vector(0 to 2); |
---|
| 545 | Radio4_ADC_RX_DCS : out std_logic; |
---|
| 546 | Radio4_ADC_RX_DFS : out std_logic; |
---|
| 547 | Radio4_ADC_RX_OTRA : in std_logic; |
---|
| 548 | Radio4_ADC_RX_OTRB : in std_logic; |
---|
| 549 | Radio4_ADC_RX_PWDNA : out std_logic; |
---|
| 550 | Radio4_ADC_RX_PWDNB : out std_logic; |
---|
| 551 | Radio4_DIPSW : in std_logic_vector(0 to 3); |
---|
| 552 | Radio4_RSSI_ADC_CLAMP : out std_logic; |
---|
| 553 | Radio4_RSSI_ADC_HIZ : out std_logic; |
---|
| 554 | Radio4_RSSI_ADC_OTR : in std_logic; |
---|
| 555 | Radio4_RSSI_ADC_SLEEP : out std_logic; |
---|
| 556 | Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
| 557 | Radio4_TX_DAC_PLL_LOCK : in std_logic; |
---|
| 558 | Radio4_TX_DAC_RESET : out std_logic; |
---|
| 559 | Radio4_SHDN_external : in std_logic; |
---|
| 560 | Radio4_TxEn_external : in std_logic; |
---|
| 561 | Radio4_RxEn_external : in std_logic; |
---|
| 562 | Radio4_RxHP_external : in std_logic; |
---|
| 563 | Radio4_TxGain : out std_logic_vector(0 to 5); |
---|
| 564 | Radio4_TxStart : out std_logic; |
---|
| 565 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
---|
| 566 | |
---|
| 567 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
---|
| 568 | -- Bus protocol ports, do not add to or delete |
---|
| 569 | Bus2IP_Clk : in std_logic; |
---|
| 570 | Bus2IP_Reset : in std_logic; |
---|
| 571 | Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); |
---|
| 572 | Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); |
---|
| 573 | Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1); |
---|
| 574 | Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1); |
---|
| 575 | IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); |
---|
| 576 | IP2Bus_RdAck : out std_logic; |
---|
| 577 | IP2Bus_WrAck : out std_logic; |
---|
| 578 | IP2Bus_Error : out std_logic |
---|
| 579 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
---|
| 580 | ); |
---|
| 581 | end component user_logic; |
---|
| 582 | |
---|
| 583 | begin |
---|
| 584 | |
---|
| 585 | ------------------------------------------ |
---|
| 586 | -- instantiate plbv46_slave_single |
---|
| 587 | ------------------------------------------ |
---|
| 588 | PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single |
---|
| 589 | generic map |
---|
| 590 | ( |
---|
| 591 | C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, |
---|
| 592 | C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, |
---|
| 593 | C_SPLB_P2P => C_SPLB_P2P, |
---|
| 594 | C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, |
---|
| 595 | C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, |
---|
| 596 | C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, |
---|
| 597 | C_SPLB_AWIDTH => C_SPLB_AWIDTH, |
---|
| 598 | C_SPLB_DWIDTH => C_SPLB_DWIDTH, |
---|
| 599 | C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, |
---|
| 600 | C_FAMILY => C_FAMILY |
---|
| 601 | ) |
---|
| 602 | port map |
---|
| 603 | ( |
---|
| 604 | SPLB_Clk => SPLB_Clk, |
---|
| 605 | SPLB_Rst => SPLB_Rst, |
---|
| 606 | PLB_ABus => PLB_ABus, |
---|
| 607 | PLB_UABus => PLB_UABus, |
---|
| 608 | PLB_PAValid => PLB_PAValid, |
---|
| 609 | PLB_SAValid => PLB_SAValid, |
---|
| 610 | PLB_rdPrim => PLB_rdPrim, |
---|
| 611 | PLB_wrPrim => PLB_wrPrim, |
---|
| 612 | PLB_masterID => PLB_masterID, |
---|
| 613 | PLB_abort => PLB_abort, |
---|
| 614 | PLB_busLock => PLB_busLock, |
---|
| 615 | PLB_RNW => PLB_RNW, |
---|
| 616 | PLB_BE => PLB_BE, |
---|
| 617 | PLB_MSize => PLB_MSize, |
---|
| 618 | PLB_size => PLB_size, |
---|
| 619 | PLB_type => PLB_type, |
---|
| 620 | PLB_lockErr => PLB_lockErr, |
---|
| 621 | PLB_wrDBus => PLB_wrDBus, |
---|
| 622 | PLB_wrBurst => PLB_wrBurst, |
---|
| 623 | PLB_rdBurst => PLB_rdBurst, |
---|
| 624 | PLB_wrPendReq => PLB_wrPendReq, |
---|
| 625 | PLB_rdPendReq => PLB_rdPendReq, |
---|
| 626 | PLB_wrPendPri => PLB_wrPendPri, |
---|
| 627 | PLB_rdPendPri => PLB_rdPendPri, |
---|
| 628 | PLB_reqPri => PLB_reqPri, |
---|
| 629 | PLB_TAttribute => PLB_TAttribute, |
---|
| 630 | Sl_addrAck => Sl_addrAck, |
---|
| 631 | Sl_SSize => Sl_SSize, |
---|
| 632 | Sl_wait => Sl_wait, |
---|
| 633 | Sl_rearbitrate => Sl_rearbitrate, |
---|
| 634 | Sl_wrDAck => Sl_wrDAck, |
---|
| 635 | Sl_wrComp => Sl_wrComp, |
---|
| 636 | Sl_wrBTerm => Sl_wrBTerm, |
---|
| 637 | Sl_rdDBus => Sl_rdDBus, |
---|
| 638 | Sl_rdWdAddr => Sl_rdWdAddr, |
---|
| 639 | Sl_rdDAck => Sl_rdDAck, |
---|
| 640 | Sl_rdComp => Sl_rdComp, |
---|
| 641 | Sl_rdBTerm => Sl_rdBTerm, |
---|
| 642 | Sl_MBusy => Sl_MBusy, |
---|
| 643 | Sl_MWrErr => Sl_MWrErr, |
---|
| 644 | Sl_MRdErr => Sl_MRdErr, |
---|
| 645 | Sl_MIRQ => Sl_MIRQ, |
---|
| 646 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
---|
| 647 | Bus2IP_Reset => ipif_Bus2IP_Reset, |
---|
| 648 | IP2Bus_Data => ipif_IP2Bus_Data, |
---|
| 649 | IP2Bus_WrAck => ipif_IP2Bus_WrAck, |
---|
| 650 | IP2Bus_RdAck => ipif_IP2Bus_RdAck, |
---|
| 651 | IP2Bus_Error => ipif_IP2Bus_Error, |
---|
| 652 | Bus2IP_Addr => ipif_Bus2IP_Addr, |
---|
| 653 | Bus2IP_Data => ipif_Bus2IP_Data, |
---|
| 654 | Bus2IP_RNW => ipif_Bus2IP_RNW, |
---|
| 655 | Bus2IP_BE => ipif_Bus2IP_BE, |
---|
| 656 | Bus2IP_CS => ipif_Bus2IP_CS, |
---|
| 657 | Bus2IP_RdCE => ipif_Bus2IP_RdCE, |
---|
| 658 | Bus2IP_WrCE => ipif_Bus2IP_WrCE |
---|
| 659 | ); |
---|
| 660 | |
---|
| 661 | ------------------------------------------ |
---|
| 662 | -- instantiate User Logic |
---|
| 663 | ------------------------------------------ |
---|
| 664 | USER_LOGIC_I : component user_logic |
---|
| 665 | generic map |
---|
| 666 | ( |
---|
| 667 | -- MAP USER GENERICS BELOW THIS LINE --------------- |
---|
| 668 | --USER generics mapped here |
---|
| 669 | -- MAP USER GENERICS ABOVE THIS LINE --------------- |
---|
| 670 | |
---|
| 671 | C_SLV_DWIDTH => USER_SLV_DWIDTH, |
---|
| 672 | C_NUM_REG => USER_NUM_REG |
---|
| 673 | ) |
---|
| 674 | port map |
---|
| 675 | ( |
---|
| 676 | -- MAP USER PORTS BELOW THIS LINE ------------------ |
---|
| 677 | |
---|
[1056] | 678 | controller_logic_clk => controller_logic_clk, |
---|
[889] | 679 | spi_clk => spi_clk, |
---|
| 680 | data_out => data_out, |
---|
| 681 | Radio1_cs => radio1_cs, |
---|
| 682 | Radio2_cs => radio2_cs, |
---|
| 683 | Radio3_cs => radio3_cs, |
---|
| 684 | Radio4_cs => radio4_cs, |
---|
| 685 | Dac1_cs => dac1_cs, |
---|
| 686 | Dac2_cs => dac2_cs, |
---|
| 687 | Dac3_cs => dac3_cs, |
---|
| 688 | Dac4_cs => dac4_cs, |
---|
| 689 | Radio1_SHDN => radio1_SHDN, |
---|
| 690 | Radio1_TxEn => radio1_TxEn, |
---|
| 691 | Radio1_RxEn => radio1_RxEn, |
---|
| 692 | Radio1_RxHP => radio1_RxHP, |
---|
| 693 | Radio1_LD => radio1_LD, |
---|
| 694 | Radio1_24PA => radio1_24PA, |
---|
| 695 | Radio1_5PA => radio1_5PA, |
---|
| 696 | Radio1_ANTSW => radio1_ANTSW, |
---|
| 697 | Radio1_LED => radio1_LED, |
---|
| 698 | Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS, |
---|
| 699 | Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS, |
---|
| 700 | Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA, |
---|
| 701 | Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB, |
---|
| 702 | Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA, |
---|
| 703 | Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB, |
---|
| 704 | Radio1_DIPSW => radio1_DIPSW, |
---|
| 705 | Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP, |
---|
| 706 | Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ, |
---|
| 707 | Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR, |
---|
| 708 | Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP, |
---|
| 709 | Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D, |
---|
| 710 | Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK, |
---|
| 711 | Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET, |
---|
| 712 | Radio1_SHDN_external => radio1_SHDN_external, |
---|
| 713 | Radio1_TxEn_external => radio1_TxEn_external, |
---|
| 714 | Radio1_RxEn_external => radio1_RxEn_external, |
---|
| 715 | Radio1_RxHP_external => radio1_RxHP_external, |
---|
| 716 | Radio1_TxGain => radio1_TxGain, |
---|
| 717 | Radio1_TxStart => radio1_TxStart, |
---|
| 718 | Radio2_SHDN => radio2_SHDN, |
---|
| 719 | Radio2_TxEn => radio2_TxEn, |
---|
| 720 | Radio2_RxEn => radio2_RxEn, |
---|
| 721 | Radio2_RxHP => radio2_RxHP, |
---|
| 722 | Radio2_LD => radio2_LD, |
---|
| 723 | Radio2_24PA => radio2_24PA, |
---|
| 724 | Radio2_5PA => radio2_5PA, |
---|
| 725 | Radio2_ANTSW => radio2_ANTSW, |
---|
| 726 | Radio2_LED => radio2_LED, |
---|
| 727 | Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS, |
---|
| 728 | Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS, |
---|
| 729 | Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA, |
---|
| 730 | Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB, |
---|
| 731 | Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA, |
---|
| 732 | Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB, |
---|
| 733 | Radio2_DIPSW => radio2_DIPSW, |
---|
| 734 | Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP, |
---|
| 735 | Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ, |
---|
| 736 | Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR, |
---|
| 737 | Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP, |
---|
| 738 | Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D, |
---|
| 739 | Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK, |
---|
| 740 | Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET, |
---|
| 741 | Radio2_SHDN_external => radio2_SHDN_external, |
---|
| 742 | Radio2_TxEn_external => radio2_TxEn_external, |
---|
| 743 | Radio2_RxEn_external => radio2_RxEn_external, |
---|
| 744 | Radio2_RxHP_external => radio2_RxHP_external, |
---|
| 745 | Radio2_TxGain => radio2_TxGain, |
---|
| 746 | Radio2_TxStart => radio2_TxStart, |
---|
| 747 | Radio3_SHDN => radio3_SHDN, |
---|
| 748 | Radio3_TxEn => radio3_TxEn, |
---|
| 749 | Radio3_RxEn => radio3_RxEn, |
---|
| 750 | Radio3_RxHP => radio3_RxHP, |
---|
| 751 | Radio3_LD => radio3_LD, |
---|
| 752 | Radio3_24PA => radio3_24PA, |
---|
| 753 | Radio3_5PA => radio3_5PA, |
---|
| 754 | Radio3_ANTSW => radio3_ANTSW, |
---|
| 755 | Radio3_LED => radio3_LED, |
---|
| 756 | Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS, |
---|
| 757 | Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS, |
---|
| 758 | Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA, |
---|
| 759 | Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB, |
---|
| 760 | Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA, |
---|
| 761 | Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB, |
---|
| 762 | Radio3_DIPSW => radio3_DIPSW, |
---|
| 763 | Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP, |
---|
| 764 | Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ, |
---|
| 765 | Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR, |
---|
| 766 | Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP, |
---|
| 767 | Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D, |
---|
| 768 | Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK, |
---|
| 769 | Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET, |
---|
| 770 | Radio3_SHDN_external => radio3_SHDN_external, |
---|
| 771 | Radio3_TxEn_external => radio3_TxEn_external, |
---|
| 772 | Radio3_RxEn_external => radio3_RxEn_external, |
---|
| 773 | Radio3_RxHP_external => radio3_RxHP_external, |
---|
| 774 | Radio3_TxGain => radio3_TxGain, |
---|
| 775 | Radio3_TxStart => radio3_TxStart, |
---|
| 776 | Radio4_SHDN => radio4_SHDN, |
---|
| 777 | Radio4_TxEn => radio4_TxEn, |
---|
| 778 | Radio4_RxEn => radio4_RxEn, |
---|
| 779 | Radio4_RxHP => radio4_RxHP, |
---|
| 780 | Radio4_LD => radio4_LD, |
---|
| 781 | Radio4_24PA => radio4_24PA, |
---|
| 782 | Radio4_5PA => radio4_5PA, |
---|
| 783 | Radio4_ANTSW => radio4_ANTSW, |
---|
| 784 | Radio4_LED => radio4_LED, |
---|
| 785 | Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS, |
---|
| 786 | Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS, |
---|
| 787 | Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA, |
---|
| 788 | Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB, |
---|
| 789 | Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA, |
---|
| 790 | Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB, |
---|
| 791 | Radio4_DIPSW => radio4_DIPSW, |
---|
| 792 | Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP, |
---|
| 793 | Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ, |
---|
| 794 | Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR, |
---|
| 795 | Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP, |
---|
| 796 | Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D, |
---|
| 797 | Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK, |
---|
| 798 | Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET, |
---|
| 799 | Radio4_SHDN_external => radio4_SHDN_external, |
---|
| 800 | Radio4_TxEn_external => radio4_TxEn_external, |
---|
| 801 | Radio4_RxEn_external => radio4_RxEn_external, |
---|
| 802 | Radio4_RxHP_external => radio4_RxHP_external, |
---|
| 803 | Radio4_TxGain => radio4_TxGain, |
---|
| 804 | Radio4_TxStart => radio4_TxStart, |
---|
| 805 | -- MAP USER PORTS ABOVE THIS LINE ------------------ |
---|
| 806 | |
---|
| 807 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
---|
| 808 | Bus2IP_Reset => ipif_Bus2IP_Reset, |
---|
| 809 | Bus2IP_Data => ipif_Bus2IP_Data, |
---|
| 810 | Bus2IP_BE => ipif_Bus2IP_BE, |
---|
| 811 | Bus2IP_RdCE => user_Bus2IP_RdCE, |
---|
| 812 | Bus2IP_WrCE => user_Bus2IP_WrCE, |
---|
| 813 | IP2Bus_Data => user_IP2Bus_Data, |
---|
| 814 | IP2Bus_RdAck => user_IP2Bus_RdAck, |
---|
| 815 | IP2Bus_WrAck => user_IP2Bus_WrAck, |
---|
| 816 | IP2Bus_Error => user_IP2Bus_Error |
---|
| 817 | ); |
---|
| 818 | |
---|
| 819 | ------------------------------------------ |
---|
| 820 | -- connect internal signals |
---|
| 821 | ------------------------------------------ |
---|
| 822 | ipif_IP2Bus_Data <= user_IP2Bus_Data; |
---|
| 823 | ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; |
---|
| 824 | ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; |
---|
| 825 | ipif_IP2Bus_Error <= user_IP2Bus_Error; |
---|
| 826 | |
---|
| 827 | user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); |
---|
| 828 | user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); |
---|
| 829 | |
---|
| 830 | end IMP; |
---|