1 | //---------------------------------------------------------------------------- |
---|
2 | // WARP v2 Radio Controller |
---|
3 | // Copyright (c) 2013 Mango Communications |
---|
4 | // Based on the user_logic template generated by XPS 13.4 |
---|
5 | // Original Xilinx copyright statement for user_logic template included below |
---|
6 | //---------------------------------------------------------------------------- |
---|
7 | // |
---|
8 | // *************************************************************************** |
---|
9 | // ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. ** |
---|
10 | // ** ** |
---|
11 | // ** Xilinx, Inc. ** |
---|
12 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
---|
13 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
---|
14 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
---|
15 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
---|
16 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
---|
17 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
---|
18 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
---|
19 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
---|
20 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
---|
21 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
---|
22 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
---|
23 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
---|
24 | // ** FOR A PARTICULAR PURPOSE. ** |
---|
25 | // ** ** |
---|
26 | // *************************************************************************** |
---|
27 | // |
---|
28 | //---------------------------------------------------------------------------- |
---|
29 | // Filename: user_logic.vhd |
---|
30 | // Version: 3.00.a |
---|
31 | // Description: User logic module. |
---|
32 | // Date: Wed Jul 04 20:55:56 2012 (by Create and Import Peripheral Wizard) |
---|
33 | // Verilog Standard: Verilog-2001 |
---|
34 | //---------------------------------------------------------------------------- |
---|
35 | // Naming Conventions: |
---|
36 | // active low signals: "*_n" |
---|
37 | // clock signals: "clk", "clk_div#", "clk_#x" |
---|
38 | // reset signals: "rst", "rst_n" |
---|
39 | // generics: "C_*" |
---|
40 | // user defined types: "*_TYPE" |
---|
41 | // state machine next state: "*_ns" |
---|
42 | // state machine current state: "*_cs" |
---|
43 | // combinatorial signals: "*_com" |
---|
44 | // pipelined or register delay signals: "*_d#" |
---|
45 | // counter signals: "*cnt*" |
---|
46 | // clock enable signals: "*_ce" |
---|
47 | // internal version of output port: "*_i" |
---|
48 | // device pins: "*_pin" |
---|
49 | // ports: "- Names begin with Uppercase" |
---|
50 | // processes: "*_PROCESS" |
---|
51 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
---|
52 | //---------------------------------------------------------------------------- |
---|
53 | |
---|
54 | module user_logic #(parameter C_SLV_DWIDTH = 32, parameter C_NUM_REG = 64) |
---|
55 | ( |
---|
56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
---|
57 | |
---|
58 | //I/O for MAX2829 pins |
---|
59 | output RFA_TxEn, |
---|
60 | output RFB_TxEn, |
---|
61 | output RFC_TxEn, |
---|
62 | output RFD_TxEn, |
---|
63 | |
---|
64 | output RFA_RxEn, |
---|
65 | output RFB_RxEn, |
---|
66 | output RFC_RxEn, |
---|
67 | output RFD_RxEn, |
---|
68 | |
---|
69 | output RFA_RxHP, |
---|
70 | output RFB_RxHP, |
---|
71 | output RFC_RxHP, |
---|
72 | output RFD_RxHP, |
---|
73 | |
---|
74 | output RFA_SHDN, |
---|
75 | output RFB_SHDN, |
---|
76 | output RFC_SHDN, |
---|
77 | output RFD_SHDN, |
---|
78 | |
---|
79 | output RFA_SPI_SCLK, |
---|
80 | output RFB_SPI_SCLK, |
---|
81 | output RFC_SPI_SCLK, |
---|
82 | output RFD_SPI_SCLK, |
---|
83 | |
---|
84 | output RFA_SPI_MOSI, |
---|
85 | output RFB_SPI_MOSI, |
---|
86 | output RFC_SPI_MOSI, |
---|
87 | output RFD_SPI_MOSI, |
---|
88 | |
---|
89 | output RFA_SPI_CSn, |
---|
90 | output RFB_SPI_CSn, |
---|
91 | output RFC_SPI_CSn, |
---|
92 | output RFD_SPI_CSn, |
---|
93 | |
---|
94 | output [0:6] RFA_B, |
---|
95 | output [0:6] RFB_B, |
---|
96 | output [0:6] RFC_B, |
---|
97 | output [0:6] RFD_B, |
---|
98 | |
---|
99 | input RFA_LD, |
---|
100 | input RFB_LD, |
---|
101 | input RFC_LD, |
---|
102 | input RFD_LD, |
---|
103 | |
---|
104 | //Outputs to PA and ant switch pins |
---|
105 | output RFA_PAEn_24, |
---|
106 | output RFB_PAEn_24, |
---|
107 | output RFC_PAEn_24, |
---|
108 | output RFD_PAEn_24, |
---|
109 | |
---|
110 | output RFA_PAEn_5, |
---|
111 | output RFB_PAEn_5, |
---|
112 | output RFC_PAEn_5, |
---|
113 | output RFD_PAEn_5, |
---|
114 | |
---|
115 | output [0:1] RFA_AntSw, |
---|
116 | output [0:1] RFB_AntSw, |
---|
117 | output [0:1] RFC_AntSw, |
---|
118 | output [0:1] RFD_AntSw, |
---|
119 | |
---|
120 | input [0:3] RFA_DIPSW, |
---|
121 | input [0:3] RFB_DIPSW, |
---|
122 | input [0:3] RFC_DIPSW, |
---|
123 | input [0:3] RFD_DIPSW, |
---|
124 | |
---|
125 | output RFA_RX_ADC_DCS, |
---|
126 | output RFB_RX_ADC_DCS, |
---|
127 | output RFC_RX_ADC_DCS, |
---|
128 | output RFD_RX_ADC_DCS, |
---|
129 | |
---|
130 | output RFA_RX_ADC_DFS, |
---|
131 | output RFB_RX_ADC_DFS, |
---|
132 | output RFC_RX_ADC_DFS, |
---|
133 | output RFD_RX_ADC_DFS, |
---|
134 | |
---|
135 | output RFA_RX_ADC_PWDN, |
---|
136 | output RFB_RX_ADC_PWDN, |
---|
137 | output RFC_RX_ADC_PWDN, |
---|
138 | output RFD_RX_ADC_PWDN, |
---|
139 | |
---|
140 | output RFA_RSSI_ADC_CLAMP, |
---|
141 | output RFB_RSSI_ADC_CLAMP, |
---|
142 | output RFC_RSSI_ADC_CLAMP, |
---|
143 | output RFD_RSSI_ADC_CLAMP, |
---|
144 | |
---|
145 | output RFA_RSSI_ADC_HIZ, |
---|
146 | output RFB_RSSI_ADC_HIZ, |
---|
147 | output RFC_RSSI_ADC_HIZ, |
---|
148 | output RFD_RSSI_ADC_HIZ, |
---|
149 | |
---|
150 | output RFA_RSSI_ADC_SLEEP, |
---|
151 | output RFB_RSSI_ADC_SLEEP, |
---|
152 | output RFC_RSSI_ADC_SLEEP, |
---|
153 | output RFD_RSSI_ADC_SLEEP, |
---|
154 | |
---|
155 | output RFA_DAC_SPI_CSn, |
---|
156 | output RFB_DAC_SPI_CSn, |
---|
157 | output RFC_DAC_SPI_CSn, |
---|
158 | output RFD_DAC_SPI_CSn, |
---|
159 | |
---|
160 | output RFA_DAC_SPI_SCLK, |
---|
161 | output RFB_DAC_SPI_SCLK, |
---|
162 | output RFC_DAC_SPI_SCLK, |
---|
163 | output RFD_DAC_SPI_SCLK, |
---|
164 | |
---|
165 | output RFA_DAC_SPI_MOSI, |
---|
166 | output RFB_DAC_SPI_MOSI, |
---|
167 | output RFC_DAC_SPI_MOSI, |
---|
168 | output RFD_DAC_SPI_MOSI, |
---|
169 | |
---|
170 | input RFA_DAC_SPI_MISO, |
---|
171 | input RFB_DAC_SPI_MISO, |
---|
172 | input RFC_DAC_SPI_MISO, |
---|
173 | input RFD_DAC_SPI_MISO, |
---|
174 | |
---|
175 | output RFA_DAC_RESET, |
---|
176 | output RFB_DAC_RESET, |
---|
177 | output RFC_DAC_RESET, |
---|
178 | output RFD_DAC_RESET, |
---|
179 | |
---|
180 | input RFA_DAC_PLLLOCK, |
---|
181 | input RFB_DAC_PLLLOCK, |
---|
182 | input RFC_DAC_PLLLOCK, |
---|
183 | input RFD_DAC_PLLLOCK, |
---|
184 | |
---|
185 | //I/O for user logic to control state from hardware |
---|
186 | input usr_RFA_TxEn, |
---|
187 | input usr_RFB_TxEn, |
---|
188 | input usr_RFC_TxEn, |
---|
189 | input usr_RFD_TxEn, |
---|
190 | |
---|
191 | input usr_RFA_RxEn, |
---|
192 | input usr_RFB_RxEn, |
---|
193 | input usr_RFC_RxEn, |
---|
194 | input usr_RFD_RxEn, |
---|
195 | |
---|
196 | input usr_RFA_RxHP, |
---|
197 | input usr_RFB_RxHP, |
---|
198 | input usr_RFC_RxHP, |
---|
199 | input usr_RFD_RxHP, |
---|
200 | |
---|
201 | input usr_RFA_SHDN, |
---|
202 | input usr_RFB_SHDN, |
---|
203 | input usr_RFC_SHDN, |
---|
204 | input usr_RFD_SHDN, |
---|
205 | |
---|
206 | input [0:1] usr_RFA_RxGainRF, |
---|
207 | input [0:1] usr_RFB_RxGainRF, |
---|
208 | input [0:1] usr_RFC_RxGainRF, |
---|
209 | input [0:1] usr_RFD_RxGainRF, |
---|
210 | |
---|
211 | input [0:4] usr_RFA_RxGainBB, |
---|
212 | input [0:4] usr_RFB_RxGainBB, |
---|
213 | input [0:4] usr_RFC_RxGainBB, |
---|
214 | input [0:4] usr_RFD_RxGainBB, |
---|
215 | |
---|
216 | input [0:5] usr_RFA_TxGain, |
---|
217 | input [0:5] usr_RFB_TxGain, |
---|
218 | input [0:5] usr_RFC_TxGain, |
---|
219 | input [0:5] usr_RFD_TxGain, |
---|
220 | |
---|
221 | input usr_SPI_ctrlSrc, |
---|
222 | input usr_SPI_go, |
---|
223 | output usr_SPI_active, |
---|
224 | input [0: 3] usr_SPI_rfsel, |
---|
225 | input [0: 3] usr_SPI_regaddr, |
---|
226 | input [0:13] usr_SPI_regdata, |
---|
227 | |
---|
228 | output usr_RFA_PHYStart, |
---|
229 | output usr_RFB_PHYStart, |
---|
230 | output usr_RFC_PHYStart, |
---|
231 | output usr_RFD_PHYStart, |
---|
232 | |
---|
233 | output usr_any_PHYStart, |
---|
234 | |
---|
235 | output usr_RFA_statLED_Tx, |
---|
236 | output usr_RFA_statLED_Rx, |
---|
237 | output usr_RFA_statLED_NoLock, |
---|
238 | |
---|
239 | output usr_RFB_statLED_Tx, |
---|
240 | output usr_RFB_statLED_Rx, |
---|
241 | output usr_RFB_statLED_NoLock, |
---|
242 | |
---|
243 | output usr_RFC_statLED_Tx, |
---|
244 | output usr_RFC_statLED_Rx, |
---|
245 | output usr_RFC_statLED_NoLock, |
---|
246 | |
---|
247 | output usr_RFD_statLED_Tx, |
---|
248 | output usr_RFD_statLED_Rx, |
---|
249 | output usr_RFD_statLED_NoLock, |
---|
250 | |
---|
251 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
---|
252 | |
---|
253 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
---|
254 | // -- Bus protocol ports, do not add to or delete |
---|
255 | input Bus2IP_Clk, |
---|
256 | input Bus2IP_Reset, |
---|
257 | input [0 : C_SLV_DWIDTH-1] Bus2IP_Data, |
---|
258 | input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE, |
---|
259 | input [0 : C_NUM_REG-1] Bus2IP_RdCE, |
---|
260 | input [0 : C_NUM_REG-1] Bus2IP_WrCE, |
---|
261 | output [0 : C_SLV_DWIDTH-1] IP2Bus_Data, |
---|
262 | output IP2Bus_RdAck, |
---|
263 | output IP2Bus_WrAck, |
---|
264 | output IP2Bus_Error |
---|
265 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
---|
266 | ); // user_logic |
---|
267 | |
---|
268 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
---|
269 | // --USER parameters added here |
---|
270 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
---|
271 | |
---|
272 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
---|
273 | // -- Bus protocol parameters, do not add to or delete |
---|
274 | //parameter C_SLV_DWIDTH = 32; |
---|
275 | //parameter C_NUM_REG = 64; |
---|
276 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
---|
277 | |
---|
278 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
---|
279 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
---|
280 | |
---|
281 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
---|
282 | // -- Bus protocol ports, do not add to or delete |
---|
283 | /* |
---|
284 | input Bus2IP_Clk; |
---|
285 | input Bus2IP_Reset; |
---|
286 | input [0 : C_SLV_DWIDTH-1] Bus2IP_Data; |
---|
287 | input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE; |
---|
288 | input [0 : C_NUM_REG-1] Bus2IP_RdCE; |
---|
289 | input [0 : C_NUM_REG-1] Bus2IP_WrCE; |
---|
290 | output [0 : C_SLV_DWIDTH-1] IP2Bus_Data; |
---|
291 | output IP2Bus_RdAck; |
---|
292 | output IP2Bus_WrAck; |
---|
293 | output IP2Bus_Error; |
---|
294 | */ |
---|
295 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
---|
296 | |
---|
297 | //---------------------------------------------------------------------------- |
---|
298 | // Implementation |
---|
299 | //---------------------------------------------------------------------------- |
---|
300 | |
---|
301 | // --USER nets declarations added here, as needed for user logic |
---|
302 | `define MAX2829_REG0_ON_RESET 14'b01000101000000 |
---|
303 | `define MAX2829_REG1_ON_RESET 14'b00000011001010 |
---|
304 | `define MAX2829_REG2_ON_RESET 14'b01000000000111 |
---|
305 | `define MAX2829_REG3_ON_RESET 14'b11000010100010 |
---|
306 | `define MAX2829_REG4_ON_RESET 14'b01110111011101 |
---|
307 | `define MAX2829_REG5_ON_RESET 14'b01100000100100 |
---|
308 | `define MAX2829_REG6_ON_RESET 14'b01110000000000 |
---|
309 | `define MAX2829_REG7_ON_RESET 14'b00000000101010 |
---|
310 | `define MAX2829_REG8_ON_RESET 14'b00000000100101 |
---|
311 | `define MAX2829_REG9_ON_RESET 14'b00001000000000 |
---|
312 | `define MAX2829_REGA_ON_RESET 14'b00001111000000 |
---|
313 | `define MAX2829_REGB_ON_RESET 14'b00000001111111 |
---|
314 | `define MAX2829_REGC_ON_RESET 14'b00000000000000 |
---|
315 | |
---|
316 | `define TXTIMING_REG_ON_RESET 32'h401000F0 //Sane default Tx Timing values |
---|
317 | `define TXGAINS_REG_ON_RESET 32'h32323232 //Tx Gain targets = 50 |
---|
318 | `define CLKDIV_GAINTIMING_REG_ON_RESET 32'h00004F22 //Gain step=0xF, time step=4, clk divs = 2 |
---|
319 | |
---|
320 | // Nets for user logic slave model s/w accessible register example |
---|
321 | reg [0 : C_SLV_DWIDTH-1] slv_reg0; |
---|
322 | reg [0 : C_SLV_DWIDTH-1] slv_reg1; |
---|
323 | reg [0 : C_SLV_DWIDTH-1] slv_reg2; |
---|
324 | reg [0 : C_SLV_DWIDTH-1] slv_reg3; |
---|
325 | reg [0 : C_SLV_DWIDTH-1] slv_reg4; |
---|
326 | reg [0 : C_SLV_DWIDTH-1] slv_reg5; |
---|
327 | reg [0 : C_SLV_DWIDTH-1] slv_reg6; |
---|
328 | reg [0 : C_SLV_DWIDTH-1] slv_reg7; |
---|
329 | reg [0 : C_SLV_DWIDTH-1] slv_reg8; |
---|
330 | reg [0 : C_SLV_DWIDTH-1] slv_reg9; |
---|
331 | reg [0 : C_SLV_DWIDTH-1] slv_reg10; |
---|
332 | |
---|
333 | wire [0 : 10] slv_reg_write_sel; |
---|
334 | wire [0 : 63] slv_reg_read_sel; |
---|
335 | reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data; |
---|
336 | wire slv_read_ack; |
---|
337 | wire slv_write_ack; |
---|
338 | integer byte_index, bit_index; |
---|
339 | |
---|
340 | |
---|
341 | wire slv_write_ack_normalRegisters; |
---|
342 | |
---|
343 | wire [0:31] status_reg; |
---|
344 | |
---|
345 | //Use Verilog array-of-arrays syntax for the register banks to mirror MAX2829 internal registers |
---|
346 | // RFx_MAX2829_mirrorRegs[N] maps to MAX2829 reg N, for N=[0x0, 0xC] |
---|
347 | // All registers are 14 bits in the MAX2829 |
---|
348 | reg [0:13] RFA_MAX2829_mirrorRegs [0:12]; |
---|
349 | reg [0:13] RFB_MAX2829_mirrorRegs [0:12]; |
---|
350 | reg [0:13] RFC_MAX2829_mirrorRegs [0:12]; |
---|
351 | reg [0:13] RFD_MAX2829_mirrorRegs [0:12]; |
---|
352 | |
---|
353 | wire RFA_TxEn_ctrlSrc, RFB_TxEn_ctrlSrc, RFC_TxEn_ctrlSrc, RFD_TxEn_ctrlSrc; |
---|
354 | wire RFA_RxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFD_RxEn_ctrlSrc; |
---|
355 | wire RFA_RxHP_ctrlSrc, RFB_RxHP_ctrlSrc, RFC_RxHP_ctrlSrc, RFD_RxHP_ctrlSrc; |
---|
356 | wire RFA_SHDN_ctrlSrc, RFB_SHDN_ctrlSrc, RFC_SHDN_ctrlSrc, RFD_SHDN_ctrlSrc; |
---|
357 | wire RFA_TxGain_ctrlSrc, RFB_TxGain_ctrlSrc, RFC_TxGain_ctrlSrc, RFD_TxGain_ctrlSrc; |
---|
358 | wire RFA_RxGain_ctrlSrc, RFB_RxGain_ctrlSrc, RFC_RxGain_ctrlSrc, RFD_RxGain_ctrlSrc; |
---|
359 | |
---|
360 | wire RFA_TxEn_sw, RFB_TxEn_sw, RFC_TxEn_sw, RFD_TxEn_sw; |
---|
361 | wire RFA_RxEn_sw, RFB_RxEn_sw, RFC_RxEn_sw, RFD_RxEn_sw; |
---|
362 | wire RFA_RxHP_sw, RFB_RxHP_sw, RFC_RxHP_sw, RFD_RxHP_sw; |
---|
363 | wire RFA_SHDN_sw, RFB_SHDN_sw, RFC_SHDN_sw, RFD_SHDN_sw; |
---|
364 | |
---|
365 | wire RFA_PAEn, RFB_PAEn, RFC_PAEn, RFD_PAEn; |
---|
366 | |
---|
367 | wire RFA_AntSw_mode, RFB_AntSw_mode, RFC_AntSw_mode, RFD_AntSw_mode; |
---|
368 | |
---|
369 | wire [0:7] TxTiming_dly_TxGainRamp, TxTiming_dly_PowerAmpEn, TxTiming_dly_TxEn, TxTiming_dly_startPHY; |
---|
370 | |
---|
371 | wire [0:3] TxGainRamp_gainStep, TxGainRamp_timeStep; |
---|
372 | |
---|
373 | wire [0:5] RFA_TxGain_sw, RFB_TxGain_sw, RFC_TxGain_sw, RFD_TxGain_sw; |
---|
374 | wire [0:4] RFA_RxGainBB_sw, RFB_RxGainBB_sw, RFC_RxGainBB_sw, RFD_RxGainBB_sw; |
---|
375 | wire [0:1] RFA_RxGainRF_sw, RFB_RxGainRF_sw, RFC_RxGainRF_sw, RFD_RxGainRF_sw; |
---|
376 | |
---|
377 | wire [0:5] RFA_TxGain_target, RFB_TxGain_target, RFC_TxGain_target, RFD_TxGain_target; |
---|
378 | wire [0:5] RFA_TxGain_ramped, RFB_TxGain_ramped, RFC_TxGain_ramped, RFD_TxGain_ramped; |
---|
379 | |
---|
380 | wire [0:4] RFA_RxGainBB, RFB_RxGainBB, RFC_RxGainBB, RFD_RxGainBB; |
---|
381 | wire [0:1] RFA_RxGainRF, RFB_RxGainRF, RFC_RxGainRF, RFD_RxGainRF; |
---|
382 | |
---|
383 | wire [0:1] txTiming_clk_div_sel; |
---|
384 | |
---|
385 | wire [0:2] spi_rf_clk_div_sel; |
---|
386 | wire [0: 3] spi_rf_cs_mask_sw; |
---|
387 | wire [0: 3] spi_rf_cs_mask; |
---|
388 | wire [0:13] spi_rf_tx_regdata; |
---|
389 | wire [0: 3] spi_rf_tx_regaddr; |
---|
390 | |
---|
391 | wire [0:2] spi_dac_clk_div_sel; |
---|
392 | wire [0:3] spi_dac_cs_mask; |
---|
393 | wire spi_dac_tx_rnw; |
---|
394 | wire [0:7] spi_dac_tx_regdata; |
---|
395 | wire [0:3] spi_dac_tx_regaddr; |
---|
396 | |
---|
397 | wire [0:31] spi_dacA_rx_data; |
---|
398 | wire [0:31] spi_dacB_rx_data; |
---|
399 | wire [0:31] spi_dacC_rx_data; |
---|
400 | wire [0:31] spi_dacD_rx_data; |
---|
401 | |
---|
402 | wire spi_rf_go; |
---|
403 | wire spi_dac_go; |
---|
404 | |
---|
405 | wire spi_rf_tx_reg_write; |
---|
406 | wire spi_rf_xfer_done; |
---|
407 | |
---|
408 | wire spi_dac_tx_reg_write; |
---|
409 | wire spi_dac_xfer_done; |
---|
410 | |
---|
411 | wire RFA_txStart, RFB_txStart, RFC_txStart, RFD_txStart; |
---|
412 | |
---|
413 | wire RFA_MAX2829_Reset, RFB_MAX2829_Reset, RFC_MAX2829_Reset, RFD_MAX2829_Reset; |
---|
414 | |
---|
415 | wire [0:31] radio_aux_status_bits_reg; |
---|
416 | |
---|
417 | // Slave register write process; only implemented for RW and WO registers |
---|
418 | always @( posedge Bus2IP_Clk ) |
---|
419 | begin: SLAVE_REG_WRITE_PROC |
---|
420 | if ( Bus2IP_Reset == 1 ) |
---|
421 | begin |
---|
422 | slv_reg0 <= 0; //All zeros on reset- Tx/Rx disabled, SHDN (active low) enabled |
---|
423 | slv_reg1 <= `TXTIMING_REG_ON_RESET; |
---|
424 | slv_reg2 <= `TXGAINS_REG_ON_RESET; |
---|
425 | slv_reg3 <= 0; |
---|
426 | slv_reg4 <= `CLKDIV_GAINTIMING_REG_ON_RESET; |
---|
427 | slv_reg5 <= 0; |
---|
428 | slv_reg6 <= 0; |
---|
429 | slv_reg7 <= 0; |
---|
430 | slv_reg8 <= 0; |
---|
431 | slv_reg9 <= 0; |
---|
432 | slv_reg10 <= 0; |
---|
433 | end |
---|
434 | else |
---|
435 | case ( slv_reg_write_sel ) |
---|
436 | 11'b10000000000 : |
---|
437 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
438 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
439 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
440 | slv_reg0[bit_index] <= Bus2IP_Data[bit_index]; |
---|
441 | 11'b01000000000 : |
---|
442 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
443 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
444 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
445 | slv_reg1[bit_index] <= Bus2IP_Data[bit_index]; |
---|
446 | 11'b00100000000 : |
---|
447 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
448 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
449 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
450 | slv_reg2[bit_index] <= Bus2IP_Data[bit_index]; |
---|
451 | 11'b00010000000 : |
---|
452 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
453 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
454 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
455 | slv_reg3[bit_index] <= Bus2IP_Data[bit_index]; |
---|
456 | 11'b00001000000 : |
---|
457 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
458 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
459 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
460 | slv_reg4[bit_index] <= Bus2IP_Data[bit_index]; |
---|
461 | 11'b00000100000 : |
---|
462 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
463 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
464 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
465 | slv_reg5[bit_index] <= Bus2IP_Data[bit_index]; |
---|
466 | 11'b00000010000 : |
---|
467 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
468 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
469 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
470 | slv_reg6[bit_index] <= Bus2IP_Data[bit_index]; |
---|
471 | 11'b00000001000 : |
---|
472 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
473 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
474 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
475 | slv_reg7[bit_index] <= Bus2IP_Data[bit_index]; |
---|
476 | 11'b00000000100 : |
---|
477 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
478 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
479 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
480 | slv_reg8[bit_index] <= Bus2IP_Data[bit_index]; |
---|
481 | 11'b00000000010 : |
---|
482 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
483 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
484 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
485 | slv_reg9[bit_index] <= Bus2IP_Data[bit_index]; |
---|
486 | 11'b00000000001 : |
---|
487 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
488 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
489 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
490 | slv_reg10[bit_index] <= Bus2IP_Data[bit_index]; |
---|
491 | default : ; |
---|
492 | endcase |
---|
493 | |
---|
494 | end // SLAVE_REG_WRITE_PROC |
---|
495 | |
---|
496 | // Slave model register read mux |
---|
497 | // All registers can be read |
---|
498 | // Really annoying XST bug for V4 devices prevents use of wildcard in sensitivity list when 2D arrays are used, hence the crazy long |
---|
499 | // list below (http://www.xilinx.com/support/answers/20391.htm) |
---|
500 | always @(slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, spi_dacD_rx_data[24:31], spi_dacC_rx_data[24:31], spi_dacB_rx_data[24:31], spi_dacA_rx_data[24:31], slv_reg8, radio_aux_status_bits_reg, slv_reg10, status_reg, RFA_MAX2829_mirrorRegs[0], RFA_MAX2829_mirrorRegs[1], RFA_MAX2829_mirrorRegs[2], RFA_MAX2829_mirrorRegs[3], RFA_MAX2829_mirrorRegs[4], RFA_MAX2829_mirrorRegs[5], RFA_MAX2829_mirrorRegs[6], RFA_MAX2829_mirrorRegs[7], RFA_MAX2829_mirrorRegs[8], RFA_MAX2829_mirrorRegs[9], RFA_MAX2829_mirrorRegs[10], RFA_MAX2829_mirrorRegs[11], RFA_MAX2829_mirrorRegs[12], RFB_MAX2829_mirrorRegs[0], RFB_MAX2829_mirrorRegs[1], RFB_MAX2829_mirrorRegs[2], RFB_MAX2829_mirrorRegs[3], RFB_MAX2829_mirrorRegs[4], RFB_MAX2829_mirrorRegs[5], RFB_MAX2829_mirrorRegs[6], RFB_MAX2829_mirrorRegs[7], RFB_MAX2829_mirrorRegs[8], RFB_MAX2829_mirrorRegs[9], RFB_MAX2829_mirrorRegs[10], RFB_MAX2829_mirrorRegs[11], RFB_MAX2829_mirrorRegs[12], RFC_MAX2829_mirrorRegs[0], RFC_MAX2829_mirrorRegs[1], RFC_MAX2829_mirrorRegs[2], RFC_MAX2829_mirrorRegs[3], RFC_MAX2829_mirrorRegs[4], RFC_MAX2829_mirrorRegs[5], RFC_MAX2829_mirrorRegs[6], RFC_MAX2829_mirrorRegs[7], RFC_MAX2829_mirrorRegs[8], RFC_MAX2829_mirrorRegs[9], RFC_MAX2829_mirrorRegs[10], RFC_MAX2829_mirrorRegs[11], RFC_MAX2829_mirrorRegs[12], RFD_MAX2829_mirrorRegs[0], RFD_MAX2829_mirrorRegs[1], RFD_MAX2829_mirrorRegs[2], RFD_MAX2829_mirrorRegs[3], RFD_MAX2829_mirrorRegs[4], RFD_MAX2829_mirrorRegs[5], RFD_MAX2829_mirrorRegs[6], RFD_MAX2829_mirrorRegs[7], RFD_MAX2829_mirrorRegs[8], RFD_MAX2829_mirrorRegs[9], RFD_MAX2829_mirrorRegs[10], RFD_MAX2829_mirrorRegs[11], RFD_MAX2829_mirrorRegs[12]) |
---|
501 | begin: SLAVE_REG_READ_PROC |
---|
502 | case ( slv_reg_read_sel ) |
---|
503 | 64'b1000000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg0; |
---|
504 | 64'b0100000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg1; |
---|
505 | 64'b0010000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg2; |
---|
506 | 64'b0001000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg3; |
---|
507 | 64'b0000100000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg4; |
---|
508 | 64'b0000010000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg5; |
---|
509 | 64'b0000001000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg6; |
---|
510 | 64'b0000000100000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {spi_dacD_rx_data[24:31], spi_dacC_rx_data[24:31], spi_dacB_rx_data[24:31], spi_dacA_rx_data[24:31]}; |
---|
511 | 64'b0000000010000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg8; |
---|
512 | 64'b0000000001000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= radio_aux_status_bits_reg; |
---|
513 | 64'b0000000000100000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg10; |
---|
514 | 64'b0000000000010000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= status_reg; |
---|
515 | 64'b0000000000001000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[0]}; |
---|
516 | 64'b0000000000000100000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[1]}; |
---|
517 | 64'b0000000000000010000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[2]}; |
---|
518 | 64'b0000000000000001000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[3]}; |
---|
519 | 64'b0000000000000000100000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[4]}; |
---|
520 | 64'b0000000000000000010000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[5]}; |
---|
521 | 64'b0000000000000000001000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[6]}; |
---|
522 | 64'b0000000000000000000100000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[7]}; |
---|
523 | 64'b0000000000000000000010000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[8]}; |
---|
524 | 64'b0000000000000000000001000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[9]}; |
---|
525 | 64'b0000000000000000000000100000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[10]}; |
---|
526 | 64'b0000000000000000000000010000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[11]}; |
---|
527 | 64'b0000000000000000000000001000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[12]}; |
---|
528 | 64'b0000000000000000000000000100000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[0]}; |
---|
529 | 64'b0000000000000000000000000010000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[1]}; |
---|
530 | 64'b0000000000000000000000000001000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[2]}; |
---|
531 | 64'b0000000000000000000000000000100000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[3]}; |
---|
532 | 64'b0000000000000000000000000000010000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[4]}; |
---|
533 | 64'b0000000000000000000000000000001000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[5]}; |
---|
534 | 64'b0000000000000000000000000000000100000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[6]}; |
---|
535 | 64'b0000000000000000000000000000000010000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[7]}; |
---|
536 | 64'b0000000000000000000000000000000001000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[8]}; |
---|
537 | 64'b0000000000000000000000000000000000100000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[9]}; |
---|
538 | 64'b0000000000000000000000000000000000010000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[10]}; |
---|
539 | 64'b0000000000000000000000000000000000001000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[11]}; |
---|
540 | 64'b0000000000000000000000000000000000000100000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[12]}; |
---|
541 | 64'b0000000000000000000000000000000000000010000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[0]}; |
---|
542 | 64'b0000000000000000000000000000000000000001000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[1]}; |
---|
543 | 64'b0000000000000000000000000000000000000000100000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[2]}; |
---|
544 | 64'b0000000000000000000000000000000000000000010000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[3]}; |
---|
545 | 64'b0000000000000000000000000000000000000000001000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[4]}; |
---|
546 | 64'b0000000000000000000000000000000000000000000100000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[5]}; |
---|
547 | 64'b0000000000000000000000000000000000000000000010000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[6]}; |
---|
548 | 64'b0000000000000000000000000000000000000000000001000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[7]}; |
---|
549 | 64'b0000000000000000000000000000000000000000000000100000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[8]}; |
---|
550 | 64'b0000000000000000000000000000000000000000000000010000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[9]}; |
---|
551 | 64'b0000000000000000000000000000000000000000000000001000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[10]}; |
---|
552 | 64'b0000000000000000000000000000000000000000000000000100000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[11]}; |
---|
553 | 64'b0000000000000000000000000000000000000000000000000010000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[12]}; |
---|
554 | 64'b0000000000000000000000000000000000000000000000000001000000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[0]}; |
---|
555 | 64'b0000000000000000000000000000000000000000000000000000100000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[1]}; |
---|
556 | 64'b0000000000000000000000000000000000000000000000000000010000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[2]}; |
---|
557 | 64'b0000000000000000000000000000000000000000000000000000001000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[3]}; |
---|
558 | 64'b0000000000000000000000000000000000000000000000000000000100000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[4]}; |
---|
559 | 64'b0000000000000000000000000000000000000000000000000000000010000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[5]}; |
---|
560 | 64'b0000000000000000000000000000000000000000000000000000000001000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[6]}; |
---|
561 | 64'b0000000000000000000000000000000000000000000000000000000000100000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[7]}; |
---|
562 | 64'b0000000000000000000000000000000000000000000000000000000000010000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[8]}; |
---|
563 | 64'b0000000000000000000000000000000000000000000000000000000000001000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[9]}; |
---|
564 | 64'b0000000000000000000000000000000000000000000000000000000000000100 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[10]}; |
---|
565 | 64'b0000000000000000000000000000000000000000000000000000000000000010 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[11]}; |
---|
566 | 64'b0000000000000000000000000000000000000000000000000000000000000001 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[12]}; |
---|
567 | default : slv_ip2bus_data <= 0; |
---|
568 | endcase |
---|
569 | |
---|
570 | end // SLAVE_REG_READ_PROC |
---|
571 | |
---|
572 | /* Address map: |
---|
573 | HDL is coded [MSB:LSB] = [0:31] |
---|
574 | regX[ 0] maps to 0x80000000 in C driver |
---|
575 | regX[31] maps to 0x00000001 in C driver |
---|
576 | |
---|
577 | 0: RW: MAX2829 control signals and control source (sw vs. hw) |
---|
578 | Mask for RFA: 0x000000FF |
---|
579 | Mask for RFB: 0x0000FF00 |
---|
580 | Mask for RFC: 0x00FF0000 |
---|
581 | Mask for RFD: 0xFF000000 |
---|
582 | [ 0: 3] = RFD Control: {TxEn, RxEn, RxHP, SHDN} |
---|
583 | [ 4: 7] = RFD Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) |
---|
584 | [ 8:11] = RFC Control: {TxEn, RxEn, RxHP, SHDN} |
---|
585 | [12:15] = RFC Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) |
---|
586 | [16:19] = RFB Control: {TxEn, RxEn, RxHP, SHDN} |
---|
587 | [20:23] = RFB Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) |
---|
588 | [24:27] = RFA Control: {TxEn, RxEn, RxHP, SHDN} |
---|
589 | [28:31] = RFA Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) |
---|
590 | |
---|
591 | 1: RW: Tx Timing |
---|
592 | Shared by all RF interfaces |
---|
593 | [ 0: 7] = Delay before Tx VGA ramp start 0xFF000000 |
---|
594 | [ 8:15] = Delay before PA enable 0x00FF0000 |
---|
595 | [16:23] = Delay before MAX2829 TxEn assertion 0x0000FF00 |
---|
596 | [24:31] = Delay before usr_startPHY assertion 0x000000FF |
---|
597 | |
---|
598 | 2: RW: Tx Gains |
---|
599 | [ 0] = RF D Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x80000000 |
---|
600 | [ 1] = Reserved |
---|
601 | [ 2: 7] = RF D Tx Gain 0x3F000000 |
---|
602 | [ 8] = RF C Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00800000 |
---|
603 | [ 9] = Reserved |
---|
604 | [10:15] = RF C Tx Gain 0x003F0000 |
---|
605 | [ 16] = RF B Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00008000 |
---|
606 | [ 17] = Reserved |
---|
607 | [18:23] = RF B Tx Gain 0x00003F00 |
---|
608 | [ 24] = RF A Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00000080 |
---|
609 | [ 25] = Reserved |
---|
610 | [26:31] = RF A Tx Gain 0x0000003F |
---|
611 | |
---|
612 | 3: RW: Rx gains |
---|
613 | [ 0] = RFD Rx gain ctrl source (0=register values, 1=usr_ ports) |
---|
614 | [ 1: 2] = RFD Rx RF Gain |
---|
615 | [ 3: 7] = RFD Rx BB Gain |
---|
616 | [ 8] = RFC Rx gain ctrl source (0=register values, 1=usr_ ports) |
---|
617 | [ 9:10] = RFC Rx RF Gain |
---|
618 | [11:15] = RFC Rx BB Gain |
---|
619 | [ 16] = RFB Rx gain ctrl source (0=register values, 1=usr_ ports) |
---|
620 | [17:18] = RFB Rx RF Gain |
---|
621 | [19:23] = RFB Rx BB Gain |
---|
622 | [ 24] = RFA Rx gain ctrl source (0=register values, 1=usr_ ports) |
---|
623 | [25:26] = RFA Rx RF Gain |
---|
624 | [27:31] = RFA Rx BB Gain |
---|
625 | |
---|
626 | 4: RW: Clock dividers & Tx gain ramp config |
---|
627 | [ 0:12] = Reserved |
---|
628 | [13:15] = DAC SPI clock divider 0x00070000 |
---|
629 | [16:19] = Tx VGA ramp time step 0x0000F000 |
---|
630 | [20:23] = Tx VGA ramp gain step 0x00000F00 |
---|
631 | [ 24] = Reserved 0x00000080 |
---|
632 | [25:27] = RF SPI clock divider 0x00000070 |
---|
633 | [28:29] = Reserved 0x0000000C |
---|
634 | [30:31] = TxTiming clock divider 0x00000003 |
---|
635 | |
---|
636 | 5: WO: MAX2829 SPI write register |
---|
637 | Special register: |
---|
638 | * Write from software triggers SPI transaction |
---|
639 | * IPIF WrACK delayed until SPI is done (i.e. software doesn't have to poll; Xil_Out32 blocks until SPI is done) |
---|
640 | * Reads of this register return last SPI word transferred by software (might be stale, if usr_ SPI ports are also used) |
---|
641 | [ 0: 3] SPI chip select mask RF[D:A] 0x80000000=RFD, 0x40000000=RFC, 0x20000000=RFB, 0x10000000=RFA |
---|
642 | [ 4:11] Reserved 0x0FF00000 |
---|
643 | [12:15] Register address to write 0x000F0000 (MAX2829 registers have 4 bit addresses) |
---|
644 | [16:17] Reserved 0x0000C000 |
---|
645 | [18:31] Register value to write 0x00003FFF (MAX2829 registers are all 14 bits) |
---|
646 | |
---|
647 | 6: WO: DAC SPI write register |
---|
648 | Special register: |
---|
649 | * Write from software triggers SPI transaction |
---|
650 | * IPIF WrACK delayed until SPI is done (i.e. software doesn't have to poll; Xil_Out32 blocks until SPI is done) |
---|
651 | * Reads of this register return last SPI word transferred by software (might be stale, if usr_ SPI ports are also used) |
---|
652 | [ 0: 3] SPI chip select mask RF[D:A] 0x80000000=RFD, 0x40000000=RFC, 0x20000000=RFB, 0x10000000=RFA |
---|
653 | [ 4:10] Reserved 0x0FE00000 |
---|
654 | [ 11] RNW 0x00100000 |
---|
655 | [12:15] Register address to write 0x000F0000 (AD9777 registers have 5 bit addresses, but MSB is always 0) |
---|
656 | [16:23] Reserved 0x0000FF00 |
---|
657 | [24:31] Register value to write 0x000000FF (AD9777 registers are all 8 bits) |
---|
658 | |
---|
659 | 7: RO: DAC SPI Rx: {RFA_DAC_rxByte, RFB_DAC_rxByte, RFC_DAC_rxByte, RFD_DAC_rxByte} |
---|
660 | [ 0: 7] SPI Rx byte for RFD_DAC 0xFF000000 |
---|
661 | [ 8:15] SPI Rx byte for RFC_DAC 0x00FF0000 |
---|
662 | [16:23] SPI Rx byte for RFB_DAC 0x0000FF00 |
---|
663 | [24:31] SPI Rx byte for RFA_DAC 0x000000FF |
---|
664 | |
---|
665 | 8: Radio Board aux config outputs |
---|
666 | [ 0: 6] RFA aux cfg: {ADC_DCS, ADC_DFS, ADC_PWDN, RSSI_ADC_CLAMP, RSSI_ADC_HIZ, RSSI_ADC_SLEEP, DAC_RESET} |
---|
667 | [ 7] RFA ant switch mode (0: Tx/Rx on J1; 1: Tx/Rx on J2) |
---|
668 | [ 8:14] RFB aux cfg: {ADC_DCS, ADC_DFS, ADC_PWDN, RSSI_ADC_CLAMP, RSSI_ADC_HIZ, RSSI_ADC_SLEEP, DAC_RESET} |
---|
669 | [ 15] RFB ant switch mode (0: Tx/Rx on J1; 1: Tx/Rx on J2) |
---|
670 | [16:22] RFC aux cfg: {ADC_DCS, ADC_DFS, ADC_PWDN, RSSI_ADC_CLAMP, RSSI_ADC_HIZ, RSSI_ADC_SLEEP, DAC_RESET} |
---|
671 | [ 23] RFC ant switch mode (0: Tx/Rx on J1; 1: Tx/Rx on J2) |
---|
672 | [24:30] RFD aux cfg: {ADC_DCS, ADC_DFS, ADC_PWDN, RSSI_ADC_CLAMP, RSSI_ADC_HIZ, RSSI_ADC_SLEEP, DAC_RESET} |
---|
673 | [ 31] RFD ant switch mode (0: Tx/Rx on J1; 1: Tx/Rx on J2) |
---|
674 | |
---|
675 | 9: Radio Board aux status inputs |
---|
676 | [ 0: 3] RFA DIP Switch |
---|
677 | [ 4] RFA DAC PLL Lock |
---|
678 | [ 5: 7] Reserved |
---|
679 | [ 8:11] RFB DIP Switch |
---|
680 | [ 12] RFB DAC PLL Lock |
---|
681 | [13:15] Reserved |
---|
682 | [16:19] RFC DIP Switch |
---|
683 | [ 20] RFC DAC PLL Lock |
---|
684 | [21:23] Reserved |
---|
685 | [24:27] RFD DIP Switch |
---|
686 | [ 28] RFD DAC PLL Lock |
---|
687 | [29:31] Reserved |
---|
688 | |
---|
689 | 10: Reserved (RW 32-bit register implemented; no connection to external hardware) |
---|
690 | |
---|
691 | 11: RO: Status bits |
---|
692 | Same per-RF masks as reg[0], same control signal masks as reg[0] |
---|
693 | [ 0: 3] = RFD control status {TxEn, RxEn, RxHP, SHDN} |
---|
694 | [ 4] = RFD MAX2829 PLL locked (1=locked) |
---|
695 | [ 5] = RFD SPI transfer in progress |
---|
696 | [ 6: 7] = Reserved |
---|
697 | |
---|
698 | [ 8:11] = RFC control status {TxEn, RxEn, RxHP, SHDN} |
---|
699 | [ 12] = RFC MAX2829 PLL locked (1=locked) |
---|
700 | [ 13] = RFC SPI transfer in progress |
---|
701 | [14:15] = Reserved |
---|
702 | |
---|
703 | [16:19] = RFB control status {TxEn, RxEn, RxHP, SHDN} |
---|
704 | [ 20] = RFB MAX2829 PLL locked (1=locked) |
---|
705 | [ 21] = RFB SPI transfer in progress |
---|
706 | [22:23] = Reserved |
---|
707 | |
---|
708 | [24:27] = RFA control status {TxEn, RxEn, RxHP, SHDN} |
---|
709 | [ 28] = RFA MAX2829 PLL locked (1=locked) |
---|
710 | [ 29] = RFA SPI transfer in progress |
---|
711 | [30:31] = Reserved |
---|
712 | |
---|
713 | 12 to 63: RO: Read-only registers which mirror state of MAX2829 internal registers (since MAX2829 SPI is write-only) |
---|
714 | * Registers are initialized (on FPGA config and MAX2829 reset) to MAX2829 defaults, to match MAX2829 reset state |
---|
715 | * Register values are updated automatically by SPI writes (via reg4 or via usr_ SPI port use) |
---|
716 | * Every register is: |
---|
717 | [ 0:17] Reserved; returns 0 on read |
---|
718 | [18:31] Register value (14 bits) |
---|
719 | |
---|
720 | 12...24: RO: Local copies of MAX2829 registers for RFA |
---|
721 | 12: RFA MAX2829 reg0 |
---|
722 | ... |
---|
723 | 24: RFA MAX2829 regC |
---|
724 | |
---|
725 | 25...37: RO: Local copies of MAX2829 registers for RFB |
---|
726 | 25: RFB MAX2829 reg0 |
---|
727 | ... |
---|
728 | 37: RFB MAX2829 regC |
---|
729 | |
---|
730 | 38...50: RO: Local copies of MAX2829 registers for RFC |
---|
731 | 38: RFC MAX2829 reg0 |
---|
732 | ... |
---|
733 | 50: RFC MAX2829 regC |
---|
734 | |
---|
735 | 51...63: RO: Local copies of MAX2829 registers for RFD |
---|
736 | 51: RFD MAX2829 reg0 |
---|
737 | ... |
---|
738 | 63: RFD MAX2829 regC |
---|
739 | |
---|
740 | */ |
---|
741 | |
---|
742 | //User logic -> IPIF signals |
---|
743 | assign IP2Bus_Data = slv_ip2bus_data; |
---|
744 | assign IP2Bus_RdAck = slv_read_ack; |
---|
745 | assign IP2Bus_Error = 0; |
---|
746 | |
---|
747 | //spi_X_tx_reg_write (Bus2IP_WrCE[x]) de-asserts as soon as transaction is ACK'd |
---|
748 | // so this mux switches back to the generic ACK as soon as the SPI xfer is done |
---|
749 | //Thus, the duration of assertion for spi_xfer_done doesn't really matter |
---|
750 | //A bit fast-n-loose, but works ok |
---|
751 | assign IP2Bus_WrAck = (spi_rf_tx_reg_write || spi_dac_tx_reg_write) ? ((spi_rf_tx_reg_write & spi_rf_xfer_done) | (spi_dac_tx_reg_write & spi_dac_xfer_done)) : slv_write_ack_normalRegisters; |
---|
752 | |
---|
753 | //Original definitions (wizard assumes all registers are RW) |
---|
754 | //slv_reg_write_sel = Bus2IP_WrCE[0:63], |
---|
755 | //slv_reg_read_sel = Bus2IP_RdCE[0:63], |
---|
756 | //slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15] || Bus2IP_RdCE[16] || Bus2IP_RdCE[17] || Bus2IP_RdCE[18] || Bus2IP_RdCE[19] || Bus2IP_RdCE[20] || Bus2IP_RdCE[21] || Bus2IP_RdCE[22] || Bus2IP_RdCE[23] || Bus2IP_RdCE[24] || Bus2IP_RdCE[25] || Bus2IP_RdCE[26] || Bus2IP_RdCE[27] || Bus2IP_RdCE[28] || Bus2IP_RdCE[29] || Bus2IP_RdCE[30] || Bus2IP_RdCE[31] || Bus2IP_RdCE[32] || Bus2IP_RdCE[33] || Bus2IP_RdCE[34] || Bus2IP_RdCE[35] || Bus2IP_RdCE[36] || Bus2IP_RdCE[37] || Bus2IP_RdCE[38] || Bus2IP_RdCE[39] || Bus2IP_RdCE[40] || Bus2IP_RdCE[41] || Bus2IP_RdCE[42] || Bus2IP_RdCE[43] || Bus2IP_RdCE[44] || Bus2IP_RdCE[45] || Bus2IP_RdCE[46] || Bus2IP_RdCE[47] || Bus2IP_RdCE[48] || Bus2IP_RdCE[49] || Bus2IP_RdCE[50] || Bus2IP_RdCE[51] || Bus2IP_RdCE[52] || Bus2IP_RdCE[53] || Bus2IP_RdCE[54] || Bus2IP_RdCE[55] || Bus2IP_RdCE[56] || Bus2IP_RdCE[57] || Bus2IP_RdCE[58] || Bus2IP_RdCE[59] || Bus2IP_RdCE[60] || Bus2IP_RdCE[61] || Bus2IP_RdCE[62] || Bus2IP_RdCE[63]; |
---|
757 | //slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15] || Bus2IP_WrCE[16] || Bus2IP_WrCE[17] || Bus2IP_WrCE[18] || Bus2IP_WrCE[19] || Bus2IP_WrCE[20] || Bus2IP_WrCE[21] || Bus2IP_WrCE[22] || Bus2IP_WrCE[23] || Bus2IP_WrCE[24] || Bus2IP_WrCE[25] || Bus2IP_WrCE[26] || Bus2IP_WrCE[27] || Bus2IP_WrCE[28] || Bus2IP_WrCE[29] || Bus2IP_WrCE[30] || Bus2IP_WrCE[31] || Bus2IP_WrCE[32] || Bus2IP_WrCE[33] || Bus2IP_WrCE[34] || Bus2IP_WrCE[35] || Bus2IP_WrCE[36] || Bus2IP_WrCE[37] || Bus2IP_WrCE[38] || Bus2IP_WrCE[39] || Bus2IP_WrCE[40] || Bus2IP_WrCE[41] || Bus2IP_WrCE[42] || Bus2IP_WrCE[43] || Bus2IP_WrCE[44] || Bus2IP_WrCE[45] || Bus2IP_WrCE[46] || Bus2IP_WrCE[47] || Bus2IP_WrCE[48] || Bus2IP_WrCE[49] || Bus2IP_WrCE[50] || Bus2IP_WrCE[51] || Bus2IP_WrCE[52] || Bus2IP_WrCE[53] || Bus2IP_WrCE[54] || Bus2IP_WrCE[55] || Bus2IP_WrCE[56] || Bus2IP_WrCE[57] || Bus2IP_WrCE[58] || Bus2IP_WrCE[59] || Bus2IP_WrCE[60] || Bus2IP_WrCE[61] || Bus2IP_WrCE[62] || Bus2IP_WrCE[63], |
---|
758 | |
---|
759 | //All registers can be read |
---|
760 | assign slv_reg_read_sel = Bus2IP_RdCE[0:63]; |
---|
761 | assign slv_read_ack = |Bus2IP_RdCE[0:63]; |
---|
762 | |
---|
763 | //Only regs 0 to 10 can be written; 12 to 63 are RO |
---|
764 | assign slv_reg_write_sel = Bus2IP_WrCE[0:10]; |
---|
765 | |
---|
766 | //Write ack for reg5 and reg6 is delayed by SPI transfer |
---|
767 | assign slv_write_ack_normalRegisters = |{Bus2IP_WrCE[0:4], Bus2IP_WrCE[7:10]}; |
---|
768 | |
---|
769 | |
---|
770 | //Register 0: MAX2829 control |
---|
771 | assign RFD_TxEn_sw = slv_reg0[ 0]; |
---|
772 | assign RFC_TxEn_sw = slv_reg0[ 8]; |
---|
773 | assign RFB_TxEn_sw = slv_reg0[16]; |
---|
774 | assign RFA_TxEn_sw = slv_reg0[24]; |
---|
775 | |
---|
776 | assign RFD_RxEn_sw = slv_reg0[ 1]; |
---|
777 | assign RFC_RxEn_sw = slv_reg0[ 9]; |
---|
778 | assign RFB_RxEn_sw = slv_reg0[17]; |
---|
779 | assign RFA_RxEn_sw = slv_reg0[25]; |
---|
780 | |
---|
781 | assign RFD_RxHP_sw = slv_reg0[ 2]; |
---|
782 | assign RFC_RxHP_sw = slv_reg0[10]; |
---|
783 | assign RFB_RxHP_sw = slv_reg0[18]; |
---|
784 | assign RFA_RxHP_sw = slv_reg0[26]; |
---|
785 | |
---|
786 | assign RFD_SHDN_sw = slv_reg0[ 3]; |
---|
787 | assign RFC_SHDN_sw = slv_reg0[11]; |
---|
788 | assign RFB_SHDN_sw = slv_reg0[19]; |
---|
789 | assign RFA_SHDN_sw = slv_reg0[27]; |
---|
790 | |
---|
791 | assign RFD_TxEn_ctrlSrc = slv_reg0[ 4]; |
---|
792 | assign RFC_TxEn_ctrlSrc = slv_reg0[12]; |
---|
793 | assign RFB_TxEn_ctrlSrc = slv_reg0[20]; |
---|
794 | assign RFA_TxEn_ctrlSrc = slv_reg0[28]; |
---|
795 | |
---|
796 | assign RFD_RxEn_ctrlSrc = slv_reg0[ 5]; |
---|
797 | assign RFC_RxEn_ctrlSrc = slv_reg0[13]; |
---|
798 | assign RFB_RxEn_ctrlSrc = slv_reg0[21]; |
---|
799 | assign RFA_RxEn_ctrlSrc = slv_reg0[29]; |
---|
800 | |
---|
801 | assign RFD_RxHP_ctrlSrc = slv_reg0[ 6]; |
---|
802 | assign RFC_RxHP_ctrlSrc = slv_reg0[14]; |
---|
803 | assign RFB_RxHP_ctrlSrc = slv_reg0[22]; |
---|
804 | assign RFA_RxHP_ctrlSrc = slv_reg0[30]; |
---|
805 | |
---|
806 | assign RFD_SHDN_ctrlSrc = slv_reg0[ 7]; |
---|
807 | assign RFC_SHDN_ctrlSrc = slv_reg0[15]; |
---|
808 | assign RFB_SHDN_ctrlSrc = slv_reg0[23]; |
---|
809 | assign RFA_SHDN_ctrlSrc = slv_reg0[31]; |
---|
810 | |
---|
811 | //Register 1: Tx timing |
---|
812 | assign TxTiming_dly_TxGainRamp = slv_reg1[ 0: 7]; |
---|
813 | assign TxTiming_dly_PowerAmpEn = slv_reg1[ 8:15]; |
---|
814 | assign TxTiming_dly_TxEn = slv_reg1[16:23]; |
---|
815 | assign TxTiming_dly_startPHY = slv_reg1[24:31]; |
---|
816 | |
---|
817 | //Register 2: Tx gains |
---|
818 | assign RFD_TxGain_sw = slv_reg2[ 2: 7]; |
---|
819 | assign RFC_TxGain_sw = slv_reg2[10:15]; |
---|
820 | assign RFB_TxGain_sw = slv_reg2[18:23]; |
---|
821 | assign RFA_TxGain_sw = slv_reg2[26:31]; |
---|
822 | |
---|
823 | assign RFD_TxGain_ctrlSrc = slv_reg2[ 0]; |
---|
824 | assign RFC_TxGain_ctrlSrc = slv_reg2[ 8]; |
---|
825 | assign RFB_TxGain_ctrlSrc = slv_reg2[16]; |
---|
826 | assign RFA_TxGain_ctrlSrc = slv_reg2[24]; |
---|
827 | |
---|
828 | //Register 3: Rx gains |
---|
829 | assign RFD_RxGainBB_sw = slv_reg3[ 3: 7]; |
---|
830 | assign RFC_RxGainBB_sw = slv_reg3[11:15]; |
---|
831 | assign RFB_RxGainBB_sw = slv_reg3[19:23]; |
---|
832 | assign RFA_RxGainBB_sw = slv_reg3[27:31]; |
---|
833 | |
---|
834 | assign RFD_RxGainRF_sw = slv_reg3[ 1: 2]; |
---|
835 | assign RFC_RxGainRF_sw = slv_reg3[ 9:10]; |
---|
836 | assign RFB_RxGainRF_sw = slv_reg3[17:18]; |
---|
837 | assign RFA_RxGainRF_sw = slv_reg3[25:26]; |
---|
838 | |
---|
839 | assign RFD_RxGain_ctrlSrc = slv_reg3[ 0]; |
---|
840 | assign RFC_RxGain_ctrlSrc = slv_reg3[ 8]; |
---|
841 | assign RFB_RxGain_ctrlSrc = slv_reg3[16]; |
---|
842 | assign RFA_RxGain_ctrlSrc = slv_reg3[24]; |
---|
843 | |
---|
844 | //Register 4: Clock dividers & Tx gain ramp config |
---|
845 | assign spi_dac_clk_div_sel = slv_reg4[13:15]; |
---|
846 | assign TxGainRamp_timeStep = slv_reg4[16:19]; |
---|
847 | assign TxGainRamp_gainStep = slv_reg4[20:23]; |
---|
848 | assign spi_rf_clk_div_sel = slv_reg4[25:27]; |
---|
849 | assign txTiming_clk_div_sel = slv_reg4[30:31]; |
---|
850 | |
---|
851 | //Register 5: RF SPI write |
---|
852 | assign spi_rf_cs_mask_sw = slv_reg5[0:3]; |
---|
853 | assign spi_rf_tx_regdata = slv_reg5[18:31]; |
---|
854 | assign spi_rf_tx_regaddr = slv_reg5[12:15]; |
---|
855 | |
---|
856 | //Use the IPIF write-enable for the SPI Tx register as the SPI go |
---|
857 | // The bus will be paused until the SPI transfer is finished |
---|
858 | assign spi_rf_tx_reg_write = Bus2IP_WrCE[5]; |
---|
859 | |
---|
860 | //Register 6: DAC SPI write |
---|
861 | assign spi_dac_cs_mask = slv_reg6[0:3]; |
---|
862 | assign spi_dac_tx_rnw = slv_reg6[11]; |
---|
863 | assign spi_dac_tx_regaddr = slv_reg6[12:15]; |
---|
864 | assign spi_dac_tx_regdata = slv_reg6[24:31]; |
---|
865 | |
---|
866 | //Use the IPIF write-enable for the SPI Tx register as the SPI go |
---|
867 | // The bus will be paused until the SPI transfer is finished |
---|
868 | assign spi_dac_tx_reg_write = Bus2IP_WrCE[6]; |
---|
869 | |
---|
870 | //Register 7: RO, assgined in switch above |
---|
871 | |
---|
872 | //Register 8: radio board aux config outputs |
---|
873 | assign {RFA_RX_ADC_DCS, RFA_RX_ADC_DFS, RFA_RX_ADC_PWDN, RFA_RSSI_ADC_CLAMP, RFA_RSSI_ADC_HIZ, RFA_RSSI_ADC_SLEEP, RFA_DAC_RESET} = slv_reg8[ 0: 6]; |
---|
874 | assign {RFB_RX_ADC_DCS, RFB_RX_ADC_DFS, RFB_RX_ADC_PWDN, RFB_RSSI_ADC_CLAMP, RFB_RSSI_ADC_HIZ, RFB_RSSI_ADC_SLEEP, RFB_DAC_RESET} = slv_reg8[ 8:14]; |
---|
875 | assign {RFC_RX_ADC_DCS, RFC_RX_ADC_DFS, RFC_RX_ADC_PWDN, RFC_RSSI_ADC_CLAMP, RFC_RSSI_ADC_HIZ, RFC_RSSI_ADC_SLEEP, RFC_DAC_RESET} = slv_reg8[16:22]; |
---|
876 | assign {RFD_RX_ADC_DCS, RFD_RX_ADC_DFS, RFD_RX_ADC_PWDN, RFD_RSSI_ADC_CLAMP, RFD_RSSI_ADC_HIZ, RFD_RSSI_ADC_SLEEP, RFD_DAC_RESET} = slv_reg8[24:30]; |
---|
877 | |
---|
878 | assign RFA_AntSw_mode = slv_reg8[7]; |
---|
879 | assign RFB_AntSw_mode = slv_reg8[15]; |
---|
880 | assign RFC_AntSw_mode = slv_reg8[23]; |
---|
881 | assign RFD_AntSw_mode = slv_reg8[31]; |
---|
882 | |
---|
883 | //Register 9: aux status inputs |
---|
884 | assign radio_aux_status_bits_reg[0:31] = {RFA_DIPSW, RFA_DAC_PLLLOCK, 3'b0, RFB_DIPSW, RFB_DAC_PLLLOCK, 3'b0, RFC_DIPSW, RFC_DAC_PLLLOCK, 3'b0, RFD_DIPSW, RFD_DAC_PLLLOCK, 3'b0}; |
---|
885 | |
---|
886 | //Register 11: Read-only status bits |
---|
887 | assign status_reg[ 0: 3] = {RFD_TxEn, RFD_RxEn, RFD_RxHP, RFD_SHDN}; |
---|
888 | assign status_reg[ 4: 7] = {RFD_LD, ~RFD_SPI_CSn, RFD_PAEn_24, RFD_PAEn_5}; |
---|
889 | |
---|
890 | assign status_reg[ 8:11] = {RFC_TxEn, RFC_RxEn, RFC_RxHP, RFC_SHDN}; |
---|
891 | assign status_reg[12:15] = {RFC_LD, ~RFC_SPI_CSn, RFC_PAEn_24, RFC_PAEn_5}; |
---|
892 | |
---|
893 | assign status_reg[16:19] = {RFB_TxEn, RFB_RxEn, RFB_RxHP, RFB_SHDN}; |
---|
894 | assign status_reg[20:23] = {RFB_LD, ~RFB_SPI_CSn, RFB_PAEn_24, RFB_PAEn_5}; |
---|
895 | |
---|
896 | assign status_reg[24:27] = {RFA_TxEn, RFA_RxEn, RFA_RxHP, RFA_SHDN}; |
---|
897 | assign status_reg[28:31] = {RFA_LD, ~RFA_SPI_CSn, RFA_PAEn_24, RFA_PAEn_5}; |
---|
898 | |
---|
899 | //Mux the various control signals between software and hardware control |
---|
900 | assign RFA_txStart = RFA_TxEn_ctrlSrc ? usr_RFA_TxEn : RFA_TxEn_sw; |
---|
901 | assign RFB_txStart = RFB_TxEn_ctrlSrc ? usr_RFB_TxEn : RFB_TxEn_sw; |
---|
902 | assign RFC_txStart = RFC_TxEn_ctrlSrc ? usr_RFC_TxEn : RFC_TxEn_sw; |
---|
903 | assign RFD_txStart = RFD_TxEn_ctrlSrc ? usr_RFD_TxEn : RFD_TxEn_sw; |
---|
904 | |
---|
905 | assign RFA_RxEn = RFA_RxEn_ctrlSrc ? usr_RFA_RxEn : RFA_RxEn_sw; |
---|
906 | assign RFB_RxEn = RFB_RxEn_ctrlSrc ? usr_RFB_RxEn : RFB_RxEn_sw; |
---|
907 | assign RFC_RxEn = RFC_RxEn_ctrlSrc ? usr_RFC_RxEn : RFC_RxEn_sw; |
---|
908 | assign RFD_RxEn = RFD_RxEn_ctrlSrc ? usr_RFD_RxEn : RFD_RxEn_sw; |
---|
909 | |
---|
910 | assign RFA_RxHP = RFA_RxHP_ctrlSrc ? usr_RFA_RxHP : RFA_RxHP_sw; |
---|
911 | assign RFB_RxHP = RFB_RxHP_ctrlSrc ? usr_RFB_RxHP : RFB_RxHP_sw; |
---|
912 | assign RFC_RxHP = RFC_RxHP_ctrlSrc ? usr_RFC_RxHP : RFC_RxHP_sw; |
---|
913 | assign RFD_RxHP = RFD_RxHP_ctrlSrc ? usr_RFD_RxHP : RFD_RxHP_sw; |
---|
914 | |
---|
915 | assign RFA_SHDN = RFA_SHDN_ctrlSrc ? usr_RFA_SHDN : RFA_SHDN_sw; |
---|
916 | assign RFB_SHDN = RFB_SHDN_ctrlSrc ? usr_RFB_SHDN : RFB_SHDN_sw; |
---|
917 | assign RFC_SHDN = RFC_SHDN_ctrlSrc ? usr_RFC_SHDN : RFC_SHDN_sw; |
---|
918 | assign RFD_SHDN = RFD_SHDN_ctrlSrc ? usr_RFD_SHDN : RFD_SHDN_sw; |
---|
919 | |
---|
920 | assign RFA_TxGain_target = RFA_TxGain_ctrlSrc ? usr_RFA_TxGain : RFA_TxGain_sw; |
---|
921 | assign RFB_TxGain_target = RFB_TxGain_ctrlSrc ? usr_RFB_TxGain : RFB_TxGain_sw; |
---|
922 | assign RFC_TxGain_target = RFC_TxGain_ctrlSrc ? usr_RFC_TxGain : RFC_TxGain_sw; |
---|
923 | assign RFD_TxGain_target = RFD_TxGain_ctrlSrc ? usr_RFD_TxGain : RFD_TxGain_sw; |
---|
924 | |
---|
925 | assign RFA_RxGainBB = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainBB : RFA_RxGainBB_sw; |
---|
926 | assign RFB_RxGainBB = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainBB : RFB_RxGainBB_sw; |
---|
927 | assign RFC_RxGainBB = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainBB : RFC_RxGainBB_sw; |
---|
928 | assign RFD_RxGainBB = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainBB : RFD_RxGainBB_sw; |
---|
929 | |
---|
930 | assign RFA_RxGainRF = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainRF : RFA_RxGainRF_sw; |
---|
931 | assign RFB_RxGainRF = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainRF : RFB_RxGainRF_sw; |
---|
932 | assign RFC_RxGainRF = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainRF : RFC_RxGainRF_sw; |
---|
933 | assign RFD_RxGainRF = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainRF : RFD_RxGainRF_sw; |
---|
934 | |
---|
935 | |
---|
936 | //Output OR'd PHYStart signal (most PHYs use this, so any TxEnable will start the PHY) |
---|
937 | // Individual PHYStarts are provided in case user has multiple PHYs connected to different RF paths |
---|
938 | assign usr_any_PHYStart = usr_RFA_PHYStart || usr_RFB_PHYStart || usr_RFC_PHYStart || usr_RFD_PHYStart; |
---|
939 | |
---|
940 | //Ant switch needs time to settle, so make the switch as soon as we know Tx process is starting |
---|
941 | //2-bit control signal in hardware, but only two valid states: |
---|
942 | // [V1 V2] = [1 0] => Rx path connected to SMA (PA must be off!) |
---|
943 | // [V1 V2] = [0 1] => Tx path connected to SMA |
---|
944 | assign RFA_AntSw[0:1] = RFA_AntSw_mode ? {RFA_txStart, ~RFA_txStart} : {~RFA_txStart, RFA_txStart}; |
---|
945 | assign RFB_AntSw[0:1] = RFB_AntSw_mode ? {RFB_txStart, ~RFB_txStart} : {~RFB_txStart, RFB_txStart}; |
---|
946 | assign RFC_AntSw[0:1] = RFC_AntSw_mode ? {RFC_txStart, ~RFC_txStart} : {~RFC_txStart, RFC_txStart}; |
---|
947 | assign RFD_AntSw[0:1] = RFD_AntSw_mode ? {RFD_txStart, ~RFD_txStart} : {~RFD_txStart, RFD_txStart}; |
---|
948 | |
---|
949 | //PAs are enabled by single wire per band |
---|
950 | // ACTIVE LOW FOR WARP RADIO BOARD v1.4 |
---|
951 | // One path's 2.4 and 5GHz PAs should never be enabled simultaneously |
---|
952 | //2.4GHz PA is on when: |
---|
953 | // TxTiming state machine asserts PAEn AND |
---|
954 | // MAX2829.reg5[0] == 0 (indicating MAX2829 is tuned to 2.4GHz band) |
---|
955 | //5GHz PA is on when: |
---|
956 | // TxTiming state machine asserts PAEn AND |
---|
957 | // MAX2829.reg5[0] == 1 (indicating MAX2829 is tuned to 5GHz band) |
---|
958 | //RFx_MAX2829_mirrorRegs are indexed [MSB:LSB]=[0:13] to match other busses in this core, |
---|
959 | // so the LSB (bit [0] in MAX2829 datasheet) is RFA_MAX2829_mirrorRegs[x][13] here |
---|
960 | assign RFA_PAEn_24 = ~(RFA_PAEn & ~(RFA_MAX2829_mirrorRegs[5][13])); |
---|
961 | assign RFB_PAEn_24 = ~(RFB_PAEn & ~(RFB_MAX2829_mirrorRegs[5][13])); |
---|
962 | assign RFC_PAEn_24 = ~(RFC_PAEn & ~(RFC_MAX2829_mirrorRegs[5][13])); |
---|
963 | assign RFD_PAEn_24 = ~(RFD_PAEn & ~(RFD_MAX2829_mirrorRegs[5][13])); |
---|
964 | |
---|
965 | assign RFA_PAEn_5 = ~(RFA_PAEn & (RFA_MAX2829_mirrorRegs[5][13])); |
---|
966 | assign RFB_PAEn_5 = ~(RFB_PAEn & (RFB_MAX2829_mirrorRegs[5][13])); |
---|
967 | assign RFC_PAEn_5 = ~(RFC_PAEn & (RFC_MAX2829_mirrorRegs[5][13])); |
---|
968 | assign RFD_PAEn_5 = ~(RFD_PAEn & (RFD_MAX2829_mirrorRegs[5][13])); |
---|
969 | |
---|
970 | //MAX2829 gain control bus |
---|
971 | // radio_controller.RFx_B[6:0] maps to MAX2829.B[7:1] |
---|
972 | // radio_controller.RFx_B[6] is MSB, radio_controller.RFx_B[0] is LSB |
---|
973 | // MAX2829.B7 is MSB, MAX2829.B1 is LSB |
---|
974 | // Note the RFx_B port is endian swapped relative to other busses in this core |
---|
975 | // to match the MAX2829 B port |
---|
976 | //When SPI gain control is disabled: |
---|
977 | // In Tx mode: |
---|
978 | // MAX2829.B[7] is don't care |
---|
979 | // MAX2829.B[6:1] = Tx RF VGA (6'd63 is max gain, 6'd0 is min gain (approx max-30dB)) |
---|
980 | // In Rx mode: |
---|
981 | // MAX2829.B[7:6] = Rx RF LNA (2'd3 is max gain (30dB), 2'd1 is min gain (0dB), 2'd0 is invalid) |
---|
982 | // MAX2829.B[5:1] = Rx BB VGA (5'd31 is max gain (approx 62dB), 5'd0 is min gain (approx 0dB) |
---|
983 | assign {RFA_B[6], RFA_B[5], RFA_B[4], RFA_B[3], RFA_B[2], RFA_B[1], RFA_B[0]} = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB}; |
---|
984 | assign {RFB_B[6], RFB_B[5], RFB_B[4], RFB_B[3], RFB_B[2], RFB_B[1], RFB_B[0]} = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB}; |
---|
985 | assign {RFC_B[6], RFC_B[5], RFC_B[4], RFC_B[3], RFC_B[2], RFC_B[1], RFC_B[0]} = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB}; |
---|
986 | assign {RFD_B[6], RFD_B[5], RFD_B[4], RFD_B[3], RFD_B[2], RFD_B[1], RFD_B[0]} = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB}; |
---|
987 | |
---|
988 | |
---|
989 | //Simple state machines for fixed timing of Tx events (MAX2829 TxEn, PA enable and PHY start) |
---|
990 | // One per RF path, to handle case of user designs which do Tx/Rx asychronously across paths |
---|
991 | // All use same timing values, as these are really tuned to the hardware, not the Tx signal |
---|
992 | radio_controller_TxTiming RFA_txTiming ( |
---|
993 | .clk(Bus2IP_Clk), |
---|
994 | .reset(Bus2IP_Reset), |
---|
995 | |
---|
996 | .clk_div(txTiming_clk_div_sel), |
---|
997 | |
---|
998 | .sw_start(RFA_txStart), |
---|
999 | |
---|
1000 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
1001 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
1002 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
1003 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
1004 | |
---|
1005 | .gainRamp_TxGainTarget(RFA_TxGain_target), |
---|
1006 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
1007 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
1008 | .gainRamp_TxGainOut(RFA_TxGain_ramped), |
---|
1009 | |
---|
1010 | .TxEn(RFA_TxEn), |
---|
1011 | .PAEn(RFA_PAEn), |
---|
1012 | .PHYStart(usr_RFA_PHYStart) |
---|
1013 | ); |
---|
1014 | radio_controller_TxTiming RFB_txTiming ( |
---|
1015 | .clk(Bus2IP_Clk), |
---|
1016 | .reset(Bus2IP_Reset), |
---|
1017 | |
---|
1018 | .clk_div(txTiming_clk_div_sel), |
---|
1019 | |
---|
1020 | .sw_start(RFB_txStart), |
---|
1021 | |
---|
1022 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
1023 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
1024 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
1025 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
1026 | |
---|
1027 | .gainRamp_TxGainTarget(RFB_TxGain_target), |
---|
1028 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
1029 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
1030 | .gainRamp_TxGainOut(RFB_TxGain_ramped), |
---|
1031 | |
---|
1032 | .TxEn(RFB_TxEn), |
---|
1033 | .PAEn(RFB_PAEn), |
---|
1034 | .PHYStart(usr_RFB_PHYStart) |
---|
1035 | ); |
---|
1036 | radio_controller_TxTiming RFC_txTiming ( |
---|
1037 | .clk(Bus2IP_Clk), |
---|
1038 | .reset(Bus2IP_Reset), |
---|
1039 | |
---|
1040 | .clk_div(txTiming_clk_div_sel), |
---|
1041 | |
---|
1042 | .sw_start(RFC_txStart), |
---|
1043 | |
---|
1044 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
1045 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
1046 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
1047 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
1048 | |
---|
1049 | .gainRamp_TxGainTarget(RFC_TxGain_target), |
---|
1050 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
1051 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
1052 | .gainRamp_TxGainOut(RFC_TxGain_ramped), |
---|
1053 | |
---|
1054 | .TxEn(RFC_TxEn), |
---|
1055 | .PAEn(RFC_PAEn), |
---|
1056 | .PHYStart(usr_RFC_PHYStart) |
---|
1057 | ); |
---|
1058 | radio_controller_TxTiming RFD_txTiming ( |
---|
1059 | .clk(Bus2IP_Clk), |
---|
1060 | .reset(Bus2IP_Reset), |
---|
1061 | |
---|
1062 | .clk_div(txTiming_clk_div_sel), |
---|
1063 | |
---|
1064 | .sw_start(RFD_txStart), |
---|
1065 | |
---|
1066 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
1067 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
1068 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
1069 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
1070 | |
---|
1071 | .gainRamp_TxGainTarget(RFD_TxGain_target), |
---|
1072 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
1073 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
1074 | .gainRamp_TxGainOut(RFD_TxGain_ramped), |
---|
1075 | |
---|
1076 | .TxEn(RFD_TxEn), |
---|
1077 | .PAEn(RFD_PAEn), |
---|
1078 | .PHYStart(usr_RFD_PHYStart) |
---|
1079 | ); |
---|
1080 | |
---|
1081 | //Signals to detect when MAX2829 hardware reset occurs (TxEn=1, RxEn=1, SHDN=0) |
---|
1082 | // Reset can be triggered by hardware or software, depending on the user config |
---|
1083 | assign RFA_MAX2829_Reset = (RFA_TxEn & RFA_RxEn & ~RFA_SHDN); |
---|
1084 | assign RFB_MAX2829_Reset = (RFB_TxEn & RFB_RxEn & ~RFB_SHDN); |
---|
1085 | assign RFC_MAX2829_Reset = (RFC_TxEn & RFC_RxEn & ~RFC_SHDN); |
---|
1086 | assign RFD_MAX2829_Reset = (RFD_TxEn & RFD_RxEn & ~RFD_SHDN); |
---|
1087 | |
---|
1088 | //Use a counter to generate a blinking error signal to indicate a radio in standby that hasn't yet locked |
---|
1089 | reg [23:0] error_blink_counter = 24'b0; |
---|
1090 | always @(posedge Bus2IP_Clk) |
---|
1091 | error_blink_counter <= error_blink_counter + 1; |
---|
1092 | |
---|
1093 | assign usr_RFA_statLED_Tx = RFA_SHDN ? (RFA_TxEn | ((~RFA_LD) & error_blink_counter[23])) : 1'b0; |
---|
1094 | assign usr_RFA_statLED_Rx = RFA_SHDN ? (RFA_RxEn | ((~RFA_LD) & error_blink_counter[23])) : 1'b0; |
---|
1095 | |
---|
1096 | assign usr_RFB_statLED_Tx = RFB_SHDN ? (RFB_TxEn | ((~RFB_LD) & error_blink_counter[23])) : 1'b0; |
---|
1097 | assign usr_RFB_statLED_Rx = RFB_SHDN ? (RFB_RxEn | ((~RFB_LD) & error_blink_counter[23])) : 1'b0; |
---|
1098 | |
---|
1099 | assign usr_RFC_statLED_Tx = RFC_SHDN ? (RFC_TxEn | ((~RFC_LD) & error_blink_counter[23])) : 1'b0; |
---|
1100 | assign usr_RFC_statLED_Rx = RFC_SHDN ? (RFC_RxEn | ((~RFC_LD) & error_blink_counter[23])) : 1'b0; |
---|
1101 | |
---|
1102 | assign usr_RFD_statLED_Tx = RFD_SHDN ? (RFD_TxEn | ((~RFD_LD) & error_blink_counter[23])) : 1'b0; |
---|
1103 | assign usr_RFD_statLED_Rx = RFD_SHDN ? (RFD_RxEn | ((~RFD_LD) & error_blink_counter[23])) : 1'b0; |
---|
1104 | |
---|
1105 | |
---|
1106 | //Mask per-RF path to enable SPI transactions |
---|
1107 | // Driven by register for software control, usr_ port for hardware control |
---|
1108 | assign spi_rf_cs_mask = usr_SPI_ctrlSrc ? usr_SPI_rfsel : spi_rf_cs_mask_sw; |
---|
1109 | |
---|
1110 | |
---|
1111 | //Processes to update mirror registers following SPI write |
---|
1112 | // Note these registers are *not* changed by a software reset |
---|
1113 | // The only reset condition is the MAX2829 hardware reset (TxEn=1, RxEn=1, SHDN=0) |
---|
1114 | always @(posedge Bus2IP_Clk) |
---|
1115 | begin |
---|
1116 | if(RFA_MAX2829_Reset) |
---|
1117 | begin |
---|
1118 | RFA_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
---|
1119 | RFA_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
---|
1120 | RFA_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
---|
1121 | RFA_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
---|
1122 | RFA_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
---|
1123 | RFA_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
---|
1124 | RFA_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
---|
1125 | RFA_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
---|
1126 | RFA_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
---|
1127 | RFA_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
---|
1128 | RFA_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
---|
1129 | RFA_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
---|
1130 | RFA_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
---|
1131 | end |
---|
1132 | else if(spi_rf_go) |
---|
1133 | begin |
---|
1134 | if(spi_rf_cs_mask & 4'b0001) //RFA selected |
---|
1135 | RFA_MAX2829_mirrorRegs[spi_rf_tx_regaddr] <= spi_rf_tx_regdata; |
---|
1136 | end |
---|
1137 | end |
---|
1138 | |
---|
1139 | always @(posedge Bus2IP_Clk) |
---|
1140 | begin |
---|
1141 | if(RFB_MAX2829_Reset) |
---|
1142 | begin |
---|
1143 | RFB_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
---|
1144 | RFB_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
---|
1145 | RFB_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
---|
1146 | RFB_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
---|
1147 | RFB_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
---|
1148 | RFB_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
---|
1149 | RFB_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
---|
1150 | RFB_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
---|
1151 | RFB_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
---|
1152 | RFB_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
---|
1153 | RFB_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
---|
1154 | RFB_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
---|
1155 | RFB_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
---|
1156 | end |
---|
1157 | else if(spi_rf_go) |
---|
1158 | begin |
---|
1159 | if(spi_rf_cs_mask & 4'b0010) //RFB selected |
---|
1160 | RFB_MAX2829_mirrorRegs[spi_rf_tx_regaddr] <= spi_rf_tx_regdata; |
---|
1161 | end |
---|
1162 | end |
---|
1163 | |
---|
1164 | always @(posedge Bus2IP_Clk) |
---|
1165 | begin |
---|
1166 | if(RFC_MAX2829_Reset) |
---|
1167 | begin |
---|
1168 | RFC_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
---|
1169 | RFC_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
---|
1170 | RFC_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
---|
1171 | RFC_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
---|
1172 | RFC_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
---|
1173 | RFC_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
---|
1174 | RFC_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
---|
1175 | RFC_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
---|
1176 | RFC_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
---|
1177 | RFC_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
---|
1178 | RFC_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
---|
1179 | RFC_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
---|
1180 | RFC_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
---|
1181 | end |
---|
1182 | else if(spi_rf_go) |
---|
1183 | begin |
---|
1184 | if(spi_rf_cs_mask & 4'b0100) //RFC selected |
---|
1185 | RFC_MAX2829_mirrorRegs[spi_rf_tx_regaddr] <= spi_rf_tx_regdata; |
---|
1186 | end |
---|
1187 | end |
---|
1188 | |
---|
1189 | always @(posedge Bus2IP_Clk) |
---|
1190 | begin |
---|
1191 | if(RFD_MAX2829_Reset) |
---|
1192 | begin |
---|
1193 | RFD_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
---|
1194 | RFD_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
---|
1195 | RFD_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
---|
1196 | RFD_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
---|
1197 | RFD_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
---|
1198 | RFD_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
---|
1199 | RFD_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
---|
1200 | RFD_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
---|
1201 | RFD_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
---|
1202 | RFD_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
---|
1203 | RFD_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
---|
1204 | RFD_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
---|
1205 | RFD_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
---|
1206 | end |
---|
1207 | else if(spi_rf_go) |
---|
1208 | begin |
---|
1209 | if(spi_rf_cs_mask & 4'b1000) //RFD selected |
---|
1210 | RFD_MAX2829_mirrorRegs[spi_rf_tx_regaddr] <= spi_rf_tx_regdata; |
---|
1211 | end |
---|
1212 | end |
---|
1213 | |
---|
1214 | wire spi_rf_cs; |
---|
1215 | wire spi_rf_mosi; |
---|
1216 | wire spi_rf_sclk; |
---|
1217 | |
---|
1218 | //MAX2829 SPI controller |
---|
1219 | //MAX2829 CS is active-low; warp_spi_io.spi_cs is active high |
---|
1220 | assign RFA_SPI_CSn = ~(spi_rf_cs_mask[3] & spi_rf_cs); |
---|
1221 | assign RFB_SPI_CSn = ~(spi_rf_cs_mask[2] & spi_rf_cs); |
---|
1222 | assign RFC_SPI_CSn = ~(spi_rf_cs_mask[1] & spi_rf_cs); |
---|
1223 | assign RFD_SPI_CSn = ~(spi_rf_cs_mask[0] & spi_rf_cs); |
---|
1224 | |
---|
1225 | assign RFA_SPI_MOSI = spi_rf_mosi; |
---|
1226 | assign RFB_SPI_MOSI = spi_rf_mosi; |
---|
1227 | assign RFC_SPI_MOSI = spi_rf_mosi; |
---|
1228 | assign RFD_SPI_MOSI = spi_rf_mosi; |
---|
1229 | |
---|
1230 | //Mask each SCLK output by the corresponding CS |
---|
1231 | // No point toggling SCLKs that will be ignored |
---|
1232 | assign RFA_SPI_SCLK = (spi_rf_sclk & spi_rf_cs_mask[3]); |
---|
1233 | assign RFB_SPI_SCLK = (spi_rf_sclk & spi_rf_cs_mask[2]); |
---|
1234 | assign RFC_SPI_SCLK = (spi_rf_sclk & spi_rf_cs_mask[1]); |
---|
1235 | assign RFD_SPI_SCLK = (spi_rf_sclk & spi_rf_cs_mask[0]); |
---|
1236 | |
---|
1237 | //MAX2829 SPI uses 18-bit transfers, formatted as {regData[0:13] regAddr[0:3]}, data and addr both transfer MSB first |
---|
1238 | wire [0:17] spi_rf_tx_data_word; |
---|
1239 | assign spi_rf_tx_data_word[0:17] = usr_SPI_ctrlSrc ? {usr_SPI_regdata, usr_SPI_regaddr} : {spi_rf_tx_regdata, spi_rf_tx_regaddr}; |
---|
1240 | |
---|
1241 | assign spi_rf_go = usr_SPI_ctrlSrc ? usr_SPI_go : spi_rf_tx_reg_write; |
---|
1242 | assign usr_SPI_active = spi_rf_cs; |
---|
1243 | |
---|
1244 | warp_spi_io #(.SPI_XFER_LEN(18)) spi_rf_io ( |
---|
1245 | .sys_clk(Bus2IP_Clk), |
---|
1246 | .reset(Bus2IP_Reset), |
---|
1247 | .go(spi_rf_go), |
---|
1248 | .done(spi_rf_xfer_done), |
---|
1249 | .clkDiv(spi_rf_clk_div_sel), |
---|
1250 | |
---|
1251 | .currBitNum(), |
---|
1252 | |
---|
1253 | .txData({14'b0, spi_rf_tx_data_word}), |
---|
1254 | |
---|
1255 | .rxData1(), |
---|
1256 | .rxData2(), |
---|
1257 | .rxData3(), |
---|
1258 | .rxData4(), |
---|
1259 | |
---|
1260 | .spi_cs(spi_rf_cs), |
---|
1261 | .spi_sclk(spi_rf_sclk), |
---|
1262 | |
---|
1263 | .spi_mosi(spi_rf_mosi), |
---|
1264 | |
---|
1265 | .spi_miso1(1'b0), |
---|
1266 | .spi_miso2(1'b0), |
---|
1267 | .spi_miso3(1'b0), |
---|
1268 | .spi_miso4(1'b0) |
---|
1269 | ); |
---|
1270 | |
---|
1271 | /// DAC SPI controller |
---|
1272 | wire spi_dac_cs; |
---|
1273 | wire spi_dac_mosi; |
---|
1274 | wire spi_dac_sclk; |
---|
1275 | |
---|
1276 | //AD9777 CS is active-low; warp_spi_io.spi_cs is active high |
---|
1277 | assign RFA_DAC_SPI_CSn = ~(spi_dac_cs_mask[3] & spi_dac_cs); |
---|
1278 | assign RFB_DAC_SPI_CSn = ~(spi_dac_cs_mask[2] & spi_dac_cs); |
---|
1279 | assign RFC_DAC_SPI_CSn = ~(spi_dac_cs_mask[1] & spi_dac_cs); |
---|
1280 | assign RFD_DAC_SPI_CSn = ~(spi_dac_cs_mask[0] & spi_dac_cs); |
---|
1281 | |
---|
1282 | assign RFA_DAC_SPI_MOSI = spi_dac_mosi; |
---|
1283 | assign RFB_DAC_SPI_MOSI = spi_dac_mosi; |
---|
1284 | assign RFC_DAC_SPI_MOSI = spi_dac_mosi; |
---|
1285 | assign RFD_DAC_SPI_MOSI = spi_dac_mosi; |
---|
1286 | |
---|
1287 | //Mask each SCLK output by the corresponding CS |
---|
1288 | // No point toggling SCLKs that will be ignored |
---|
1289 | assign RFA_DAC_SPI_SCLK = (spi_dac_sclk & spi_dac_cs_mask[3]); |
---|
1290 | assign RFB_DAC_SPI_SCLK = (spi_dac_sclk & spi_dac_cs_mask[2]); |
---|
1291 | assign RFC_DAC_SPI_SCLK = (spi_dac_sclk & spi_dac_cs_mask[1]); |
---|
1292 | assign RFD_DAC_SPI_SCLK = (spi_dac_sclk & spi_dac_cs_mask[0]); |
---|
1293 | |
---|
1294 | //AD9777 SPI uses 16-bit transfers, formatted as LSB:MSB: {regData[0:7] regAddr[0:4] 0 0 RnW}, data and addr both transfer MSB first |
---|
1295 | // regAddr has 5 bits, but AD9777 only has 14 registers, so regAddr[4] is always 0 (user code only supplies 4 address bits) |
---|
1296 | wire [0:15] spi_dac_tx_data_word; |
---|
1297 | // assign spi_dac_tx_data_word[0:15] = {spi_dac_tx_regdata[0:7], spi_dac_tx_regaddr[0:3], 3'b0, spi_dac_tx_rnw}; |
---|
1298 | assign spi_dac_tx_data_word[0:15] = {spi_dac_tx_rnw, 3'b0, spi_dac_tx_regaddr[0:3], spi_dac_tx_regdata[0:7]}; |
---|
1299 | |
---|
1300 | assign spi_dac_go = spi_dac_tx_reg_write; |
---|
1301 | |
---|
1302 | warp_spi_io #(.SPI_XFER_LEN(16)) spi_dac_io ( |
---|
1303 | .sys_clk(Bus2IP_Clk), |
---|
1304 | .reset(Bus2IP_Reset), |
---|
1305 | .go(spi_dac_go), |
---|
1306 | .done(spi_dac_xfer_done), |
---|
1307 | .clkDiv(spi_dac_clk_div_sel), |
---|
1308 | |
---|
1309 | .currBitNum(), |
---|
1310 | |
---|
1311 | .txData({16'b0, spi_dac_tx_data_word}), |
---|
1312 | |
---|
1313 | .rxData1(spi_dacA_rx_data), |
---|
1314 | .rxData2(spi_dacB_rx_data), |
---|
1315 | .rxData3(spi_dacC_rx_data), |
---|
1316 | .rxData4(spi_dacD_rx_data), |
---|
1317 | |
---|
1318 | .spi_cs(spi_dac_cs), |
---|
1319 | .spi_sclk(spi_dac_sclk), |
---|
1320 | |
---|
1321 | .spi_mosi(spi_dac_mosi), |
---|
1322 | |
---|
1323 | .spi_miso1(RFA_DAC_SPI_MISO), |
---|
1324 | .spi_miso2(RFB_DAC_SPI_MISO), |
---|
1325 | .spi_miso3(RFC_DAC_SPI_MISO), |
---|
1326 | .spi_miso4(RFD_DAC_SPI_MISO) |
---|
1327 | ); |
---|
1328 | |
---|
1329 | |
---|
1330 | endmodule |
---|
1331 | |
---|
1332 | |
---|
1333 | |
---|
1334 | |
---|
1335 | |
---|