------------------------------------------------------------------------------ -- radio_controller.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- IMPORTANT: -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. -- -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. -- -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION -- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: radio_controller.vhd -- Version: 3.00.a -- Description: Top level design, instantiates library components and user logic. -- Date: Wed Jul 04 20:55:56 2012 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "I_<#|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library plbv46_slave_single_v1_01_a; use plbv46_slave_single_v1_01_a.plbv46_slave_single; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_BASEADDR -- PLBv46 slave: base address -- C_HIGHADDR -- PLBv46 slave: high address -- C_SPLB_AWIDTH -- PLBv46 slave: address bus width -- C_SPLB_DWIDTH -- PLBv46 slave: data bus width -- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters -- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width -- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width -- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme -- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts -- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master -- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds -- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer -- C_FAMILY -- Xilinx FPGA family -- -- Definition of Ports: -- SPLB_Clk -- PLB main bus clock -- SPLB_Rst -- PLB main bus reset -- PLB_ABus -- PLB address bus -- PLB_UABus -- PLB upper address bus -- PLB_PAValid -- PLB primary address valid indicator -- PLB_SAValid -- PLB secondary address valid indicator -- PLB_rdPrim -- PLB secondary to primary read request indicator -- PLB_wrPrim -- PLB secondary to primary write request indicator -- PLB_masterID -- PLB current master identifier -- PLB_abort -- PLB abort request indicator -- PLB_busLock -- PLB bus lock -- PLB_RNW -- PLB read/not write -- PLB_BE -- PLB byte enables -- PLB_MSize -- PLB master data bus size -- PLB_size -- PLB transfer size -- PLB_type -- PLB transfer type -- PLB_lockErr -- PLB lock error indicator -- PLB_wrDBus -- PLB write data bus -- PLB_wrBurst -- PLB burst write transfer indicator -- PLB_rdBurst -- PLB burst read transfer indicator -- PLB_wrPendReq -- PLB write pending bus request indicator -- PLB_rdPendReq -- PLB read pending bus request indicator -- PLB_wrPendPri -- PLB write pending request priority -- PLB_rdPendPri -- PLB read pending request priority -- PLB_reqPri -- PLB current request priority -- PLB_TAttribute -- PLB transfer attribute -- Sl_addrAck -- Slave address acknowledge -- Sl_SSize -- Slave data bus size -- Sl_wait -- Slave wait indicator -- Sl_rearbitrate -- Slave re-arbitrate bus indicator -- Sl_wrDAck -- Slave write data acknowledge -- Sl_wrComp -- Slave write transfer complete indicator -- Sl_wrBTerm -- Slave terminate write burst transfer -- Sl_rdDBus -- Slave read data bus -- Sl_rdWdAddr -- Slave read word address -- Sl_rdDAck -- Slave read data acknowledge -- Sl_rdComp -- Slave read transfer complete indicator -- Sl_rdBTerm -- Slave terminate read burst transfer -- Sl_MBusy -- Slave busy indicator -- Sl_MWrErr -- Slave write error indicator -- Sl_MRdErr -- Slave read error indicator -- Sl_MIRQ -- Slave interrupt indicator ------------------------------------------------------------------------------ entity radio_controller is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_SPLB_AWIDTH : integer := 32; C_SPLB_DWIDTH : integer := 128; C_SPLB_NUM_MASTERS : integer := 8; C_SPLB_MID_WIDTH : integer := 3; C_SPLB_NATIVE_DWIDTH : integer := 32; C_SPLB_P2P : integer := 0; C_SPLB_SUPPORT_BURSTS : integer := 0; C_SPLB_SMALLEST_MASTER : integer := 32; C_SPLB_CLK_PERIOD_PS : integer := 10000; C_INCLUDE_DPHASE_TIMER : integer := 0; C_FAMILY : string := "virtex6" -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ RFA_TxEn : out std_logic; RFB_TxEn : out std_logic; RFC_TxEn : out std_logic; RFD_TxEn : out std_logic; RFA_RxEn : out std_logic; RFB_RxEn : out std_logic; RFC_RxEn : out std_logic; RFD_RxEn : out std_logic; RFA_RxHP : out std_logic; RFB_RxHP : out std_logic; RFC_RxHP : out std_logic; RFD_RxHP : out std_logic; RFA_SHDN : out std_logic; RFB_SHDN : out std_logic; RFC_SHDN : out std_logic; RFD_SHDN : out std_logic; RFA_SPI_SCLK : out std_logic; RFB_SPI_SCLK : out std_logic; RFC_SPI_SCLK : out std_logic; RFD_SPI_SCLK : out std_logic; RFA_SPI_MOSI : out std_logic; RFB_SPI_MOSI : out std_logic; RFC_SPI_MOSI : out std_logic; RFD_SPI_MOSI : out std_logic; RFA_SPI_CSn : out std_logic; RFB_SPI_CSn : out std_logic; RFC_SPI_CSn : out std_logic; RFD_SPI_CSn : out std_logic; RFA_B : out std_logic_vector(0 to 6); RFB_B : out std_logic_vector(0 to 6); RFC_B : out std_logic_vector(0 to 6); RFD_B : out std_logic_vector(0 to 6); RFA_LD : in std_logic; RFB_LD : in std_logic; RFC_LD : in std_logic; RFD_LD : in std_logic; RFA_PAEn_24 : out std_logic; RFB_PAEn_24 : out std_logic; RFC_PAEn_24 : out std_logic; RFD_PAEn_24 : out std_logic; RFA_PAEn_5 : out std_logic; RFB_PAEn_5 : out std_logic; RFC_PAEn_5 : out std_logic; RFD_PAEn_5 : out std_logic; RFA_AntSw : out std_logic_vector(0 to 1); RFB_AntSw : out std_logic_vector(0 to 1); RFC_AntSw : out std_logic_vector(0 to 1); RFD_AntSw : out std_logic_vector(0 to 1); RFA_DIPSW : in std_logic_vector(0 to 3); RFB_DIPSW : in std_logic_vector(0 to 3); RFC_DIPSW : in std_logic_vector(0 to 3); RFD_DIPSW : in std_logic_vector(0 to 3); RFA_RX_ADC_DCS : OUT std_logic; RFB_RX_ADC_DCS : OUT std_logic; RFC_RX_ADC_DCS : OUT std_logic; RFD_RX_ADC_DCS : OUT std_logic; RFA_RX_ADC_DFS : OUT std_logic; RFB_RX_ADC_DFS : OUT std_logic; RFC_RX_ADC_DFS : OUT std_logic; RFD_RX_ADC_DFS : OUT std_logic; RFA_RX_ADC_PWDN : OUT std_logic; RFB_RX_ADC_PWDN : OUT std_logic; RFC_RX_ADC_PWDN : OUT std_logic; RFD_RX_ADC_PWDN : OUT std_logic; RFA_RSSI_ADC_CLAMP : OUT std_logic; RFB_RSSI_ADC_CLAMP : OUT std_logic; RFC_RSSI_ADC_CLAMP : OUT std_logic; RFD_RSSI_ADC_CLAMP : OUT std_logic; RFA_RSSI_ADC_HIZ : OUT std_logic; RFB_RSSI_ADC_HIZ : OUT std_logic; RFC_RSSI_ADC_HIZ : OUT std_logic; RFD_RSSI_ADC_HIZ : OUT std_logic; RFA_RSSI_ADC_SLEEP : OUT std_logic; RFB_RSSI_ADC_SLEEP : OUT std_logic; RFC_RSSI_ADC_SLEEP : OUT std_logic; RFD_RSSI_ADC_SLEEP : OUT std_logic; RFA_DAC_SPI_CSn : OUT std_logic; RFB_DAC_SPI_CSn : OUT std_logic; RFC_DAC_SPI_CSn : OUT std_logic; RFD_DAC_SPI_CSn : OUT std_logic; RFA_DAC_SPI_SCLK : OUT std_logic; RFB_DAC_SPI_SCLK : OUT std_logic; RFC_DAC_SPI_SCLK : OUT std_logic; RFD_DAC_SPI_SCLK : OUT std_logic; RFA_DAC_SPI_MOSI : OUT std_logic; RFB_DAC_SPI_MOSI : OUT std_logic; RFC_DAC_SPI_MOSI : OUT std_logic; RFD_DAC_SPI_MOSI : OUT std_logic; RFA_DAC_SPI_MISO : IN std_logic; RFB_DAC_SPI_MISO : IN std_logic; RFC_DAC_SPI_MISO : IN std_logic; RFD_DAC_SPI_MISO : IN std_logic; RFA_DAC_RESET : OUT std_logic; RFB_DAC_RESET : OUT std_logic; RFC_DAC_RESET : OUT std_logic; RFD_DAC_RESET : OUT std_logic; RFA_DAC_PLLLOCK : IN std_logic; RFB_DAC_PLLLOCK : IN std_logic; RFC_DAC_PLLLOCK : IN std_logic; RFD_DAC_PLLLOCK : IN std_logic; usr_RFA_TxEn : in std_logic; usr_RFB_TxEn : in std_logic; usr_RFC_TxEn : in std_logic; usr_RFD_TxEn : in std_logic; usr_RFA_RxEn : in std_logic; usr_RFB_RxEn : in std_logic; usr_RFC_RxEn : in std_logic; usr_RFD_RxEn : in std_logic; usr_RFA_RxHP : in std_logic; usr_RFB_RxHP : in std_logic; usr_RFC_RxHP : in std_logic; usr_RFD_RxHP : in std_logic; usr_RFA_SHDN : in std_logic; usr_RFB_SHDN : in std_logic; usr_RFC_SHDN : in std_logic; usr_RFD_SHDN : in std_logic; usr_RFA_RxGainRF : in std_logic_vector(0 to 1); usr_RFB_RxGainRF : in std_logic_vector(0 to 1); usr_RFC_RxGainRF : in std_logic_vector(0 to 1); usr_RFD_RxGainRF : in std_logic_vector(0 to 1); usr_RFA_RxGainBB : in std_logic_vector(0 to 4); usr_RFB_RxGainBB : in std_logic_vector(0 to 4); usr_RFC_RxGainBB : in std_logic_vector(0 to 4); usr_RFD_RxGainBB : in std_logic_vector(0 to 4); usr_RFA_TxGain : in std_logic_vector(0 to 5); usr_RFB_TxGain : in std_logic_vector(0 to 5); usr_RFC_TxGain : in std_logic_vector(0 to 5); usr_RFD_TxGain : in std_logic_vector(0 to 5); usr_SPI_ctrlSrc : in std_logic; usr_SPI_go : in std_logic; usr_SPI_active : out std_logic; usr_SPI_rfsel : in std_logic_vector(0 to 3); usr_SPI_regaddr : in std_logic_vector(0 to 3); usr_SPI_regdata : in std_logic_vector(0 to 13); usr_RFA_PHYStart : out std_logic; usr_RFB_PHYStart : out std_logic; usr_RFC_PHYStart : out std_logic; usr_RFD_PHYStart : out std_logic; usr_any_PHYStart : out std_logic; usr_RFA_statLED_Tx : out std_logic; usr_RFA_statLED_Rx : out std_logic; usr_RFA_statLED_NoLock : OUT std_logic; usr_RFB_statLED_Tx : out std_logic; usr_RFB_statLED_Rx : out std_logic; usr_RFB_statLED_NoLock : OUT std_logic; usr_RFC_statLED_Tx : out std_logic; usr_RFC_statLED_Rx : out std_logic; usr_RFC_statLED_NoLock : OUT std_logic; usr_RFD_statLED_Tx : out std_logic; usr_RFD_statLED_Rx : out std_logic; usr_RFD_statLED_NoLock : OUT std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1) -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of SPLB_Clk : signal is "CLK"; attribute SIGIS of SPLB_Rst : signal is "RST"; end entity radio_controller; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of radio_controller is ------------------------------------------ -- Array of base/high address pairs for each address range ------------------------------------------ constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address ); ------------------------------------------ -- Array of desired number of chip enables for each address range ------------------------------------------ constant USER_SLV_NUM_REG : integer := 64; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space ); ------------------------------------------ -- Ratio of bus clock to core clock (for use in dual clock systems) -- 1 = ratio is 1:1 -- 2 = ratio is 2:1 ------------------------------------------ constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; ------------------------------------------ -- Width of the slave data bus (32 only) ------------------------------------------ constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; ------------------------------------------ -- Index for CS/CE ------------------------------------------ constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; ------------------------------------------ -- IP Interconnect (IPIC) signal declarations ------------------------------------------ signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Reset : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; ------------------------------------------ -- Component declaration for verilog user logic ------------------------------------------ component user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_SLV_DWIDTH : integer := 32; C_NUM_REG : integer := 64 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ RFA_TxEn : out std_logic; RFB_TxEn : out std_logic; RFC_TxEn : out std_logic; RFD_TxEn : out std_logic; RFA_RxEn : out std_logic; RFB_RxEn : out std_logic; RFC_RxEn : out std_logic; RFD_RxEn : out std_logic; RFA_RxHP : out std_logic; RFB_RxHP : out std_logic; RFC_RxHP : out std_logic; RFD_RxHP : out std_logic; RFA_SHDN : out std_logic; RFB_SHDN : out std_logic; RFC_SHDN : out std_logic; RFD_SHDN : out std_logic; RFA_SPI_SCLK : out std_logic; RFB_SPI_SCLK : out std_logic; RFC_SPI_SCLK : out std_logic; RFD_SPI_SCLK : out std_logic; RFA_SPI_MOSI : out std_logic; RFB_SPI_MOSI : out std_logic; RFC_SPI_MOSI : out std_logic; RFD_SPI_MOSI : out std_logic; RFA_SPI_CSn : out std_logic; RFB_SPI_CSn : out std_logic; RFC_SPI_CSn : out std_logic; RFD_SPI_CSn : out std_logic; RFA_B : out std_logic_vector(0 to 6); RFB_B : out std_logic_vector(0 to 6); RFC_B : out std_logic_vector(0 to 6); RFD_B : out std_logic_vector(0 to 6); RFA_LD : in std_logic; RFB_LD : in std_logic; RFC_LD : in std_logic; RFD_LD : in std_logic; RFA_PAEn_24 : out std_logic; RFB_PAEn_24 : out std_logic; RFC_PAEn_24 : out std_logic; RFD_PAEn_24 : out std_logic; RFA_PAEn_5 : out std_logic; RFB_PAEn_5 : out std_logic; RFC_PAEn_5 : out std_logic; RFD_PAEn_5 : out std_logic; RFA_AntSw : out std_logic_vector(0 to 1); RFB_AntSw : out std_logic_vector(0 to 1); RFC_AntSw : out std_logic_vector(0 to 1); RFD_AntSw : out std_logic_vector(0 to 1); RFA_DIPSW : in std_logic_vector(0 to 3); RFB_DIPSW : in std_logic_vector(0 to 3); RFC_DIPSW : in std_logic_vector(0 to 3); RFD_DIPSW : in std_logic_vector(0 to 3); RFA_RX_ADC_DCS : OUT std_logic; RFB_RX_ADC_DCS : OUT std_logic; RFC_RX_ADC_DCS : OUT std_logic; RFD_RX_ADC_DCS : OUT std_logic; RFA_RX_ADC_DFS : OUT std_logic; RFB_RX_ADC_DFS : OUT std_logic; RFC_RX_ADC_DFS : OUT std_logic; RFD_RX_ADC_DFS : OUT std_logic; RFA_RX_ADC_PWDN : OUT std_logic; RFB_RX_ADC_PWDN : OUT std_logic; RFC_RX_ADC_PWDN : OUT std_logic; RFD_RX_ADC_PWDN : OUT std_logic; RFA_RSSI_ADC_CLAMP : OUT std_logic; RFB_RSSI_ADC_CLAMP : OUT std_logic; RFC_RSSI_ADC_CLAMP : OUT std_logic; RFD_RSSI_ADC_CLAMP : OUT std_logic; RFA_RSSI_ADC_HIZ : OUT std_logic; RFB_RSSI_ADC_HIZ : OUT std_logic; RFC_RSSI_ADC_HIZ : OUT std_logic; RFD_RSSI_ADC_HIZ : OUT std_logic; RFA_RSSI_ADC_SLEEP : OUT std_logic; RFB_RSSI_ADC_SLEEP : OUT std_logic; RFC_RSSI_ADC_SLEEP : OUT std_logic; RFD_RSSI_ADC_SLEEP : OUT std_logic; RFA_DAC_SPI_CSn : OUT std_logic; RFB_DAC_SPI_CSn : OUT std_logic; RFC_DAC_SPI_CSn : OUT std_logic; RFD_DAC_SPI_CSn : OUT std_logic; RFA_DAC_SPI_SCLK : OUT std_logic; RFB_DAC_SPI_SCLK : OUT std_logic; RFC_DAC_SPI_SCLK : OUT std_logic; RFD_DAC_SPI_SCLK : OUT std_logic; RFA_DAC_SPI_MOSI : OUT std_logic; RFB_DAC_SPI_MOSI : OUT std_logic; RFC_DAC_SPI_MOSI : OUT std_logic; RFD_DAC_SPI_MOSI : OUT std_logic; RFA_DAC_SPI_MISO : IN std_logic; RFB_DAC_SPI_MISO : IN std_logic; RFC_DAC_SPI_MISO : IN std_logic; RFD_DAC_SPI_MISO : IN std_logic; RFA_DAC_RESET : OUT std_logic; RFB_DAC_RESET : OUT std_logic; RFC_DAC_RESET : OUT std_logic; RFD_DAC_RESET : OUT std_logic; RFA_DAC_PLLLOCK : IN std_logic; RFB_DAC_PLLLOCK : IN std_logic; RFC_DAC_PLLLOCK : IN std_logic; RFD_DAC_PLLLOCK : IN std_logic; usr_RFA_TxEn : in std_logic; usr_RFB_TxEn : in std_logic; usr_RFC_TxEn : in std_logic; usr_RFD_TxEn : in std_logic; usr_RFA_RxEn : in std_logic; usr_RFB_RxEn : in std_logic; usr_RFC_RxEn : in std_logic; usr_RFD_RxEn : in std_logic; usr_RFA_RxHP : in std_logic; usr_RFB_RxHP : in std_logic; usr_RFC_RxHP : in std_logic; usr_RFD_RxHP : in std_logic; usr_RFA_SHDN : in std_logic; usr_RFB_SHDN : in std_logic; usr_RFC_SHDN : in std_logic; usr_RFD_SHDN : in std_logic; usr_RFA_RxGainRF : in std_logic_vector(0 to 1); usr_RFB_RxGainRF : in std_logic_vector(0 to 1); usr_RFC_RxGainRF : in std_logic_vector(0 to 1); usr_RFD_RxGainRF : in std_logic_vector(0 to 1); usr_RFA_RxGainBB : in std_logic_vector(0 to 4); usr_RFB_RxGainBB : in std_logic_vector(0 to 4); usr_RFC_RxGainBB : in std_logic_vector(0 to 4); usr_RFD_RxGainBB : in std_logic_vector(0 to 4); usr_RFA_TxGain : in std_logic_vector(0 to 5); usr_RFB_TxGain : in std_logic_vector(0 to 5); usr_RFC_TxGain : in std_logic_vector(0 to 5); usr_RFD_TxGain : in std_logic_vector(0 to 5); usr_SPI_ctrlSrc : in std_logic; usr_SPI_go : in std_logic; usr_SPI_active : out std_logic; usr_SPI_rfsel : in std_logic_vector(0 to 3); usr_SPI_regaddr : in std_logic_vector(0 to 3); usr_SPI_regdata : in std_logic_vector(0 to 13); usr_RFA_PHYStart : out std_logic; usr_RFB_PHYStart : out std_logic; usr_RFC_PHYStart : out std_logic; usr_RFD_PHYStart : out std_logic; usr_any_PHYStart : out std_logic; usr_RFA_statLED_Tx : out std_logic; usr_RFA_statLED_Rx : out std_logic; usr_RFA_statLED_NoLock : OUT std_logic; usr_RFB_statLED_Tx : out std_logic; usr_RFB_statLED_Rx : out std_logic; usr_RFB_statLED_NoLock : OUT std_logic; usr_RFC_statLED_Tx : out std_logic; usr_RFC_statLED_Rx : out std_logic; usr_RFC_statLED_NoLock : OUT std_logic; usr_RFD_statLED_Tx : out std_logic; usr_RFD_statLED_Rx : out std_logic; usr_RFD_statLED_NoLock : OUT std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1); IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end component user_logic; begin ------------------------------------------ -- instantiate plbv46_slave_single ------------------------------------------ PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single generic map ( C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_SPLB_P2P => C_SPLB_P2P, C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, C_SPLB_AWIDTH => C_SPLB_AWIDTH, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, C_FAMILY => C_FAMILY ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Reset => ipif_Bus2IP_Reset, IP2Bus_Data => ipif_IP2Bus_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE ); ------------------------------------------ -- instantiate User Logic ------------------------------------------ USER_LOGIC_I : component user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- --USER generics mapped here -- MAP USER GENERICS ABOVE THIS LINE --------------- C_SLV_DWIDTH => USER_SLV_DWIDTH, C_NUM_REG => USER_NUM_REG ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ RFA_TxEn => RFA_TxEn, RFB_TxEn => RFB_TxEn, RFC_TxEn => RFC_TxEn, RFD_TxEn => RFD_TxEn, RFA_RxEn => RFA_RxEn, RFB_RxEn => RFB_RxEn, RFC_RxEn => RFC_RxEn, RFD_RxEn => RFD_RxEn, RFA_RxHP => RFA_RxHP, RFB_RxHP => RFB_RxHP, RFC_RxHP => RFC_RxHP, RFD_RxHP => RFD_RxHP, RFA_SHDN => RFA_SHDN, RFB_SHDN => RFB_SHDN, RFC_SHDN => RFC_SHDN, RFD_SHDN => RFD_SHDN, RFA_SPI_SCLK => RFA_SPI_SCLK, RFB_SPI_SCLK => RFB_SPI_SCLK, RFC_SPI_SCLK => RFC_SPI_SCLK, RFD_SPI_SCLK => RFD_SPI_SCLK, RFA_SPI_MOSI => RFA_SPI_MOSI, RFB_SPI_MOSI => RFB_SPI_MOSI, RFC_SPI_MOSI => RFC_SPI_MOSI, RFD_SPI_MOSI => RFD_SPI_MOSI, RFA_SPI_CSn => RFA_SPI_CSn, RFB_SPI_CSn => RFB_SPI_CSn, RFC_SPI_CSn => RFC_SPI_CSn, RFD_SPI_CSn => RFD_SPI_CSn, RFA_B => RFA_B, RFB_B => RFB_B, RFC_B => RFC_B, RFD_B => RFD_B, RFA_LD => RFA_LD, RFB_LD => RFB_LD, RFC_LD => RFC_LD, RFD_LD => RFD_LD, RFA_PAEn_24 => RFA_PAEn_24, RFB_PAEn_24 => RFB_PAEn_24, RFC_PAEn_24 => RFC_PAEn_24, RFD_PAEn_24 => RFD_PAEn_24, RFA_PAEn_5 => RFA_PAEn_5, RFB_PAEn_5 => RFB_PAEn_5, RFC_PAEn_5 => RFC_PAEn_5, RFD_PAEn_5 => RFD_PAEn_5, RFA_AntSw => RFA_AntSw, RFB_AntSw => RFB_AntSw, RFC_AntSw => RFC_AntSw, RFD_AntSw => RFD_AntSw, RFA_DIPSW => RFA_DIPSW, RFB_DIPSW => RFB_DIPSW, RFC_DIPSW => RFC_DIPSW, RFD_DIPSW => RFD_DIPSW, RFA_RX_ADC_DCS => RFA_RX_ADC_DCS, RFB_RX_ADC_DCS => RFB_RX_ADC_DCS, RFC_RX_ADC_DCS => RFC_RX_ADC_DCS, RFD_RX_ADC_DCS => RFD_RX_ADC_DCS, RFA_RX_ADC_DFS => RFA_RX_ADC_DFS, RFB_RX_ADC_DFS => RFB_RX_ADC_DFS, RFC_RX_ADC_DFS => RFC_RX_ADC_DFS, RFD_RX_ADC_DFS => RFD_RX_ADC_DFS, RFA_RX_ADC_PWDN => RFA_RX_ADC_PWDN, RFB_RX_ADC_PWDN => RFB_RX_ADC_PWDN, RFC_RX_ADC_PWDN => RFC_RX_ADC_PWDN, RFD_RX_ADC_PWDN => RFD_RX_ADC_PWDN, RFA_RSSI_ADC_CLAMP => RFA_RSSI_ADC_CLAMP, RFB_RSSI_ADC_CLAMP => RFB_RSSI_ADC_CLAMP, RFC_RSSI_ADC_CLAMP => RFC_RSSI_ADC_CLAMP, RFD_RSSI_ADC_CLAMP => RFD_RSSI_ADC_CLAMP, RFA_RSSI_ADC_HIZ => RFA_RSSI_ADC_HIZ, RFB_RSSI_ADC_HIZ => RFB_RSSI_ADC_HIZ, RFC_RSSI_ADC_HIZ => RFC_RSSI_ADC_HIZ, RFD_RSSI_ADC_HIZ => RFD_RSSI_ADC_HIZ, RFA_RSSI_ADC_SLEEP => RFA_RSSI_ADC_SLEEP, RFB_RSSI_ADC_SLEEP => RFB_RSSI_ADC_SLEEP, RFC_RSSI_ADC_SLEEP => RFC_RSSI_ADC_SLEEP, RFD_RSSI_ADC_SLEEP => RFD_RSSI_ADC_SLEEP, RFA_DAC_SPI_CSn => RFA_DAC_SPI_CSn, RFB_DAC_SPI_CSn => RFB_DAC_SPI_CSn, RFC_DAC_SPI_CSn => RFC_DAC_SPI_CSn, RFD_DAC_SPI_CSn => RFD_DAC_SPI_CSn, RFA_DAC_SPI_SCLK => RFA_DAC_SPI_SCLK, RFB_DAC_SPI_SCLK => RFB_DAC_SPI_SCLK, RFC_DAC_SPI_SCLK => RFC_DAC_SPI_SCLK, RFD_DAC_SPI_SCLK => RFD_DAC_SPI_SCLK, RFA_DAC_SPI_MOSI => RFA_DAC_SPI_MOSI, RFB_DAC_SPI_MOSI => RFB_DAC_SPI_MOSI, RFC_DAC_SPI_MOSI => RFC_DAC_SPI_MOSI, RFD_DAC_SPI_MOSI => RFD_DAC_SPI_MOSI, RFA_DAC_SPI_MISO => RFA_DAC_SPI_MISO, RFB_DAC_SPI_MISO => RFB_DAC_SPI_MISO, RFC_DAC_SPI_MISO => RFC_DAC_SPI_MISO, RFD_DAC_SPI_MISO => RFD_DAC_SPI_MISO, RFA_DAC_RESET => RFA_DAC_RESET, RFB_DAC_RESET => RFB_DAC_RESET, RFC_DAC_RESET => RFC_DAC_RESET, RFD_DAC_RESET => RFD_DAC_RESET, RFA_DAC_PLLLOCK => RFA_DAC_PLLLOCK, RFB_DAC_PLLLOCK => RFB_DAC_PLLLOCK, RFC_DAC_PLLLOCK => RFC_DAC_PLLLOCK, RFD_DAC_PLLLOCK => RFD_DAC_PLLLOCK, usr_RFA_TxEn => usr_RFA_TxEn, usr_RFB_TxEn => usr_RFB_TxEn, usr_RFC_TxEn => usr_RFC_TxEn, usr_RFD_TxEn => usr_RFD_TxEn, usr_RFA_RxEn => usr_RFA_RxEn, usr_RFB_RxEn => usr_RFB_RxEn, usr_RFC_RxEn => usr_RFC_RxEn, usr_RFD_RxEn => usr_RFD_RxEn, usr_RFA_RxHP => usr_RFA_RxHP, usr_RFB_RxHP => usr_RFB_RxHP, usr_RFC_RxHP => usr_RFC_RxHP, usr_RFD_RxHP => usr_RFD_RxHP, usr_RFA_SHDN => usr_RFA_SHDN, usr_RFB_SHDN => usr_RFB_SHDN, usr_RFC_SHDN => usr_RFC_SHDN, usr_RFD_SHDN => usr_RFD_SHDN, usr_RFA_RxGainRF => usr_RFA_RxGainRF, usr_RFB_RxGainRF => usr_RFB_RxGainRF, usr_RFC_RxGainRF => usr_RFC_RxGainRF, usr_RFD_RxGainRF => usr_RFD_RxGainRF, usr_RFA_RxGainBB => usr_RFA_RxGainBB, usr_RFB_RxGainBB => usr_RFB_RxGainBB, usr_RFC_RxGainBB => usr_RFC_RxGainBB, usr_RFD_RxGainBB => usr_RFD_RxGainBB, usr_RFA_TxGain => usr_RFA_TxGain, usr_RFB_TxGain => usr_RFB_TxGain, usr_RFC_TxGain => usr_RFC_TxGain, usr_RFD_TxGain => usr_RFD_TxGain, usr_SPI_ctrlSrc => usr_SPI_ctrlSrc, usr_SPI_go => usr_SPI_go, usr_SPI_active => usr_SPI_active, usr_SPI_rfsel => usr_SPI_rfsel, usr_SPI_regaddr => usr_SPI_regaddr, usr_SPI_regdata => usr_SPI_regdata, usr_RFA_PHYStart => usr_RFA_PHYStart, usr_RFB_PHYStart => usr_RFB_PHYStart, usr_RFC_PHYStart => usr_RFC_PHYStart, usr_RFD_PHYStart => usr_RFD_PHYStart, usr_any_PHYStart => usr_any_PHYStart, usr_RFA_statLED_Tx => usr_RFA_statLED_Tx, usr_RFA_statLED_Rx => usr_RFA_statLED_Rx, usr_RFA_statLED_NoLock => usr_RFA_statLED_NoLock, usr_RFB_statLED_Tx => usr_RFB_statLED_Tx, usr_RFB_statLED_Rx => usr_RFB_statLED_Rx, usr_RFB_statLED_NoLock => usr_RFB_statLED_NoLock, usr_RFC_statLED_Tx => usr_RFC_statLED_Tx, usr_RFC_statLED_Rx => usr_RFC_statLED_Rx, usr_RFC_statLED_NoLock => usr_RFC_statLED_NoLock, usr_RFD_statLED_Tx => usr_RFD_statLED_Tx, usr_RFD_statLED_Rx => usr_RFD_statLED_Rx, usr_RFD_statLED_NoLock => usr_RFD_statLED_NoLock, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Reset => ipif_Bus2IP_Reset, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error ); ------------------------------------------ -- connect internal signals ------------------------------------------ ipif_IP2Bus_Data <= user_IP2Bus_Data; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); end IMP;