[6301] | 1 | //---------------------------------------------------------------------------- |
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| 2 | // user_logic.v - module |
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| 3 | //---------------------------------------------------------------------------- |
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| 4 | // |
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| 5 | // *************************************************************************** |
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| 6 | // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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| 7 | // ** ** |
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| 8 | // ** Xilinx, Inc. ** |
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| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
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| 22 | // ** ** |
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| 23 | // *************************************************************************** |
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| 24 | // |
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| 25 | //---------------------------------------------------------------------------- |
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| 26 | // Filename: user_logic.v |
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| 27 | // Version: 1.00.a |
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| 28 | // Description: User logic module. |
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| 29 | // Date: Tue Oct 30 09:50:47 2018 (by Create and Import Peripheral Wizard) |
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| 30 | // Verilog Standard: Verilog-2001 |
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| 31 | //---------------------------------------------------------------------------- |
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| 32 | // Naming Conventions: |
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| 33 | // active low signals: "*_n" |
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| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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| 35 | // reset signals: "rst", "rst_n" |
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| 36 | // generics: "C_*" |
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| 37 | // user defined types: "*_TYPE" |
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| 38 | // state machine next state: "*_ns" |
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| 39 | // state machine current state: "*_cs" |
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| 40 | // combinatorial signals: "*_com" |
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| 41 | // pipelined or register delay signals: "*_d#" |
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| 42 | // counter signals: "*cnt*" |
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| 43 | // clock enable signals: "*_ce" |
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| 44 | // internal version of output port: "*_i" |
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| 45 | // device pins: "*_pin" |
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| 46 | // ports: "- Names begin with Uppercase" |
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| 47 | // processes: "*_PROCESS" |
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| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 49 | //---------------------------------------------------------------------------- |
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| 50 | |
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| 51 | `uselib lib=unisims_ver |
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| 52 | `uselib lib=proc_common_v3_00_a |
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| 53 | |
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| 54 | module user_logic |
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| 55 | ( |
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| 56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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[6303] | 57 | intrA_out, |
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| 58 | intrB_out, |
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[6301] | 59 | // --USER ports added here |
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| 60 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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| 61 | |
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| 62 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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| 63 | // -- Bus protocol ports, do not add to or delete |
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| 64 | Bus2IP_Clk, // Bus to IP clock |
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| 65 | Bus2IP_Resetn, // Bus to IP reset |
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| 66 | Bus2IP_Data, // Bus to IP data bus |
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| 67 | Bus2IP_BE, // Bus to IP byte enables |
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| 68 | Bus2IP_RdCE, // Bus to IP read chip enable |
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| 69 | Bus2IP_WrCE, // Bus to IP write chip enable |
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| 70 | IP2Bus_Data, // IP to Bus data bus |
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| 71 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
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| 72 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
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| 73 | IP2Bus_Error // IP to Bus error response |
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| 74 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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| 75 | ); // user_logic |
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| 76 | |
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| 77 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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| 78 | // --USER parameters added here |
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| 79 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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| 80 | |
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| 81 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 82 | // -- Bus protocol parameters, do not add to or delete |
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| 83 | parameter C_NUM_REG = 16; |
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| 84 | parameter C_SLV_DWIDTH = 32; |
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| 85 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 86 | |
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| 87 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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| 88 | |
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| 89 | output reg intrA_out = 0; |
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| 90 | output reg intrB_out = 0; |
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| 91 | |
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| 92 | // --USER ports added here |
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| 93 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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| 94 | |
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| 95 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 96 | // -- Bus protocol ports, do not add to or delete |
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| 97 | input Bus2IP_Clk; |
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| 98 | input Bus2IP_Resetn; |
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| 99 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; |
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| 100 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; |
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| 101 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE; |
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| 102 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE; |
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| 103 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; |
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| 104 | output IP2Bus_RdAck; |
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| 105 | output IP2Bus_WrAck; |
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| 106 | output IP2Bus_Error; |
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| 107 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 108 | |
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| 109 | //---------------------------------------------------------------------------- |
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| 110 | // Implementation |
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| 111 | //---------------------------------------------------------------------------- |
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| 112 | |
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| 113 | // --USER nets declarations added here, as needed for user logic |
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| 114 | |
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| 115 | wire [31:0] sw_state0; |
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| 116 | wire [31:0] sw_state1; |
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| 117 | |
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| 118 | wire [31:0] sw_state0_maskA; |
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| 119 | wire [31:0] sw_state1_maskA; |
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| 120 | |
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[6303] | 121 | wire [31:0] sw_state0_maskB; |
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[6301] | 122 | wire [31:0] sw_state1_maskB; |
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| 123 | |
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| 124 | wire intrA_en, intrB_en; |
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| 125 | |
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| 126 | wire [31:0] reg0_rd; |
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| 127 | |
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| 128 | // Nets for user logic slave model s/w accessible register example |
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| 129 | reg [C_SLV_DWIDTH-1 : 0] slv_reg0 = 0; |
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| 130 | reg [C_SLV_DWIDTH-1 : 0] slv_reg1 = 0; |
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| 131 | reg [C_SLV_DWIDTH-1 : 0] slv_reg2 = 0; |
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| 132 | reg [C_SLV_DWIDTH-1 : 0] slv_reg3 = 0; |
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| 133 | reg [C_SLV_DWIDTH-1 : 0] slv_reg4 = 0; |
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| 134 | reg [C_SLV_DWIDTH-1 : 0] slv_reg5 = 0; |
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| 135 | reg [C_SLV_DWIDTH-1 : 0] slv_reg6 = 0; |
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| 136 | reg [C_SLV_DWIDTH-1 : 0] slv_reg7 = 0; |
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| 137 | reg [C_SLV_DWIDTH-1 : 0] slv_reg8 = 0; |
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| 138 | reg [C_SLV_DWIDTH-1 : 0] slv_reg9 = 0; |
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| 139 | reg [C_SLV_DWIDTH-1 : 0] slv_reg10 = 0; |
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| 140 | reg [C_SLV_DWIDTH-1 : 0] slv_reg11 = 0; |
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| 141 | reg [C_SLV_DWIDTH-1 : 0] slv_reg12 = 0; |
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| 142 | reg [C_SLV_DWIDTH-1 : 0] slv_reg13 = 0; |
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| 143 | reg [C_SLV_DWIDTH-1 : 0] slv_reg14 = 0; |
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| 144 | reg [C_SLV_DWIDTH-1 : 0] slv_reg15 = 0; |
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| 145 | wire [15 : 0] slv_reg_write_sel; |
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| 146 | wire [15 : 0] slv_reg_read_sel; |
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| 147 | reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data = 0; |
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| 148 | wire slv_read_ack; |
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| 149 | wire slv_write_ack; |
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| 150 | integer byte_index, bit_index; |
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| 151 | |
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| 152 | // USER logic implementation added here |
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| 153 | |
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| 154 | /* Address map: |
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| 155 | HDL is coded [MSB:LSB] = [31:0], per Xilinx's convention for AXI peripherals |
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| 156 | regX[31] maps to 0x80000000 in C driver |
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| 157 | regX[ 0] maps to 0x00000001 in C driver |
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| 158 | |
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| 159 | 0: RO/RW: Control/status register |
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| 160 | [ 0] = Enable (active high) for intrA output |
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| 161 | [ 1] = Enable (active high) for intrB output |
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| 162 | [ 28] = (RO) current intrA_out value |
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| 163 | [ 29] = (RO) current intrB_out value |
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| 164 | |
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| 165 | 1: RW: Software state register 0 |
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| 166 | 2: RW: Software state register 1 |
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| 167 | |
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| 168 | 3: RW: Bitmask for sw state reg 0 asserting intrA |
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| 169 | 4: RW: Bitmask for sw state reg 1 asserting intrA |
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| 170 | 5: RW: Bitmask for sw state reg 0 asserting intrB |
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| 171 | 6: RW: Bitmask for sw state reg 1 asserting intrB |
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| 172 | |
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| 173 | */ |
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| 174 | |
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| 175 | assign reg0_rd[31:0] = {2'b0, intrB_out, intrA_out, 26'b0, intrB_en, intrA_en}; |
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| 176 | |
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| 177 | assign intrA_en = slv_reg0[0]; |
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| 178 | assign intrB_en = slv_reg0[1]; |
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| 179 | |
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| 180 | assign sw_state0[31:0] = slv_reg1; |
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| 181 | assign sw_state1[31:0] = slv_reg2; |
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| 182 | |
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| 183 | assign sw_state0_maskA[31:0] = slv_reg3; |
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| 184 | assign sw_state1_maskA[31:0] = slv_reg4; |
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| 185 | assign sw_state0_maskB[31:0] = slv_reg5; |
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| 186 | assign sw_state1_maskB[31:0] = slv_reg6; |
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| 187 | |
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| 188 | reg sw_intA = 0; |
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| 189 | reg sw_intB = 0; |
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| 190 | |
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| 191 | always @(posedge Bus2IP_Clk) |
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| 192 | begin |
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| 193 | sw_intA <= (|(sw_state0 & sw_state0_maskA)) | (|(sw_state1 & sw_state1_maskA)); |
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[6304] | 194 | sw_intB <= (|(sw_state0 & sw_state0_maskB)) | (|(sw_state1 & sw_state1_maskB)); |
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[6301] | 195 | |
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| 196 | intrA_out <= sw_intA; |
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| 197 | intrB_out <= sw_intB; |
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| 198 | end |
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| 199 | |
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| 200 | // ------------------------------------------------------ |
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| 201 | // Example code to read/write user logic slave model s/w accessible registers |
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| 202 | // |
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| 203 | // Note: |
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| 204 | // The example code presented here is to show you one way of reading/writing |
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| 205 | // software accessible registers implemented in the user logic slave model. |
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| 206 | // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond |
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| 207 | // to one software accessible register by the top level template. For example, |
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| 208 | // if you have four 32 bit software accessible registers in the user logic, |
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| 209 | // you are basically operating on the following memory mapped registers: |
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| 210 | // |
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| 211 | // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register |
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| 212 | // "1000" C_BASEADDR + 0x0 |
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| 213 | // "0100" C_BASEADDR + 0x4 |
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| 214 | // "0010" C_BASEADDR + 0x8 |
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| 215 | // "0001" C_BASEADDR + 0xC |
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| 216 | // |
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| 217 | // ------------------------------------------------------ |
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| 218 | |
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| 219 | assign |
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| 220 | slv_reg_write_sel = Bus2IP_WrCE[15:0], |
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| 221 | slv_reg_read_sel = Bus2IP_RdCE[15:0], |
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| 222 | slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15], |
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| 223 | slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15]; |
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| 224 | |
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| 225 | // implement slave model register(s) |
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| 226 | always @( posedge Bus2IP_Clk ) |
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| 227 | begin |
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| 228 | |
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| 229 | if ( Bus2IP_Resetn == 1'b0 ) |
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| 230 | begin |
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| 231 | slv_reg0 <= 0; |
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| 232 | slv_reg1 <= 0; |
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| 233 | slv_reg2 <= 0; |
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| 234 | slv_reg3 <= 0; |
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| 235 | slv_reg4 <= 0; |
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| 236 | slv_reg5 <= 0; |
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| 237 | slv_reg6 <= 0; |
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| 238 | slv_reg7 <= 0; |
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| 239 | slv_reg8 <= 0; |
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| 240 | slv_reg9 <= 0; |
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| 241 | slv_reg10 <= 0; |
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| 242 | slv_reg11 <= 0; |
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| 243 | slv_reg12 <= 0; |
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| 244 | slv_reg13 <= 0; |
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| 245 | slv_reg14 <= 0; |
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| 246 | slv_reg15 <= 0; |
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| 247 | end |
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| 248 | else |
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| 249 | case ( slv_reg_write_sel ) |
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| 250 | 16'b1000000000000000 : |
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| 251 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 252 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 253 | slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 254 | 16'b0100000000000000 : |
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| 255 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 256 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 257 | slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 258 | 16'b0010000000000000 : |
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| 259 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 260 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 261 | slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 262 | 16'b0001000000000000 : |
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| 263 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 264 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 265 | slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 266 | 16'b0000100000000000 : |
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| 267 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 268 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 269 | slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 270 | 16'b0000010000000000 : |
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| 271 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 272 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 273 | slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 274 | 16'b0000001000000000 : |
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| 275 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 276 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 277 | slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 278 | 16'b0000000100000000 : |
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| 279 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 280 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 281 | slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 282 | 16'b0000000010000000 : |
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| 283 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 284 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 285 | slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 286 | 16'b0000000001000000 : |
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| 287 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 288 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 289 | slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 290 | 16'b0000000000100000 : |
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| 291 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 292 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 293 | slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 294 | 16'b0000000000010000 : |
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| 295 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 296 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 297 | slv_reg11[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 298 | 16'b0000000000001000 : |
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| 299 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 300 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 301 | slv_reg12[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 302 | 16'b0000000000000100 : |
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| 303 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 304 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 305 | slv_reg13[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 306 | 16'b0000000000000010 : |
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| 307 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 308 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 309 | slv_reg14[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 310 | 16'b0000000000000001 : |
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| 311 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 312 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 313 | slv_reg15[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 314 | default : begin |
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| 315 | slv_reg0 <= slv_reg0; |
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| 316 | slv_reg1 <= slv_reg1; |
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| 317 | slv_reg2 <= slv_reg2; |
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| 318 | slv_reg3 <= slv_reg3; |
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| 319 | slv_reg4 <= slv_reg4; |
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| 320 | slv_reg5 <= slv_reg5; |
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| 321 | slv_reg6 <= slv_reg6; |
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| 322 | slv_reg7 <= slv_reg7; |
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| 323 | slv_reg8 <= slv_reg8; |
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| 324 | slv_reg9 <= slv_reg9; |
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| 325 | slv_reg10 <= slv_reg10; |
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| 326 | slv_reg11 <= slv_reg11; |
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| 327 | slv_reg12 <= slv_reg12; |
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| 328 | slv_reg13 <= slv_reg13; |
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| 329 | slv_reg14 <= slv_reg14; |
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| 330 | slv_reg15 <= slv_reg15; |
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| 331 | end |
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| 332 | endcase |
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| 333 | |
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| 334 | end // SLAVE_REG_WRITE_PROC |
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| 335 | |
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| 336 | // implement slave model register read mux |
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| 337 | always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 ) |
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| 338 | begin |
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| 339 | |
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| 340 | case ( slv_reg_read_sel ) |
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| 341 | 16'b1000000000000000 : slv_ip2bus_data <= reg0_rd; |
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| 342 | 16'b0100000000000000 : slv_ip2bus_data <= slv_reg1; |
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| 343 | 16'b0010000000000000 : slv_ip2bus_data <= slv_reg2; |
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| 344 | 16'b0001000000000000 : slv_ip2bus_data <= slv_reg3; |
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| 345 | 16'b0000100000000000 : slv_ip2bus_data <= slv_reg4; |
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| 346 | 16'b0000010000000000 : slv_ip2bus_data <= slv_reg5; |
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| 347 | 16'b0000001000000000 : slv_ip2bus_data <= slv_reg6; |
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| 348 | 16'b0000000100000000 : slv_ip2bus_data <= slv_reg7; |
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| 349 | 16'b0000000010000000 : slv_ip2bus_data <= slv_reg8; |
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| 350 | 16'b0000000001000000 : slv_ip2bus_data <= slv_reg9; |
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| 351 | 16'b0000000000100000 : slv_ip2bus_data <= slv_reg10; |
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| 352 | 16'b0000000000010000 : slv_ip2bus_data <= slv_reg11; |
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| 353 | 16'b0000000000001000 : slv_ip2bus_data <= slv_reg12; |
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| 354 | 16'b0000000000000100 : slv_ip2bus_data <= slv_reg13; |
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| 355 | 16'b0000000000000010 : slv_ip2bus_data <= slv_reg14; |
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| 356 | 16'b0000000000000001 : slv_ip2bus_data <= slv_reg15; |
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| 357 | default : slv_ip2bus_data <= 0; |
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| 358 | endcase |
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| 359 | |
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| 360 | end // SLAVE_REG_READ_PROC |
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| 361 | |
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| 362 | // ------------------------------------------------------------ |
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| 363 | // Example code to drive IP to Bus signals |
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| 364 | // ------------------------------------------------------------ |
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| 365 | |
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| 366 | assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; |
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| 367 | assign IP2Bus_WrAck = slv_write_ack; |
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| 368 | assign IP2Bus_RdAck = slv_read_ack; |
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| 369 | assign IP2Bus_Error = 0; |
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| 370 | |
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| 371 | endmodule |
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