[1927] | 1 | //---------------------------------------------------------------------------- |
---|
| 2 | // user_logic.v - module |
---|
| 3 | //---------------------------------------------------------------------------- |
---|
| 4 | // |
---|
| 5 | // *************************************************************************** |
---|
| 6 | // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
---|
| 7 | // ** ** |
---|
| 8 | // ** Xilinx, Inc. ** |
---|
| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
---|
| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
---|
| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
---|
| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
---|
| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
---|
| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
---|
| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
---|
| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
---|
| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
---|
| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
---|
| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
---|
| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
---|
| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
---|
| 22 | // ** ** |
---|
| 23 | // *************************************************************************** |
---|
| 24 | // |
---|
| 25 | //---------------------------------------------------------------------------- |
---|
| 26 | // Filename: user_logic.v |
---|
| 27 | // Version: 3.01.a |
---|
| 28 | // Description: User logic module. |
---|
| 29 | // Date: Tue Feb 26 12:57:13 2013 (by Create and Import Peripheral Wizard) |
---|
| 30 | // Verilog Standard: Verilog-2001 |
---|
| 31 | //---------------------------------------------------------------------------- |
---|
| 32 | // Naming Conventions: |
---|
| 33 | // active low signals: "*_n" |
---|
| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
---|
| 35 | // reset signals: "rst", "rst_n" |
---|
| 36 | // generics: "C_*" |
---|
| 37 | // user defined types: "*_TYPE" |
---|
| 38 | // state machine next state: "*_ns" |
---|
| 39 | // state machine current state: "*_cs" |
---|
| 40 | // combinatorial signals: "*_com" |
---|
| 41 | // pipelined or register delay signals: "*_d#" |
---|
| 42 | // counter signals: "*cnt*" |
---|
| 43 | // clock enable signals: "*_ce" |
---|
| 44 | // internal version of output port: "*_i" |
---|
| 45 | // device pins: "*_pin" |
---|
| 46 | // ports: "- Names begin with Uppercase" |
---|
| 47 | // processes: "*_PROCESS" |
---|
| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
---|
| 49 | //---------------------------------------------------------------------------- |
---|
| 50 | |
---|
| 51 | `uselib lib=unisims_ver |
---|
| 52 | `uselib lib=proc_common_v3_00_a |
---|
| 53 | |
---|
| 54 | module user_logic |
---|
| 55 | ( |
---|
| 56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
---|
| 57 | RFA_AD_spi_sclk, |
---|
| 58 | RFA_AD_spi_cs_n, |
---|
| 59 | RFA_AD_spi_sdio, |
---|
| 60 | RFA_AD_reset_n, |
---|
| 61 | |
---|
| 62 | RFB_AD_spi_sclk, |
---|
| 63 | RFB_AD_spi_cs_n, |
---|
| 64 | RFB_AD_spi_sdio, |
---|
| 65 | RFB_AD_reset_n, |
---|
| 66 | |
---|
| 67 | RFC_AD_spi_sclk, |
---|
| 68 | RFC_AD_spi_cs_n, |
---|
| 69 | RFC_AD_spi_sdio, |
---|
| 70 | RFC_AD_reset_n, |
---|
| 71 | |
---|
| 72 | RFD_AD_spi_sclk, |
---|
| 73 | RFD_AD_spi_cs_n, |
---|
| 74 | RFD_AD_spi_sdio, |
---|
| 75 | RFD_AD_reset_n, |
---|
| 76 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
---|
| 77 | |
---|
| 78 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
---|
| 79 | // -- Bus protocol ports, do not add to or delete |
---|
| 80 | Bus2IP_Clk, // Bus to IP clock |
---|
| 81 | Bus2IP_Resetn, // Bus to IP reset |
---|
| 82 | Bus2IP_Data, // Bus to IP data bus |
---|
| 83 | Bus2IP_BE, // Bus to IP byte enables |
---|
| 84 | Bus2IP_RdCE, // Bus to IP read chip enable |
---|
| 85 | Bus2IP_WrCE, // Bus to IP write chip enable |
---|
| 86 | IP2Bus_Data, // IP to Bus data bus |
---|
| 87 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
---|
| 88 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
---|
| 89 | IP2Bus_Error // IP to Bus error response |
---|
| 90 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
---|
| 91 | ); // user_logic |
---|
| 92 | |
---|
| 93 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
---|
| 94 | // --USER parameters added here |
---|
| 95 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
---|
| 96 | |
---|
| 97 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
---|
| 98 | // -- Bus protocol parameters, do not add to or delete |
---|
| 99 | parameter C_NUM_REG = 16; |
---|
| 100 | parameter C_SLV_DWIDTH = 32; |
---|
| 101 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
---|
| 102 | |
---|
| 103 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
---|
| 104 | output RFA_AD_spi_sclk; |
---|
| 105 | output RFA_AD_spi_cs_n; |
---|
| 106 | inout RFA_AD_spi_sdio; |
---|
| 107 | output RFA_AD_reset_n; |
---|
| 108 | |
---|
| 109 | output RFB_AD_spi_sclk; |
---|
| 110 | output RFB_AD_spi_cs_n; |
---|
| 111 | inout RFB_AD_spi_sdio; |
---|
| 112 | output RFB_AD_reset_n; |
---|
| 113 | |
---|
| 114 | output RFC_AD_spi_sclk; |
---|
| 115 | output RFC_AD_spi_cs_n; |
---|
| 116 | inout RFC_AD_spi_sdio; |
---|
| 117 | output RFC_AD_reset_n; |
---|
| 118 | |
---|
| 119 | output RFD_AD_spi_sclk; |
---|
| 120 | output RFD_AD_spi_cs_n; |
---|
| 121 | inout RFD_AD_spi_sdio; |
---|
| 122 | output RFD_AD_reset_n; |
---|
| 123 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
---|
| 124 | |
---|
| 125 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
---|
| 126 | // -- Bus protocol ports, do not add to or delete |
---|
| 127 | input Bus2IP_Clk; |
---|
| 128 | input Bus2IP_Resetn; |
---|
| 129 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; |
---|
| 130 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; |
---|
| 131 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE; |
---|
| 132 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE; |
---|
| 133 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; |
---|
| 134 | output IP2Bus_RdAck; |
---|
| 135 | output IP2Bus_WrAck; |
---|
| 136 | output IP2Bus_Error; |
---|
| 137 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
---|
| 138 | |
---|
| 139 | //---------------------------------------------------------------------------- |
---|
| 140 | // Implementation |
---|
| 141 | //---------------------------------------------------------------------------- |
---|
| 142 | |
---|
| 143 | // --USER nets declarations added here, as needed for user logic |
---|
| 144 | |
---|
| 145 | // Nets for user logic slave model s/w accessible register example |
---|
| 146 | reg [C_SLV_DWIDTH-1 : 0] slv_reg0; |
---|
| 147 | reg [C_SLV_DWIDTH-1 : 0] slv_reg1; |
---|
| 148 | reg [C_SLV_DWIDTH-1 : 0] slv_reg2; |
---|
| 149 | reg [C_SLV_DWIDTH-1 : 0] slv_reg3; |
---|
| 150 | reg [C_SLV_DWIDTH-1 : 0] slv_reg4; |
---|
| 151 | reg [C_SLV_DWIDTH-1 : 0] slv_reg5; |
---|
| 152 | reg [C_SLV_DWIDTH-1 : 0] slv_reg6; |
---|
| 153 | reg [C_SLV_DWIDTH-1 : 0] slv_reg7; |
---|
| 154 | reg [C_SLV_DWIDTH-1 : 0] slv_reg8; |
---|
| 155 | reg [C_SLV_DWIDTH-1 : 0] slv_reg9; |
---|
| 156 | reg [C_SLV_DWIDTH-1 : 0] slv_reg10; |
---|
| 157 | reg [C_SLV_DWIDTH-1 : 0] slv_reg11; |
---|
| 158 | reg [C_SLV_DWIDTH-1 : 0] slv_reg12; |
---|
| 159 | reg [C_SLV_DWIDTH-1 : 0] slv_reg13; |
---|
| 160 | reg [C_SLV_DWIDTH-1 : 0] slv_reg14; |
---|
| 161 | reg [C_SLV_DWIDTH-1 : 0] slv_reg15; |
---|
| 162 | wire [15 : 0] slv_reg_write_sel; |
---|
| 163 | wire [15 : 0] slv_reg_read_sel; |
---|
| 164 | reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; |
---|
| 165 | wire slv_read_ack; |
---|
| 166 | wire slv_write_ack; |
---|
| 167 | integer byte_index, bit_index; |
---|
| 168 | |
---|
| 169 | // USER logic implementation added here |
---|
| 170 | |
---|
| 171 | // ------------------------------------------------------ |
---|
| 172 | // Example code to read/write user logic slave model s/w accessible registers |
---|
| 173 | // |
---|
| 174 | // Note: |
---|
| 175 | // The example code presented here is to show you one way of reading/writing |
---|
| 176 | // software accessible registers implemented in the user logic slave model. |
---|
| 177 | // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond |
---|
| 178 | // to one software accessible register by the top level template. For example, |
---|
| 179 | // if you have four 32 bit software accessible registers in the user logic, |
---|
| 180 | // you are basically operating on the following memory mapped registers: |
---|
| 181 | // |
---|
| 182 | // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register |
---|
| 183 | // "1000" C_BASEADDR + 0x0 |
---|
| 184 | // "0100" C_BASEADDR + 0x4 |
---|
| 185 | // "0010" C_BASEADDR + 0x8 |
---|
| 186 | // "0001" C_BASEADDR + 0xC |
---|
| 187 | // |
---|
| 188 | // ------------------------------------------------------ |
---|
| 189 | |
---|
| 190 | assign slv_reg_write_sel = Bus2IP_WrCE[15:0]; |
---|
| 191 | assign slv_reg_read_sel = Bus2IP_RdCE[15:0]; |
---|
| 192 | |
---|
| 193 | //Removed [14] from write_ack, so ack can be delayed following write to SPI Tx register |
---|
| 194 | // WrCE/RdCE[15:0] map to slv_reg[0:15] |
---|
| 195 | assign slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[15]; |
---|
| 196 | assign slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15]; |
---|
| 197 | |
---|
| 198 | // implement slave model register(s) |
---|
| 199 | always @( posedge Bus2IP_Clk ) |
---|
| 200 | begin |
---|
| 201 | |
---|
| 202 | if ( Bus2IP_Resetn == 1'b0 ) |
---|
| 203 | begin |
---|
| 204 | slv_reg0 <= 0; |
---|
| 205 | slv_reg1 <= 0; |
---|
| 206 | slv_reg2 <= 0; |
---|
| 207 | slv_reg3 <= 0; |
---|
| 208 | slv_reg4 <= 0; |
---|
| 209 | slv_reg5 <= 0; |
---|
| 210 | slv_reg6 <= 0; |
---|
| 211 | slv_reg7 <= 0; |
---|
| 212 | slv_reg8 <= 0; |
---|
| 213 | slv_reg9 <= 0; |
---|
| 214 | slv_reg10 <= 0; |
---|
| 215 | slv_reg11 <= 0; |
---|
| 216 | slv_reg12 <= 0; |
---|
| 217 | slv_reg13 <= 0; |
---|
| 218 | slv_reg14 <= 0; |
---|
| 219 | slv_reg15 <= 0; |
---|
| 220 | end |
---|
| 221 | else |
---|
| 222 | case ( slv_reg_write_sel ) |
---|
| 223 | 16'b1000000000000000 : |
---|
| 224 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 225 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 226 | slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 227 | 16'b0100000000000000 : |
---|
| 228 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 229 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 230 | slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 231 | 16'b0010000000000000 : |
---|
| 232 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 233 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 234 | slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 235 | 16'b0001000000000000 : |
---|
| 236 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 237 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 238 | slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 239 | 16'b0000100000000000 : |
---|
| 240 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 241 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 242 | slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 243 | 16'b0000010000000000 : |
---|
| 244 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 245 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 246 | slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 247 | 16'b0000001000000000 : |
---|
| 248 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 249 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 250 | slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 251 | 16'b0000000100000000 : |
---|
| 252 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 253 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 254 | slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 255 | 16'b0000000010000000 : |
---|
| 256 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 257 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 258 | slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 259 | 16'b0000000001000000 : |
---|
| 260 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 261 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 262 | slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 263 | 16'b0000000000100000 : |
---|
| 264 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 265 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 266 | slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 267 | 16'b0000000000010000 : |
---|
| 268 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 269 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 270 | slv_reg11[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 271 | 16'b0000000000001000 : |
---|
| 272 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 273 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 274 | slv_reg12[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 275 | 16'b0000000000000100 : |
---|
| 276 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 277 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 278 | slv_reg13[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 279 | 16'b0000000000000010 : |
---|
| 280 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 281 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 282 | slv_reg14[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 283 | 16'b0000000000000001 : |
---|
| 284 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 285 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 286 | slv_reg15[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 287 | default : begin |
---|
| 288 | slv_reg0 <= slv_reg0; |
---|
| 289 | slv_reg1 <= slv_reg1; |
---|
| 290 | slv_reg2 <= slv_reg2; |
---|
| 291 | slv_reg3 <= slv_reg3; |
---|
| 292 | slv_reg4 <= slv_reg4; |
---|
| 293 | slv_reg5 <= slv_reg5; |
---|
| 294 | slv_reg6 <= slv_reg6; |
---|
| 295 | slv_reg7 <= slv_reg7; |
---|
| 296 | slv_reg8 <= slv_reg8; |
---|
| 297 | slv_reg9 <= slv_reg9; |
---|
| 298 | slv_reg10 <= slv_reg10; |
---|
| 299 | slv_reg11 <= slv_reg11; |
---|
| 300 | slv_reg12 <= slv_reg12; |
---|
| 301 | slv_reg13 <= slv_reg13; |
---|
| 302 | slv_reg14 <= slv_reg14; |
---|
| 303 | slv_reg15 <= slv_reg15; |
---|
| 304 | end |
---|
| 305 | endcase |
---|
| 306 | |
---|
| 307 | end // SLAVE_REG_WRITE_PROC |
---|
| 308 | |
---|
| 309 | wire [7:0] RFA_AD_spi_rx_byte; |
---|
| 310 | wire [7:0] RFB_AD_spi_rx_byte; |
---|
| 311 | wire [7:0] RFC_AD_spi_rx_byte; |
---|
| 312 | wire [7:0] RFD_AD_spi_rx_byte; |
---|
| 313 | |
---|
| 314 | |
---|
| 315 | // implement slave model register read mux |
---|
| 316 | always @*//( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 ) |
---|
| 317 | begin |
---|
| 318 | |
---|
| 319 | case ( slv_reg_read_sel ) |
---|
| 320 | 16'b1000000000000000 : slv_ip2bus_data <= slv_reg0; |
---|
| 321 | 16'b0100000000000000 : slv_ip2bus_data <= slv_reg1; |
---|
| 322 | 16'b0010000000000000 : slv_ip2bus_data <= {RFD_AD_spi_rx_byte, RFC_AD_spi_rx_byte, RFB_AD_spi_rx_byte, RFA_AD_spi_rx_byte}; |
---|
| 323 | 16'b0001000000000000 : slv_ip2bus_data <= slv_reg3; |
---|
| 324 | 16'b0000100000000000 : slv_ip2bus_data <= slv_reg4; |
---|
| 325 | 16'b0000010000000000 : slv_ip2bus_data <= slv_reg5; |
---|
| 326 | 16'b0000001000000000 : slv_ip2bus_data <= slv_reg6; |
---|
| 327 | 16'b0000000100000000 : slv_ip2bus_data <= slv_reg7; |
---|
| 328 | 16'b0000000010000000 : slv_ip2bus_data <= slv_reg8; |
---|
| 329 | 16'b0000000001000000 : slv_ip2bus_data <= slv_reg9; |
---|
| 330 | 16'b0000000000100000 : slv_ip2bus_data <= slv_reg10; |
---|
| 331 | 16'b0000000000010000 : slv_ip2bus_data <= slv_reg11; |
---|
| 332 | 16'b0000000000001000 : slv_ip2bus_data <= slv_reg12; |
---|
| 333 | 16'b0000000000000100 : slv_ip2bus_data <= slv_reg13; |
---|
| 334 | 16'b0000000000000010 : slv_ip2bus_data <= slv_reg14; |
---|
| 335 | 16'b0000000000000001 : slv_ip2bus_data <= slv_reg15; |
---|
| 336 | default : slv_ip2bus_data <= 0; |
---|
| 337 | endcase |
---|
| 338 | |
---|
| 339 | end // SLAVE_REG_READ_PROC |
---|
| 340 | |
---|
| 341 | // ------------------------------------------------------------ |
---|
| 342 | // Example code to drive IP to Bus signals |
---|
| 343 | // ------------------------------------------------------------ |
---|
| 344 | |
---|
| 345 | assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; |
---|
| 346 | // assign IP2Bus_WrAck = slv_write_ack; //Overridden below |
---|
| 347 | assign IP2Bus_RdAck = slv_read_ack; |
---|
| 348 | assign IP2Bus_Error = 0; |
---|
| 349 | |
---|
| 350 | /* Address map: |
---|
| 351 | HDL is coded [MSB:LSB] = [31:0], per Xilinx's convention for AXI peripherals |
---|
| 352 | regX[31] maps to 0x80000000 in C driver |
---|
| 353 | regX[0] maps to 0x00000001 in C driver |
---|
| 354 | |
---|
| 355 | 0: Config: {clk_div_sel[2:0], 1'b0, RFA_AD_rst_n, RFB_AD_rst_n, RFC_AD_rst_n, RFD_AD_rst_n, 24'b0} |
---|
| 356 | [ 2: 0] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x00000007 |
---|
| 357 | [ 3] Reserved |
---|
| 358 | [ 4] RFA_AD reset (active low) 0x00000010 |
---|
| 359 | [ 5] RFB_AD reset (active low) 0x00000020 |
---|
| 360 | [ 6] RFC_AD reset (active low) 0x00000040 |
---|
| 361 | [ 7] RFD_AD reset (active low) 0x00000080 |
---|
| 362 | [31: 8] Reserved |
---|
| 363 | |
---|
| 364 | 1: SPI Tx |
---|
| 365 | [ 7: 0] Tx data byte 0x00FF |
---|
| 366 | [15: 8] 8-bit register address (0x00 to 0xFF all valid) 0xFF00 |
---|
| 367 | [20:16] 5'b0 (always zero) |
---|
| 368 | [22:21] Num bytes to Tx/Rx; must be 2'b0 for 1-byte Tx/Rx |
---|
| 369 | [ 23] RW# 1=Read, 0=Write |
---|
| 370 | [ 24] RFA_AD chip select mask |
---|
| 371 | [ 25] RFB_AD chip select mask |
---|
| 372 | [ 26] RFC_AD chip select mask |
---|
| 373 | [ 27] RFD_AD chip select mask |
---|
| 374 | [31:28] Reserved |
---|
| 375 | |
---|
| 376 | 2: SPI Rx: {RFA_AD_rxByte, RFB_AD_rxByte, RFC_AD_rxByte, RFD_AD_rxByte} |
---|
| 377 | [ 7: 0] SPI Rx byte for RFA_AD 0x000000FF |
---|
| 378 | [15: 8] SPI Rx byte for RFB_AD 0x0000FF00 |
---|
| 379 | [23:16] SPI Rx byte for RFC_AD 0x00FF0000 |
---|
| 380 | [31:24] SPI Rx byte for RFD_AD 0xFF000000 |
---|
| 381 | |
---|
| 382 | 3-15: Reserved |
---|
| 383 | */ |
---|
| 384 | |
---|
| 385 | `define AD9963_SPI_XFER_LEN 24 //AD9963 |
---|
| 386 | `define AD9963_SPI_FIRST_RXBIT 5'd16 //AD9963 (16-bit instruction, 8-bit data) |
---|
| 387 | |
---|
| 388 | wire [4:0] spi_bitNum; |
---|
| 389 | wire spi_mosi; |
---|
| 390 | wire spi_sclk; |
---|
| 391 | wire spi_cs; |
---|
| 392 | wire spi_rnw; |
---|
| 393 | wire RFA_AD_spi_cs, RFB_AD_spi_cs, RFC_AD_spi_cs, RFD_AD_spi_cs; |
---|
| 394 | wire spi_tx_reg_write; |
---|
| 395 | wire [2:0] clk_div_sel; |
---|
| 396 | wire spi_xfer_done; |
---|
| 397 | |
---|
| 398 | wire [31:0] RFA_AD_spi_rxData; |
---|
| 399 | wire [31:0] RFB_AD_spi_rxData; |
---|
| 400 | wire [31:0] RFC_AD_spi_rxData; |
---|
| 401 | wire [31:0] RFD_AD_spi_rxData; |
---|
| 402 | |
---|
| 403 | wire RFA_AD_spi_mosi, RFA_AD_spi_miso; |
---|
| 404 | wire RFB_AD_spi_mosi, RFB_AD_spi_miso; |
---|
| 405 | wire RFC_AD_spi_mosi, RFC_AD_spi_miso; |
---|
| 406 | wire RFD_AD_spi_mosi, RFD_AD_spi_miso; |
---|
| 407 | |
---|
| 408 | //Extract bits from IPIF slave registers and control signals |
---|
| 409 | |
---|
| 410 | //spi_io stores 32 bits for Tx/Rx |
---|
| 411 | // AD9963 only outputs 8-bit words during reads, always the last 8 bits of the transfer |
---|
| 412 | assign RFA_AD_spi_rx_byte = RFA_AD_spi_rxData[7:0]; |
---|
| 413 | assign RFB_AD_spi_rx_byte = RFB_AD_spi_rxData[7:0]; |
---|
| 414 | assign RFC_AD_spi_rx_byte = RFC_AD_spi_rxData[7:0]; |
---|
| 415 | assign RFD_AD_spi_rx_byte = RFD_AD_spi_rxData[7:0]; |
---|
| 416 | |
---|
| 417 | //SPI clock divider selection |
---|
| 418 | assign clk_div_sel = slv_reg0[2:0]; //0x7 from driver |
---|
| 419 | |
---|
| 420 | //SPI device resets (active low) |
---|
| 421 | assign RFA_AD_reset_n = slv_reg0[4]; //0x10 from driver |
---|
| 422 | assign RFB_AD_reset_n = slv_reg0[5]; //0x20 from driver |
---|
| 423 | assign RFC_AD_reset_n = slv_reg0[6]; //0x40 from driver |
---|
| 424 | assign RFD_AD_reset_n = slv_reg0[7]; //0x80 from driver |
---|
| 425 | |
---|
| 426 | //SPI device chip selects (active high; inverted before use below) |
---|
| 427 | assign RFA_AD_spi_cs = slv_reg1[24]; //0x01000000 from driver |
---|
| 428 | assign RFB_AD_spi_cs = slv_reg1[25]; //0x02000000 from driver |
---|
| 429 | assign RFC_AD_spi_cs = slv_reg1[26]; //0x04000000 from driver |
---|
| 430 | assign RFD_AD_spi_cs = slv_reg1[27]; //0x08000000 from driver |
---|
| 431 | |
---|
| 432 | //Internal signal for read vs. write transaction |
---|
| 433 | assign spi_rnw = slv_reg1[`AD9963_SPI_XFER_LEN-1]; //0x00800000 from driver |
---|
| 434 | |
---|
| 435 | //Use the IPIC write-enable for the SPI Tx register as the SPI go |
---|
| 436 | // The bus will be paused until this core ACKs the write |
---|
| 437 | assign spi_tx_reg_write = Bus2IP_WrCE[14]; //WrCE[15:0] maps to slv_reg[0:15] |
---|
| 438 | |
---|
| 439 | //spi_tx_reg_write (Bus2IP_WrCE[14]) de-asserts as soon as transaction is ACK'd |
---|
| 440 | // so this mux switches back to the generic ACK as soon as the SPI xfer is done |
---|
| 441 | //Thus, the duration of assertion for spi_xfer_done doesn't really matter |
---|
| 442 | //A bit fast-n-loose, but works ok |
---|
| 443 | assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack; |
---|
| 444 | |
---|
| 445 | //SPI device chip selects are active low |
---|
| 446 | assign RFA_AD_spi_cs_n = ~(RFA_AD_spi_cs & spi_cs); |
---|
| 447 | assign RFB_AD_spi_cs_n = ~(RFB_AD_spi_cs & spi_cs); |
---|
| 448 | assign RFC_AD_spi_cs_n = ~(RFC_AD_spi_cs & spi_cs); |
---|
| 449 | assign RFD_AD_spi_cs_n = ~(RFD_AD_spi_cs & spi_cs); |
---|
| 450 | |
---|
| 451 | //Mask each device's SPI clock output by its CS; no point toggling signals that will be ignored |
---|
| 452 | assign RFA_AD_spi_sclk = (spi_sclk & RFA_AD_spi_cs); |
---|
| 453 | assign RFB_AD_spi_sclk = (spi_sclk & RFB_AD_spi_cs); |
---|
| 454 | assign RFC_AD_spi_sclk = (spi_sclk & RFC_AD_spi_cs); |
---|
| 455 | assign RFD_AD_spi_sclk = (spi_sclk & RFD_AD_spi_cs); |
---|
| 456 | |
---|
| 457 | //All SPI devices driven by same serial data output; CS signals control who listens |
---|
| 458 | assign RFA_AD_spi_mosi = RFA_AD_spi_cs ? spi_mosi : 1'b0; |
---|
| 459 | assign RFB_AD_spi_mosi = RFB_AD_spi_cs ? spi_mosi : 1'b0; |
---|
| 460 | assign RFC_AD_spi_mosi = RFC_AD_spi_cs ? spi_mosi : 1'b0; |
---|
| 461 | assign RFD_AD_spi_mosi = RFD_AD_spi_cs ? spi_mosi : 1'b0; |
---|
| 462 | |
---|
| 463 | //AD9963 SPI data is bi-directional; IOBUFs instantiated here to switch I vs. O mid-transfer |
---|
| 464 | //Set spi_sdio pins as inputs except when actively driving, to avoid accidental drive fights |
---|
| 465 | // FPGA drives the sdio pin when: |
---|
| 466 | // An SPI transaction is in progress AND |
---|
| 467 | // The transaction is a read AND the current bit is part of the instruction bytes |
---|
| 468 | // OR |
---|
| 469 | // The transaction is a write |
---|
| 470 | assign RFA_AD_spi_sdio_output_en = spi_cs & ( (spi_rnw & (spi_bitNum < `AD9963_SPI_FIRST_RXBIT)) | (~spi_rnw)); |
---|
| 471 | assign RFB_AD_spi_sdio_output_en = spi_cs & ( (spi_rnw & (spi_bitNum < `AD9963_SPI_FIRST_RXBIT)) | (~spi_rnw)); |
---|
| 472 | assign RFC_AD_spi_sdio_output_en = spi_cs & ( (spi_rnw & (spi_bitNum < `AD9963_SPI_FIRST_RXBIT)) | (~spi_rnw)); |
---|
| 473 | assign RFD_AD_spi_sdio_output_en = spi_cs & ( (spi_rnw & (spi_bitNum < `AD9963_SPI_FIRST_RXBIT)) | (~spi_rnw)); |
---|
| 474 | |
---|
| 475 | IOBUF IOBUF_RFA_AD_sdio ( |
---|
| 476 | .IO(RFA_AD_spi_sdio), //Connected to actual FPGA pin |
---|
| 477 | .I(RFA_AD_spi_mosi), //Logic-> Pad, input to OBUFT |
---|
| 478 | .O(RFA_AD_spi_miso), //Pad-> Logic, output of IBUF |
---|
| 479 | .T(~RFA_AD_spi_sdio_output_en) |
---|
| 480 | ); |
---|
| 481 | |
---|
| 482 | IOBUF IOBUF_RFB_AD_sdio ( |
---|
| 483 | .IO(RFB_AD_spi_sdio), //Connected to actual FPGA pin |
---|
| 484 | .I(RFB_AD_spi_mosi), //Logic-> Pad, input to OBUFT |
---|
| 485 | .O(RFB_AD_spi_miso), //Pad-> Logic, output of IBUF |
---|
| 486 | .T(~RFB_AD_spi_sdio_output_en) |
---|
| 487 | ); |
---|
| 488 | |
---|
| 489 | IOBUF IOBUF_RFC_AD_sdio ( |
---|
| 490 | .IO(RFC_AD_spi_sdio), //Connected to actual FPGA pin |
---|
| 491 | .I(RFC_AD_spi_mosi), //Logic-> Pad, input to OBUFT |
---|
| 492 | .O(RFC_AD_spi_miso), //Pad-> Logic, output of IBUF |
---|
| 493 | .T(~RFC_AD_spi_sdio_output_en) |
---|
| 494 | ); |
---|
| 495 | |
---|
| 496 | IOBUF IOBUF_RFD_AD_sdio ( |
---|
| 497 | .IO(RFD_AD_spi_sdio), //Connected to actual FPGA pin |
---|
| 498 | .I(RFD_AD_spi_mosi), //Logic-> Pad, input to OBUFT |
---|
| 499 | .O(RFD_AD_spi_miso), //Pad-> Logic, output of IBUF |
---|
| 500 | .T(~RFD_AD_spi_sdio_output_en) |
---|
| 501 | ); |
---|
| 502 | |
---|
| 503 | warp_spi_io #(.SPI_XFER_LEN(`AD9963_SPI_XFER_LEN)) spi_io |
---|
| 504 | ( |
---|
| 505 | .sys_clk(Bus2IP_Clk), |
---|
| 506 | .reset(~Bus2IP_Resetn),//warp_spi_io.reset is active high |
---|
| 507 | .go(spi_tx_reg_write), |
---|
| 508 | .done(spi_xfer_done), |
---|
| 509 | .clkDiv(clk_div_sel), |
---|
| 510 | |
---|
| 511 | .currBitNum(spi_bitNum), |
---|
| 512 | |
---|
| 513 | .txData(slv_reg1), |
---|
| 514 | |
---|
| 515 | .rxData1(RFA_AD_spi_rxData), |
---|
| 516 | .rxData2(RFB_AD_spi_rxData), |
---|
| 517 | .rxData3(RFC_AD_spi_rxData), |
---|
| 518 | .rxData4(RFD_AD_spi_rxData), |
---|
| 519 | |
---|
| 520 | .spi_cs(spi_cs), |
---|
| 521 | .spi_sclk(spi_sclk), |
---|
| 522 | |
---|
| 523 | .spi_mosi(spi_mosi), |
---|
| 524 | |
---|
| 525 | .spi_miso1(RFA_AD_spi_miso), |
---|
| 526 | .spi_miso2(RFB_AD_spi_miso), |
---|
| 527 | .spi_miso3(RFC_AD_spi_miso), |
---|
| 528 | .spi_miso4(RFD_AD_spi_miso) |
---|
| 529 | ); |
---|
| 530 | |
---|
| 531 | endmodule |
---|