[1766] | 1 | ###################################################################
|
---|
| 2 | ##
|
---|
| 3 | ## Name : warp_ad_controller
|
---|
| 4 | ## Desc : Microprocessor Peripheral Description
|
---|
| 5 | ## : Automatically generated by PsfUtility
|
---|
| 6 | ##
|
---|
| 7 | ###################################################################
|
---|
| 8 |
|
---|
| 9 | BEGIN w3_ad_controller
|
---|
| 10 |
|
---|
| 11 | ## Peripheral Options
|
---|
| 12 | OPTION IPTYPE = PERIPHERAL
|
---|
| 13 | OPTION IMP_NETLIST = TRUE
|
---|
| 14 | OPTION HDL = MIXED
|
---|
| 15 | OPTION IP_GROUP = MICROBLAZE:PPC:USER
|
---|
| 16 | OPTION DESC = WARP_AD_CONTROLLER
|
---|
| 17 | OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
|
---|
| 18 |
|
---|
| 19 |
|
---|
| 20 | ## Bus Interfaces
|
---|
| 21 | BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
|
---|
| 22 |
|
---|
| 23 | ## Generics for VHDL or Parameters for Verilog
|
---|
| 24 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
|
---|
| 25 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
|
---|
| 26 | PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
|
---|
| 27 | PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
|
---|
| 28 | PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
|
---|
| 29 | PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
|
---|
| 30 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
|
---|
| 31 | PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
|
---|
| 32 | PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
|
---|
| 33 | PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
|
---|
| 34 | PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
|
---|
| 35 | PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1)
|
---|
| 36 | PARAMETER C_FAMILY = virtex6, DT = STRING
|
---|
| 37 |
|
---|
| 38 | ## Ports
|
---|
| 39 | PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
|
---|
| 40 | PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
|
---|
| 41 | PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
|
---|
| 42 | PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
|
---|
| 43 | PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
|
---|
| 44 | PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
|
---|
| 45 | PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
|
---|
| 46 | PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
|
---|
| 47 | PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
|
---|
| 48 | PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
|
---|
| 49 | PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
|
---|
| 50 | PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
|
---|
| 51 | PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
|
---|
| 52 | PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
|
---|
| 53 | PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
|
---|
| 54 | PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
|
---|
| 55 | PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
|
---|
| 56 | PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
|
---|
| 57 | PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
|
---|
| 58 | PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
|
---|
| 59 | PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
|
---|
| 60 | PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
|
---|
| 61 | PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
|
---|
| 62 | PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
|
---|
| 63 | PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
|
---|
| 64 | PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
|
---|
| 65 | PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
|
---|
| 66 | PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
|
---|
| 67 | PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
|
---|
| 68 | PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
|
---|
| 69 | PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
|
---|
| 70 | PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
|
---|
| 71 | PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
|
---|
| 72 | PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
|
---|
| 73 | PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
|
---|
| 74 | PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
|
---|
| 75 | PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
|
---|
| 76 | PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
|
---|
| 77 | PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
|
---|
| 78 | PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
|
---|
| 79 | PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
|
---|
| 80 | PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
|
---|
| 81 |
|
---|
| 82 |
|
---|
| 83 | PORT RFA_AD_spi_sclk = "", DIR = O
|
---|
| 84 | PORT RFA_AD_spi_cs_n = "", DIR = O
|
---|
| 85 | PORT RFA_AD_reset_n = "", DIR = O
|
---|
| 86 | PORT RFA_AD_spi_sdio = "", DIR = IO, THREE_STATE = FALSE
|
---|
| 87 |
|
---|
| 88 | PORT RFB_AD_spi_sclk = "", DIR = O
|
---|
| 89 | PORT RFB_AD_spi_cs_n = "", DIR = O
|
---|
| 90 | PORT RFB_AD_reset_n = "", DIR = O
|
---|
| 91 | PORT RFB_AD_spi_sdio = "", DIR = IO, THREE_STATE = FALSE
|
---|
| 92 |
|
---|
| 93 | END
|
---|