source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/doc/html/api/group__user__functions.html

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adding driver docs for clock controller
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26   <div id="projectname">w3_clock_controller_axi Driver
27   </div>
28   <div id="projectbrief">Driver for WARP v3 clock controller pcore (w3_clock_controller_axi)</div>
29  </td>
30 </tr>
31 </tbody>
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57<div class="header">
58  <div class="summary">
59<a href="#func-members">Functions</a>  </div>
60  <div class="headertitle">
61<div class="title">Functions</div>  </div>
62</div><!--header-->
63<div class="contents">
64<table class="memberdecls">
65<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
66Functions</h2></td></tr>
67<tr class="memitem:ga6a17b6d143e2d820f0c5ae4283496ac7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga6a17b6d143e2d820f0c5ae4283496ac7">clk_init</a> (u32 baseaddr, u8 clkDiv)</td></tr>
68<tr class="separator:ga6a17b6d143e2d820f0c5ae4283496ac7"><td class="memSeparator" colspan="2">&#160;</td></tr>
69<tr class="memitem:ga509f9e41d2bac1b3dbf1541709d1179c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c">clk_config_outputs</a> (u32 baseaddr, u8 clkOutMode, u32 clkOutSel)</td></tr>
70<tr class="separator:ga509f9e41d2bac1b3dbf1541709d1179c"><td class="memSeparator" colspan="2">&#160;</td></tr>
71<tr class="memitem:ga18b3cfc8fd63d3f9534de4278c1c8fe2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga18b3cfc8fd63d3f9534de4278c1c8fe2">clk_config_input_rf_ref</a> (u32 baseaddr, u8 clkInSel)</td></tr>
72<tr class="separator:ga18b3cfc8fd63d3f9534de4278c1c8fe2"><td class="memSeparator" colspan="2">&#160;</td></tr>
73<tr class="memitem:ga3c02036fe93032f911218f50452fa682"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga3c02036fe93032f911218f50452fa682">clk_config_read_clkmod_status</a> (u32 baseaddr)</td></tr>
74<tr class="separator:ga3c02036fe93032f911218f50452fa682"><td class="memSeparator" colspan="2">&#160;</td></tr>
75<tr class="memitem:ga58355f82b91625951cad329e82e3e2a6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga58355f82b91625951cad329e82e3e2a6">clk_config_dividers</a> (u32 baseaddr, u8 clkDiv, u32 clkOutSel)</td></tr>
76<tr class="separator:ga58355f82b91625951cad329e82e3e2a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
77<tr class="memitem:ga0769cba992797225f0e3f8f58d9b6b1a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga0769cba992797225f0e3f8f58d9b6b1a">clk_spi_read</a> (u32 baseaddr, u32 csMask, u8 regAddr)</td></tr>
78<tr class="separator:ga0769cba992797225f0e3f8f58d9b6b1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
79<tr class="memitem:ga35a167edcce1415775ea854c165408d4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga35a167edcce1415775ea854c165408d4">clk_spi_write</a> (u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte)</td></tr>
80<tr class="separator:ga35a167edcce1415775ea854c165408d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
81</table>
82<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
83<p>Example: </p><div class="fragment"><div class="line"><span class="comment">//Assumes user code sets CLK_BASEADDR to base address of w3_clock_controller_axi core, as set in xparameters.h</span></div>
84<div class="line"></div>
85<div class="line"><span class="comment">//Initialize the AD9512 clock buffers</span></div>
86<div class="line"><a class="code" href="group__user__functions.html#ga6a17b6d143e2d820f0c5ae4283496ac7">clk_init</a>(CLK_BASEADDR, 3);</div>
87<div class="line"></div>
88<div class="line"><span class="comment">//Enable clock outputs to FMC slot</span></div>
89<div class="line"><a class="code" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c">clk_config_outputs</a>(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC | CLK_RFREF_OUTSEL_FMC));</div>
90<div class="line"></div>
91<div class="line"><span class="comment">//Disable clock outputs to clock module header</span></div>
92<div class="line"><a class="code" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c">clk_config_outputs</a>(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));</div>
93<div class="line"></div>
94<div class="line"><span class="comment">//Set clock to AD chips to 40MHz (80MHz source divided by 2)</span></div>
95<div class="line"><a class="code" href="group__user__functions.html#ga58355f82b91625951cad329e82e3e2a6">clk_config_dividers</a>(CLK_BASEADDR, 2, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));</div>
96</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
97<a class="anchor" id="ga6a17b6d143e2d820f0c5ae4283496ac7"></a>
98<div class="memitem">
99<div class="memproto">
100      <table class="memname">
101        <tr>
102          <td class="memname">int clk_init </td>
103          <td>(</td>
104          <td class="paramtype">u32&#160;</td>
105          <td class="paramname"><em>baseaddr</em>, </td>
106        </tr>
107        <tr>
108          <td class="paramkey"></td>
109          <td></td>
110          <td class="paramtype">u8&#160;</td>
111          <td class="paramname"><em>clkDiv</em>&#160;</td>
112        </tr>
113        <tr>
114          <td></td>
115          <td>)</td>
116          <td></td><td></td>
117        </tr>
118      </table>
119</div><div class="memdoc">
120
121<p>Initializes the clock controller. This function must be called once at boot before any AD or RF operations will work. The w3_clock_controller_axi HDL applies preliminary configuration values to the sampling and RF reference clock buffers, and (if preset) the PLL+buffer on the CM-PLL clock module. </p>
122<p>The HDL applies the minimum set of configuration values to allow the MicroBlaze subsystem to boot. This function does not override any configuration values applied by the HDL.</p>
123<p>Refer to the pcore user guide for details on the pre-boot configuration process: <a href="http://warpproject.org/trac/wiki/cores/w3_clock_controller">http://warpproject.org/trac/wiki/cores/w3_clock_controller</a></p>
124<p>Default config is:</p><ul>
125<li>On board 80MHz TCXO used as source for sampling and RF ref clock buffers</li>
126<li>80MHz clock driven to FPGA, RF A and RF B ADC/DACs</li>
127<li>40MHz clock driven to RF A and B transceivers</li>
128<li>FMC and clock module header clocks disabled <dl class="params"><dt>Parameters</dt><dd>
129  <table class="params">
130    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller_axi pcore </td></tr>
131    <tr><td class="paramname">clkDiv</td><td>Clock divider for SPI serial clock (set to 3 for 160MHz bus) </td></tr>
132  </table>
133  </dd>
134</dl>
135</li>
136</ul>
137
138</div>
139</div>
140<a class="anchor" id="ga509f9e41d2bac1b3dbf1541709d1179c"></a>
141<div class="memitem">
142<div class="memproto">
143      <table class="memname">
144        <tr>
145          <td class="memname">int clk_config_outputs </td>
146          <td>(</td>
147          <td class="paramtype">u32&#160;</td>
148          <td class="paramname"><em>baseaddr</em>, </td>
149        </tr>
150        <tr>
151          <td class="paramkey"></td>
152          <td></td>
153          <td class="paramtype">u8&#160;</td>
154          <td class="paramname"><em>clkOutMode</em>, </td>
155        </tr>
156        <tr>
157          <td class="paramkey"></td>
158          <td></td>
159          <td class="paramtype">u32&#160;</td>
160          <td class="paramname"><em>clkOutSel</em>&#160;</td>
161        </tr>
162        <tr>
163          <td></td>
164          <td>)</td>
165          <td></td><td></td>
166        </tr>
167      </table>
168</div><div class="memdoc">
169
170<p>Configures which outputs are en/disabled in both AD9512 clock buffers. </p>
171<dl class="params"><dt>Parameters</dt><dd>
172  <table class="params">
173    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller_axi pcore </td></tr>
174    <tr><td class="paramname">clkOutMode</td><td>New mode for selected clock outputs; must be CLK_OUTPUT_ON or CLK_OUTPUT_OFF </td></tr>
175    <tr><td class="paramname">clkOutSel</td><td>Masks to select which clock outputs to affect; must be OR'd combination of: <table class="doxtable">
176<tr>
177<th>Mask </th><th>Selected Output  </th></tr>
178<tr>
179<td>CLK_SAMP_OUTSEL_FMC </td><td>Sampling clock buffer to FMC slot </td></tr>
180<tr>
181<td>CLK_SAMP_OUTSEL_CLKMODHDR </td><td>Sampling clock buffer to clock module header </td></tr>
182<tr>
183<td>CLK_SAMP_OUTSEL_FPGA </td><td>Sampling clock buffer to FPGA </td></tr>
184<tr>
185<td>CLK_SAMP_OUTSEL_AD_RFA </td><td>Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) </td></tr>
186<tr>
187<td>CLK_SAMP_OUTSEL_AD_RFB </td><td>Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) </td></tr>
188<tr>
189<td>CLK_RFREF_OUTSEL_FMC </td><td>RF ref clock buffer to FMC </td></tr>
190<tr>
191<td>CLK_RFREF_OUTSEL_CLKMODHDR </td><td>RF ref clock buffer to clock module header </td></tr>
192<tr>
193<td>CLK_RFREF_OUTSEL_RFAB </td><td>RF ref clock buffer to RF A and B transceivers </td></tr>
194</table>
195</td></tr>
196  </table>
197  </dd>
198</dl>
199<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl>
200
201</div>
202</div>
203<a class="anchor" id="ga18b3cfc8fd63d3f9534de4278c1c8fe2"></a>
204<div class="memitem">
205<div class="memproto">
206      <table class="memname">
207        <tr>
208          <td class="memname">int clk_config_input_rf_ref </td>
209          <td>(</td>
210          <td class="paramtype">u32&#160;</td>
211          <td class="paramname"><em>baseaddr</em>, </td>
212        </tr>
213        <tr>
214          <td class="paramkey"></td>
215          <td></td>
216          <td class="paramtype">u8&#160;</td>
217          <td class="paramname"><em>clkInSel</em>&#160;</td>
218        </tr>
219        <tr>
220          <td></td>
221          <td>)</td>
222          <td></td><td></td>
223        </tr>
224      </table>
225</div><div class="memdoc">
226
227<p>Configures whether the RF Reference Buffer uses the on-board or off-board clock source. </p>
228<dl class="params"><dt>Parameters</dt><dd>
229  <table class="params">
230    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller_axi pcore </td></tr>
231    <tr><td class="paramname">clkInSel</td><td>Clock source mask, must be either CLK_INSEL_ONBOARD (for on-board oscillator) or CLK_INSEL_CLKMOD (for off-board clock via clock module header) <table class="doxtable">
232<tr>
233<th>Mask </th><th>Selected Input  </th></tr>
234<tr>
235<td>CLK_INSEL_ONBOARD </td><td>Selects on-board TCXO as RF Reference clock source (AD9512 CLK1/CLK1B port) </td></tr>
236<tr>
237<td>CLK_INSEL_CLKMOD </td><td>Selects off-board clock from clock module header as RF Reference clock source (AD9512 CLK2/CLK2B port) </td></tr>
238</table>
239</td></tr>
240  </table>
241  </dd>
242</dl>
243<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl>
244
245</div>
246</div>
247<a class="anchor" id="ga3c02036fe93032f911218f50452fa682"></a>
248<div class="memitem">
249<div class="memproto">
250<table class="mlabels">
251  <tr>
252  <td class="mlabels-left">
253      <table class="memname">
254        <tr>
255          <td class="memname">u32 clk_config_read_clkmod_status </td>
256          <td>(</td>
257          <td class="paramtype">u32&#160;</td>
258          <td class="paramname"><em>baseaddr</em></td><td>)</td>
259          <td></td>
260        </tr>
261      </table>
262  </td>
263  <td class="mlabels-right">
264<span class="mlabels"><span class="mlabel">inline</span></span>  </td>
265  </tr>
266</table>
267</div><div class="memdoc">
268
269<p>Reads the status pins of the currently installed clock module. </p>
270<dl class="params"><dt>Parameters</dt><dd>
271  <table class="params">
272    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller_axi pcore </td></tr>
273  </table>
274  </dd>
275</dl>
276<dl class="section return"><dt>Returns</dt><dd>Returns the clock module status; the meaning of the status bits depends on the currently installed module.</dd></dl>
277<p>For the CM-MMCX, 2 LSB are value of 2-position SIP switch. For the CM-PLL, 3 LSB are the value of the 3 LSB of the DIP switch. Bit 0x8 is the PLL status. </p>
278
279</div>
280</div>
281<a class="anchor" id="ga58355f82b91625951cad329e82e3e2a6"></a>
282<div class="memitem">
283<div class="memproto">
284      <table class="memname">
285        <tr>
286          <td class="memname">int clk_config_dividers </td>
287          <td>(</td>
288          <td class="paramtype">u32&#160;</td>
289          <td class="paramname"><em>baseaddr</em>, </td>
290        </tr>
291        <tr>
292          <td class="paramkey"></td>
293          <td></td>
294          <td class="paramtype">u8&#160;</td>
295          <td class="paramname"><em>clkDiv</em>, </td>
296        </tr>
297        <tr>
298          <td class="paramkey"></td>
299          <td></td>
300          <td class="paramtype">u32&#160;</td>
301          <td class="paramname"><em>clkOutSel</em>&#160;</td>
302        </tr>
303        <tr>
304          <td></td>
305          <td>)</td>
306          <td></td><td></td>
307        </tr>
308      </table>
309</div><div class="memdoc">
310
311<p>Configures output dividers in both AD9512 clock buffers. </p>
312<dl class="params"><dt>Parameters</dt><dd>
313  <table class="params">
314    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller_axi pcore </td></tr>
315    <tr><td class="paramname">clkDiv</td><td>Divider value to set; must be 1 or even integer in [2,32] </td></tr>
316    <tr><td class="paramname">clkOutSel</td><td>Masks to select which clock outputs to affect; must be OR'd combination of: <table class="doxtable">
317<tr>
318<th>Mask </th><th>Selected Output  </th></tr>
319<tr>
320<td>CLK_SAMP_OUTSEL_FMC </td><td>Sampling clock buffer to FMC slot </td></tr>
321<tr>
322<td>CLK_SAMP_OUTSEL_CLKMODHDR </td><td>Sampling clock buffer to clock module header </td></tr>
323<tr>
324<td>CLK_SAMP_OUTSEL_FPGA </td><td>Sampling clock buffer to FPGA </td></tr>
325<tr>
326<td>CLK_SAMP_OUTSEL_AD_RFA </td><td>Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) </td></tr>
327<tr>
328<td>CLK_SAMP_OUTSEL_AD_RFB </td><td>Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) </td></tr>
329<tr>
330<td>CLK_RFREF_OUTSEL_FMC </td><td>RF ref clock buffer to FMC </td></tr>
331<tr>
332<td>CLK_RFREF_OUTSEL_CLKMODHDR </td><td>RF ref clock buffer to clock module header </td></tr>
333<tr>
334<td>CLK_RFREF_OUTSEL_RFAB </td><td>RF ref clock buffer to RF A and B transceivers </td></tr>
335</table>
336</td></tr>
337  </table>
338  </dd>
339</dl>
340<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl>
341
342</div>
343</div>
344<a class="anchor" id="ga0769cba992797225f0e3f8f58d9b6b1a"></a>
345<div class="memitem">
346<div class="memproto">
347      <table class="memname">
348        <tr>
349          <td class="memname">u32 clk_spi_read </td>
350          <td>(</td>
351          <td class="paramtype">u32&#160;</td>
352          <td class="paramname"><em>baseaddr</em>, </td>
353        </tr>
354        <tr>
355          <td class="paramkey"></td>
356          <td></td>
357          <td class="paramtype">u32&#160;</td>
358          <td class="paramname"><em>csMask</em>, </td>
359        </tr>
360        <tr>
361          <td class="paramkey"></td>
362          <td></td>
363          <td class="paramtype">u8&#160;</td>
364          <td class="paramname"><em>regAddr</em>&#160;</td>
365        </tr>
366        <tr>
367          <td></td>
368          <td>)</td>
369          <td></td><td></td>
370        </tr>
371      </table>
372</div><div class="memdoc">
373
374<p>Reads the specified register from both AD9963s. </p>
375<dl class="params"><dt>Parameters</dt><dd>
376  <table class="params">
377    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller_axi pcore </td></tr>
378    <tr><td class="paramname">csMask</td><td>OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS </td></tr>
379    <tr><td class="paramname">regAddr</td><td>Address of register to read, in [0x00, 0x5A] </td></tr>
380  </table>
381  </dd>
382</dl>
383<dl class="section return"><dt>Returns</dt><dd>Returns concatenation of current values of the specified register for both AD9512s (if selected); samp clock buffer is LSB </dd></dl>
384
385</div>
386</div>
387<a class="anchor" id="ga35a167edcce1415775ea854c165408d4"></a>
388<div class="memitem">
389<div class="memproto">
390      <table class="memname">
391        <tr>
392          <td class="memname">void clk_spi_write </td>
393          <td>(</td>
394          <td class="paramtype">u32&#160;</td>
395          <td class="paramname"><em>baseaddr</em>, </td>
396        </tr>
397        <tr>
398          <td class="paramkey"></td>
399          <td></td>
400          <td class="paramtype">u32&#160;</td>
401          <td class="paramname"><em>csMask</em>, </td>
402        </tr>
403        <tr>
404          <td class="paramkey"></td>
405          <td></td>
406          <td class="paramtype">u8&#160;</td>
407          <td class="paramname"><em>regAddr</em>, </td>
408        </tr>
409        <tr>
410          <td class="paramkey"></td>
411          <td></td>
412          <td class="paramtype">u8&#160;</td>
413          <td class="paramname"><em>txByte</em>&#160;</td>
414        </tr>
415        <tr>
416          <td></td>
417          <td>)</td>
418          <td></td><td></td>
419        </tr>
420      </table>
421</div><div class="memdoc">
422
423<p>Writes the specified register value to the selected AD9512 clock buffers. </p>
424<dl class="params"><dt>Parameters</dt><dd>
425  <table class="params">
426    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller_axi pcore </td></tr>
427    <tr><td class="paramname">csMask</td><td>OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS </td></tr>
428    <tr><td class="paramname">regAddr</td><td>Address of register to write, in [0x00, 0x5A] </td></tr>
429    <tr><td class="paramname">txByte</td><td>8-bit value to write </td></tr>
430  </table>
431  </dd>
432</dl>
433
434</div>
435</div>
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440  <ul>
441    <li class="footer">Generated on Fri Jan 30 2015 10:05:57 for w3_clock_controller_axi Driver by doxygen v1.8.8</li>
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