;***************************************************************************************
;RF ref clk buffer (AD9512):
;	CLK1: Input from on-board 80MHz oscillator
;	CLK2: Input from clock module
;	OUT0: LVPECL output to clock module
;	OUT1: Unused LVPECL output (not terminated)
;	OUT2: Unused LVPECL output (not terminated)
;	OUT3: LVCMOS outputs to RFA/RFB MAX2829 (p: RFB, n: RFA)
;	OUT4: LVDS output to FMC slot
;
;	All configs not listed below are handled post-boot by MicroBlaze application
;
;	No Clock Module:
;		Do nothing - all config handled post-boot by MicroBlaze application
;
;	CM-MMCX Configs:
;		A/B/C: Do nothing
;
;	CM-PLL Configs:
;		A: Select CLK1 input (on-board osc), enable OUT0 (output to clock module) as 10MHz full-scale LVPECL
;		B/C: Do nothing
;
;	Relevant registers:
;		45: Selects clock input: 00 for off-board, 01 for on-board
;		4A: 33 sets divider on OUT0 (output to clk mod) to 8, 50% duty cycle
;		4B: 00 enables divider on OUT0 (output to clk mod)
;		3D: 08 configures LVPECL output OUT0 (output to clk mod) for max drive
;		5A: Trigger device update from SPI registers (self-clearing)
;***************************************************************************************
TABLE TBL_CFG_NOCM_RFREF_ADDR#,		[FF]
TABLE TBL_CFG_NOCM_RFREF_DATA#,		[FF]

TABLE TBL_CFG_CMMMCX_A_RFREF_ADDR#,	[FF]
TABLE TBL_CFG_CMMMCX_A_RFREF_DATA#,	[FF]

TABLE TBL_CFG_CMMMCX_B_RFREF_ADDR#,	[FF]
TABLE TBL_CFG_CMMMCX_B_RFREF_DATA#,	[FF]

TABLE TBL_CFG_CMMMCX_C_RFREF_ADDR#,	[FF]
TABLE TBL_CFG_CMMMCX_C_RFREF_DATA#,	[FF]

TABLE TBL_CFG_CMPLL_A_RFREF_ADDR#,	[45, 4A, 4B, 3D, 5A, FF]
TABLE TBL_CFG_CMPLL_A_RFREF_DATA#,	[01, 33, 00, 08, 01, FF]

TABLE TBL_CFG_CMPLL_B_RFREF_ADDR#,	[FF]
TABLE TBL_CFG_CMPLL_B_RFREF_DATA#,	[FF]

TABLE TBL_CFG_CMPLL_C_RFREF_ADDR#,	[FF]
TABLE TBL_CFG_CMPLL_C_RFREF_DATA#,	[FF]

;***************************************************************************************
;Samp clk buffer (AD9512):
;	CLK1: Input from on-board 80MHz oscillator
;	CLK2: Input from clock module
;	OUT0: LVPECL output to RFB AD9963
;	OUT1: LVPECL output to clock module
;	OUT2: LVPECL output to RFA AD9963
;	OUT3: LVDS output to FPGA
;	OUT4: LVDS output to FMC slot
;
;	All configs not listed below are handled post-boot by MicroBlaze application
;
;	No Clock Module:
;		-Select CLK1
;		-Enable OUT3 as 80MHz LVDS
;
;	CM-MMCX Configs:
;		A: Same as No Clock Module
;
;		B/C:	-Select CLK2
;				-Enable OUT3 as 80MHz LVDS
;
;	CM-PLL Configs:
;		A/B/C:	-Select CLK2 (input from clock module)
;				-Enable OUT3 (output to FPGA) as 80MHz LVDS
;
;	Relevant registers:
;		45: Selects clock input: 00 for off-board, 01 for on-board
;		51: 80 bypasses OUT3 divider (output to FPGA)
;		5A: Trigger device update from SPI registers (self-clearing)
;***************************************************************************************/
TABLE TBL_CFG_NOCM_SAMP_ADDR#,		[45, 51, 5A, FF]
TABLE TBL_CFG_NOCM_SAMP_DATA#,		[01, 80, 01, FF]

TABLE TBL_CFG_CMMMCX_A_SAMP_ADDR#,	[45, 51, 5A, FF]
TABLE TBL_CFG_CMMMCX_A_SAMP_DATA#,	[01, 80, 01, FF]

TABLE TBL_CFG_CMMMCX_B_SAMP_ADDR#,	[45, 51, 5A, FF]
TABLE TBL_CFG_CMMMCX_B_SAMP_DATA#,	[00, 80, 01, FF]

TABLE TBL_CFG_CMMMCX_C_SAMP_ADDR#,	[45, 51, 5A, FF]
TABLE TBL_CFG_CMMMCX_C_SAMP_DATA#,	[00, 80, 01, FF]

TABLE TBL_CFG_CMPLL_A_SAMP_ADDR#,	[45, 51, 5A, FF]
TABLE TBL_CFG_CMPLL_A_SAMP_DATA#,	[00, 80, 01, FF]

TABLE TBL_CFG_CMPLL_B_SAMP_ADDR#,	[45, 51, 5A, FF]
TABLE TBL_CFG_CMPLL_B_SAMP_DATA#,	[00, 80, 01, FF]

TABLE TBL_CFG_CMPLL_C_SAMP_ADDR#,	[45, 51, 5A, FF]
TABLE TBL_CFG_CMPLL_C_SAMP_DATA#,	[00, 80, 01, FF]

;***************************************************************************************
;CM-PLL Buffer/PLL (AD9511):
;	CLK1: Input from off-board reference, bypasses PLL
;	CLK2: Input from on-board 80MHz VCXO
;	OUT0/1/2: Unused LVPECL outputs (unterminated)
;	OUT3: LVDS output to clock module header RFCLKBUF pins (rf ref clk buf CLK2 input)
;	OUT4: LVDS output to clock module header SAMPCLKBUF pins (samp clk buf CLK2 input)
;
;	All configs not listed below are handled post-boot by MicroBlaze application
;
;	No Clock Module:
;		Toggle reset, power down PLL core and all outputs
;		This handles the case of the CM-PLL being mounted but its switches being set to 00
;		It's better to do SPI writes to open pins (i.e. no CM) than let the PLL run free
;
;	CM-MMCX Configs:
;		Do nothing - no PLL
;
;	CM-PLL Configs:
;		Common:
;			-Toggle reset
;			-Disable OUT0/1/2 (unused)
;			-Enable OUT4 as 80MHz max-drive LVDS
;
;		A:	-Configure PLL for 10MHz reference (see below)
;			-Disable OUT3 (output to RF ref clk buf)
;
;		B:	-Configure PLL for 10MHz reference (see below)
;			-Enable OUT3 (output to RF ref clk buf)
;
;		C:	-Configure PLL for 80MHz reference (see below)
;			-Enable OUT3 (output to RF ref clk buf)
;
;	Relevant registers:
;		00: 30 resets, 10 un-resets
;		04: A counter b[5:0]
;		05: B counter b[12:8]
;		06: B counter b[7:0]
;		0B: R counter b[13:8]
;		0C: R counter b[7:0]
;		07: 00 disables loss-of-reference state machine
;		08: 47 enables charge pump, sets STATUS=lock_det, sets positive PFD polarity
;		09: 70 sets max charge pump current
;		0A: 08 for normal operation, 10MHz ref; 040 for normal operation, 80MHz ref)
;			b[1:0]: PLL powerdown (00 or 10=normal operation, 01 or 11=powe down)
;			b[4:2]: Prescaler mode (see datasheet for full list)
;				000: FD, div by 1
;				010: DM, (P/P+1)=2/3
;		3D/3E/3F: 03 powers down LVPECL outputs OUT0/1/2
;		40/41: 01 disables OUT3/4, 02 enables LVDS output OUT3/4
;		51/53: 80 disables divider (W3 board wants 80MHz inputs from clk module)
;		45: 02 selects CLK2 (VCXO clk src), powers down CLK1 input, powers up all other I/O
;		5A: Trigger device update from SPI registers (self-clearing)
;
;	Common reference frequency configs:
;		10MHz:
;			PFD freq: 10MHz
;			R divider: 1
;			N divider: 8 (implies DM mode, prescaler mode (2/3), A=2, B=3)
;
;		80MHz:
;			PFD freq: 80MHz
;			R divider: 1
;			N divider: 1 (implies FD mode, prescaler mode div 1, B=1 (bypassed))
;
;		See AD9511 datasheet Table 16 for PLL settings for other valid divider settings
;
;***************************************************************************************/

TABLE TBL_CFG_NOCM_PLL_ADDR#,		[00, 00, 0A, 3D, 3E, 3F, 40, 41, FF]
TABLE TBL_CFG_NOCM_PLL_DATA#,		[30, 10, 11, 03, 03, 03, 01, 01, FF]

TABLE TBL_CFG_CMPLL_A_PLL_ADDR#,	[00, 00, 04, 05, 06, 0B, 0C, 07, 08, 09, 0A, 3D, 3E, 3F, 40, 41, 51, 53, 45, 5A, FF]
TABLE TBL_CFG_CMPLL_A_PLL_DATA#,	[30, 10, 02, 00, 03, 00, 01, 00, 47, 70, 08, 03, 03, 03, 01, 02, 80, 80, 02, 01, FF]

TABLE TBL_CFG_CMPLL_B_PLL_ADDR#,	[00, 00, 04, 05, 06, 0B, 0C, 07, 08, 09, 0A, 3D, 3E, 3F, 40, 41, 51, 53, 45, 5A, FF]
TABLE TBL_CFG_CMPLL_B_PLL_DATA#,	[30, 10, 02, 00, 03, 00, 01, 00, 47, 70, 08, 03, 03, 03, 02, 02, 80, 80, 02, 01, FF]

TABLE TBL_CFG_CMPLL_C_PLL_ADDR#,	[00, 00, 04, 05, 06, 0B, 0C, 07, 08, 09, 0A, 3D, 3E, 3F, 40, 41, 51, 53, 45, 5A, FF]
TABLE TBL_CFG_CMPLL_C_PLL_DATA#,	[30, 10, 02, 00, 03, 00, 01, 00, 47, 70, 40, 03, 03, 03, 02, 02, 80, 80, 02, 01, FF]