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25   <div id="projectname">w3_clock_controller Driver
26   </div>
27   <div id="projectbrief">Driver for WARP v3 AD9512 clock buffer controller core (w3_clock_controller_v3_00_b)</div>
28  </td>
29 </tr>
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57  <div class="summary">
58<a href="#func-members">Functions</a>  </div>
59  <div class="headertitle">
60<div class="title">Functions</div>  </div>
61</div><!--header-->
62<div class="contents">
63<table class="memberdecls">
64<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
65Functions</h2></td></tr>
66<tr class="memitem:ga6a17b6d143e2d820f0c5ae4283496ac7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga6a17b6d143e2d820f0c5ae4283496ac7">clk_init</a> (u32 baseaddr, u8 clkDiv)</td></tr>
67<tr class="separator:ga6a17b6d143e2d820f0c5ae4283496ac7"><td class="memSeparator" colspan="2">&#160;</td></tr>
68<tr class="memitem:ga509f9e41d2bac1b3dbf1541709d1179c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c">clk_config_outputs</a> (u32 baseaddr, u8 clkOutMode, u32 clkOutSel)</td></tr>
69<tr class="separator:ga509f9e41d2bac1b3dbf1541709d1179c"><td class="memSeparator" colspan="2">&#160;</td></tr>
70<tr class="memitem:ga58355f82b91625951cad329e82e3e2a6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga58355f82b91625951cad329e82e3e2a6">clk_config_dividers</a> (u32 baseaddr, u8 clkDiv, u32 clkOutSel)</td></tr>
71<tr class="separator:ga58355f82b91625951cad329e82e3e2a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
72<tr class="memitem:ga0769cba992797225f0e3f8f58d9b6b1a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga0769cba992797225f0e3f8f58d9b6b1a">clk_spi_read</a> (u32 baseaddr, u32 csMask, u8 regAddr)</td></tr>
73<tr class="separator:ga0769cba992797225f0e3f8f58d9b6b1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
74<tr class="memitem:ga35a167edcce1415775ea854c165408d4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga35a167edcce1415775ea854c165408d4">clk_spi_write</a> (u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte)</td></tr>
75<tr class="separator:ga35a167edcce1415775ea854c165408d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
76</table>
77<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
78<p>Example: </p>
79<div class="fragment"><div class="line"><span class="comment">//Assumes user code sets CLK_BASEADDR to base address of w3_clock_controller core, as set in xparameters.h</span></div>
80<div class="line"></div>
81<div class="line"><span class="comment">//Initialize the AD9512 clock buffers</span></div>
82<div class="line">ad_init(CLK_BASEADDR, 3);</div>
83<div class="line"></div>
84<div class="line"><span class="comment">//Enable clock outputs to FMC slot</span></div>
85<div class="line"><a class="code" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c" title="Configures which outputs are en/disabled in both AD9512 clock buffers.">clk_config_outputs</a>(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC | CLK_RFREF_OUTSEL_FMC));</div>
86<div class="line"></div>
87<div class="line"><span class="comment">//Disable clock outputs to clock module header</span></div>
88<div class="line"><a class="code" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c" title="Configures which outputs are en/disabled in both AD9512 clock buffers.">clk_config_outputs</a>(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));</div>
89<div class="line"></div>
90<div class="line"><span class="comment">//Set clock to AD chips to 40MHz (80MHz source divided by 2)</span></div>
91<div class="line"><a class="code" href="group__user__functions.html#ga58355f82b91625951cad329e82e3e2a6" title="Configures output dividers in both AD9512 clock buffers.">clk_config_dividers</a>(CLK_BASEADDR, 2, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));</div>
92</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
93<a class="anchor" id="ga6a17b6d143e2d820f0c5ae4283496ac7"></a>
94<div class="memitem">
95<div class="memproto">
96      <table class="memname">
97        <tr>
98          <td class="memname">int clk_init </td>
99          <td>(</td>
100          <td class="paramtype">u32&#160;</td>
101          <td class="paramname"><em>baseaddr</em>, </td>
102        </tr>
103        <tr>
104          <td class="paramkey"></td>
105          <td></td>
106          <td class="paramtype">u8&#160;</td>
107          <td class="paramname"><em>clkDiv</em>&#160;</td>
108        </tr>
109        <tr>
110          <td></td>
111          <td>)</td>
112          <td></td><td></td>
113        </tr>
114      </table>
115</div><div class="memdoc">
116
117<p>Initializes the clock controller. This function must be called once at boot before any AD or RF operations will work. Default config is: </p>
118<ul>
119<li>On board 80MHz TCXO used as source for sampling and RF ref clock buffers</li>
120<li>80MHz clock driven to FPGA, RF A and RF B ADC/DACs</li>
121<li>40MHz clock driven to RF A and B transceivers</li>
122<li>FMC and clock module header clocks disabled <dl class="params"><dt>Parameters</dt><dd>
123  <table class="params">
124    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
125    <tr><td class="paramname">clkDiv</td><td>Clock divider for SPI serial clock (set to 3 for 160MHz bus) </td></tr>
126  </table>
127  </dd>
128</dl>
129</li>
130</ul>
131
132</div>
133</div>
134<a class="anchor" id="ga509f9e41d2bac1b3dbf1541709d1179c"></a>
135<div class="memitem">
136<div class="memproto">
137      <table class="memname">
138        <tr>
139          <td class="memname">int clk_config_outputs </td>
140          <td>(</td>
141          <td class="paramtype">u32&#160;</td>
142          <td class="paramname"><em>baseaddr</em>, </td>
143        </tr>
144        <tr>
145          <td class="paramkey"></td>
146          <td></td>
147          <td class="paramtype">u8&#160;</td>
148          <td class="paramname"><em>clkOutMode</em>, </td>
149        </tr>
150        <tr>
151          <td class="paramkey"></td>
152          <td></td>
153          <td class="paramtype">u32&#160;</td>
154          <td class="paramname"><em>clkOutSel</em>&#160;</td>
155        </tr>
156        <tr>
157          <td></td>
158          <td>)</td>
159          <td></td><td></td>
160        </tr>
161      </table>
162</div><div class="memdoc">
163
164<p>Configures which outputs are en/disabled in both AD9512 clock buffers. </p>
165<dl class="params"><dt>Parameters</dt><dd>
166  <table class="params">
167    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
168    <tr><td class="paramname">clkOutMode</td><td>New mode for selected clock outputs; must be CLK_OUTPUT_ON or CLK_OUTPUT_OFF </td></tr>
169    <tr><td class="paramname">clkOutSel</td><td>Masks to select which clock outputs to affect; must be OR'd combination of: <table class="doxtable">
170<tr>
171<th>Mask </th><th>Selected Output</th></tr>
172<tr>
173<td>CLK_SAMP_OUTSEL_FMC </td><td>Sampling clock buffer to FMC slot </td></tr>
174<tr>
175<td>CLK_SAMP_OUTSEL_CLKMODHDR </td><td>Sampling clock buffer to clock module header </td></tr>
176<tr>
177<td>CLK_SAMP_OUTSEL_FPGA </td><td>Sampling clock buffer to FPGA </td></tr>
178<tr>
179<td>CLK_SAMP_OUTSEL_AD_RFA </td><td>Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) </td></tr>
180<tr>
181<td>CLK_SAMP_OUTSEL_AD_RFB </td><td>Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) </td></tr>
182<tr>
183<td>CLK_RFREF_OUTSEL_FMC </td><td>RF ref clock buffer to FMC </td></tr>
184<tr>
185<td>CLK_RFREF_OUTSEL_CLKMODHDR </td><td>RF ref clock buffer to clock module header </td></tr>
186<tr>
187<td>CLK_RFREF_OUTSEL_RFAB </td><td>RF ref clock buffer to RF A and B transceivers </td></tr>
188</table>
189</td></tr>
190  </table>
191  </dd>
192</dl>
193<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl>
194
195</div>
196</div>
197<a class="anchor" id="ga58355f82b91625951cad329e82e3e2a6"></a>
198<div class="memitem">
199<div class="memproto">
200      <table class="memname">
201        <tr>
202          <td class="memname">int clk_config_dividers </td>
203          <td>(</td>
204          <td class="paramtype">u32&#160;</td>
205          <td class="paramname"><em>baseaddr</em>, </td>
206        </tr>
207        <tr>
208          <td class="paramkey"></td>
209          <td></td>
210          <td class="paramtype">u8&#160;</td>
211          <td class="paramname"><em>clkDiv</em>, </td>
212        </tr>
213        <tr>
214          <td class="paramkey"></td>
215          <td></td>
216          <td class="paramtype">u32&#160;</td>
217          <td class="paramname"><em>clkOutSel</em>&#160;</td>
218        </tr>
219        <tr>
220          <td></td>
221          <td>)</td>
222          <td></td><td></td>
223        </tr>
224      </table>
225</div><div class="memdoc">
226
227<p>Configures output dividers in both AD9512 clock buffers. </p>
228<dl class="params"><dt>Parameters</dt><dd>
229  <table class="params">
230    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
231    <tr><td class="paramname">clkDiv</td><td>Divider value to set; must be 1 or even integer in [2,32] </td></tr>
232    <tr><td class="paramname">clkOutSel</td><td>Masks to select which clock outputs to affect; must be OR'd combination of: <table class="doxtable">
233<tr>
234<th>Mask </th><th>Selected Output</th></tr>
235<tr>
236<td>CLK_SAMP_OUTSEL_FMC </td><td>Sampling clock buffer to FMC slot </td></tr>
237<tr>
238<td>CLK_SAMP_OUTSEL_CLKMODHDR </td><td>Sampling clock buffer to clock module header </td></tr>
239<tr>
240<td>CLK_SAMP_OUTSEL_FPGA </td><td>Sampling clock buffer to FPGA </td></tr>
241<tr>
242<td>CLK_SAMP_OUTSEL_AD_RFA </td><td>Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) </td></tr>
243<tr>
244<td>CLK_SAMP_OUTSEL_AD_RFB </td><td>Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) </td></tr>
245<tr>
246<td>CLK_RFREF_OUTSEL_FMC </td><td>RF ref clock buffer to FMC </td></tr>
247<tr>
248<td>CLK_RFREF_OUTSEL_CLKMODHDR </td><td>RF ref clock buffer to clock module header </td></tr>
249<tr>
250<td>CLK_RFREF_OUTSEL_RFAB </td><td>RF ref clock buffer to RF A and B transceivers </td></tr>
251</table>
252</td></tr>
253  </table>
254  </dd>
255</dl>
256<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl>
257
258</div>
259</div>
260<a class="anchor" id="ga0769cba992797225f0e3f8f58d9b6b1a"></a>
261<div class="memitem">
262<div class="memproto">
263      <table class="memname">
264        <tr>
265          <td class="memname">u32 clk_spi_read </td>
266          <td>(</td>
267          <td class="paramtype">u32&#160;</td>
268          <td class="paramname"><em>baseaddr</em>, </td>
269        </tr>
270        <tr>
271          <td class="paramkey"></td>
272          <td></td>
273          <td class="paramtype">u32&#160;</td>
274          <td class="paramname"><em>csMask</em>, </td>
275        </tr>
276        <tr>
277          <td class="paramkey"></td>
278          <td></td>
279          <td class="paramtype">u8&#160;</td>
280          <td class="paramname"><em>regAddr</em>&#160;</td>
281        </tr>
282        <tr>
283          <td></td>
284          <td>)</td>
285          <td></td><td></td>
286        </tr>
287      </table>
288</div><div class="memdoc">
289
290<p>Reads the specified register from both AD9963s. </p>
291<dl class="params"><dt>Parameters</dt><dd>
292  <table class="params">
293    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
294    <tr><td class="paramname">csMask</td><td>OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS </td></tr>
295    <tr><td class="paramname">regAddr</td><td>Address of register to read, in [0x00, 0x5A] </td></tr>
296  </table>
297  </dd>
298</dl>
299<dl class="section return"><dt>Returns</dt><dd>Returns concatenation of current values of the specified register for both AD9512s (if selected); samp clock buffer is LSB </dd></dl>
300
301</div>
302</div>
303<a class="anchor" id="ga35a167edcce1415775ea854c165408d4"></a>
304<div class="memitem">
305<div class="memproto">
306      <table class="memname">
307        <tr>
308          <td class="memname">void clk_spi_write </td>
309          <td>(</td>
310          <td class="paramtype">u32&#160;</td>
311          <td class="paramname"><em>baseaddr</em>, </td>
312        </tr>
313        <tr>
314          <td class="paramkey"></td>
315          <td></td>
316          <td class="paramtype">u32&#160;</td>
317          <td class="paramname"><em>csMask</em>, </td>
318        </tr>
319        <tr>
320          <td class="paramkey"></td>
321          <td></td>
322          <td class="paramtype">u8&#160;</td>
323          <td class="paramname"><em>regAddr</em>, </td>
324        </tr>
325        <tr>
326          <td class="paramkey"></td>
327          <td></td>
328          <td class="paramtype">u8&#160;</td>
329          <td class="paramname"><em>txByte</em>&#160;</td>
330        </tr>
331        <tr>
332          <td></td>
333          <td>)</td>
334          <td></td><td></td>
335        </tr>
336      </table>
337</div><div class="memdoc">
338
339<p>Writes the specified register value to the selected AD9512 clock buffers. </p>
340<dl class="params"><dt>Parameters</dt><dd>
341  <table class="params">
342    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
343    <tr><td class="paramname">csMask</td><td>OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS </td></tr>
344    <tr><td class="paramname">regAddr</td><td>Address of register to write, in [0x00, 0x5A] </td></tr>
345    <tr><td class="paramname">txByte</td><td>8-bit value to write </td></tr>
346  </table>
347  </dd>
348</dl>
349
350</div>
351</div>
352</div><!-- contents -->
353</div><!-- doc-content -->
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356  <ul>
357    <li class="footer">Generated on Sun Aug 19 2012 21:58:59 for w3_clock_controller Driver by doxygen v1.8.2</li>
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