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25 | <div id="projectname">w3_clock_controller Driver |
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26 | </div> |
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27 | <div id="projectbrief">Driver for WARP v3 AD9512 clock buffer controller core (w3_clock_controller_v3_00_b)</div> |
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28 | </td> |
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58 | <a href="#func-members">Functions</a> </div> |
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59 | <div class="headertitle"> |
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60 | <div class="title">Functions</div> </div> |
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61 | </div><!--header--> |
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62 | <div class="contents"> |
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63 | <table class="memberdecls"> |
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64 | <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> |
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65 | Functions</h2></td></tr> |
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66 | <tr class="memitem:ga6a17b6d143e2d820f0c5ae4283496ac7"><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga6a17b6d143e2d820f0c5ae4283496ac7">clk_init</a> (u32 baseaddr, u8 clkDiv)</td></tr> |
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67 | <tr class="separator:ga6a17b6d143e2d820f0c5ae4283496ac7"><td class="memSeparator" colspan="2"> </td></tr> |
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68 | <tr class="memitem:ga509f9e41d2bac1b3dbf1541709d1179c"><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c">clk_config_outputs</a> (u32 baseaddr, u8 clkOutMode, u32 clkOutSel)</td></tr> |
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69 | <tr class="separator:ga509f9e41d2bac1b3dbf1541709d1179c"><td class="memSeparator" colspan="2"> </td></tr> |
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70 | <tr class="memitem:ga58355f82b91625951cad329e82e3e2a6"><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga58355f82b91625951cad329e82e3e2a6">clk_config_dividers</a> (u32 baseaddr, u8 clkDiv, u32 clkOutSel)</td></tr> |
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71 | <tr class="separator:ga58355f82b91625951cad329e82e3e2a6"><td class="memSeparator" colspan="2"> </td></tr> |
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72 | <tr class="memitem:ga0769cba992797225f0e3f8f58d9b6b1a"><td class="memItemLeft" align="right" valign="top">u32 </td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga0769cba992797225f0e3f8f58d9b6b1a">clk_spi_read</a> (u32 baseaddr, u32 csMask, u8 regAddr)</td></tr> |
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73 | <tr class="separator:ga0769cba992797225f0e3f8f58d9b6b1a"><td class="memSeparator" colspan="2"> </td></tr> |
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74 | <tr class="memitem:ga35a167edcce1415775ea854c165408d4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga35a167edcce1415775ea854c165408d4">clk_spi_write</a> (u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte)</td></tr> |
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75 | <tr class="separator:ga35a167edcce1415775ea854c165408d4"><td class="memSeparator" colspan="2"> </td></tr> |
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76 | </table> |
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77 | <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> |
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78 | <p>Example: </p> |
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79 | <div class="fragment"><div class="line"><span class="comment">//Assumes user code sets CLK_BASEADDR to base address of w3_clock_controller core, as set in xparameters.h</span></div> |
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80 | <div class="line"></div> |
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81 | <div class="line"><span class="comment">//Initialize the AD9512 clock buffers</span></div> |
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82 | <div class="line">ad_init(CLK_BASEADDR, 3);</div> |
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83 | <div class="line"></div> |
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84 | <div class="line"><span class="comment">//Enable clock outputs to FMC slot</span></div> |
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85 | <div class="line"><a class="code" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c" title="Configures which outputs are en/disabled in both AD9512 clock buffers.">clk_config_outputs</a>(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC | CLK_RFREF_OUTSEL_FMC));</div> |
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86 | <div class="line"></div> |
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87 | <div class="line"><span class="comment">//Disable clock outputs to clock module header</span></div> |
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88 | <div class="line"><a class="code" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c" title="Configures which outputs are en/disabled in both AD9512 clock buffers.">clk_config_outputs</a>(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));</div> |
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89 | <div class="line"></div> |
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90 | <div class="line"><span class="comment">//Set clock to AD chips to 40MHz (80MHz source divided by 2)</span></div> |
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91 | <div class="line"><a class="code" href="group__user__functions.html#ga58355f82b91625951cad329e82e3e2a6" title="Configures output dividers in both AD9512 clock buffers.">clk_config_dividers</a>(CLK_BASEADDR, 2, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));</div> |
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92 | </div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2> |
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93 | <a class="anchor" id="ga6a17b6d143e2d820f0c5ae4283496ac7"></a> |
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94 | <div class="memitem"> |
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95 | <div class="memproto"> |
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96 | <table class="memname"> |
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97 | <tr> |
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98 | <td class="memname">int clk_init </td> |
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99 | <td>(</td> |
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100 | <td class="paramtype">u32 </td> |
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101 | <td class="paramname"><em>baseaddr</em>, </td> |
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102 | </tr> |
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103 | <tr> |
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104 | <td class="paramkey"></td> |
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105 | <td></td> |
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106 | <td class="paramtype">u8 </td> |
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107 | <td class="paramname"><em>clkDiv</em> </td> |
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108 | </tr> |
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109 | <tr> |
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110 | <td></td> |
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111 | <td>)</td> |
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112 | <td></td><td></td> |
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113 | </tr> |
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114 | </table> |
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115 | </div><div class="memdoc"> |
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116 | |
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117 | <p>Initializes the clock controller. This function must be called once at boot before any AD or RF operations will work. Default config is: </p> |
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118 | <ul> |
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119 | <li>On board 80MHz TCXO used as source for sampling and RF ref clock buffers</li> |
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120 | <li>80MHz clock driven to FPGA, RF A and RF B ADC/DACs</li> |
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121 | <li>40MHz clock driven to RF A and B transceivers</li> |
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122 | <li>FMC and clock module header clocks disabled <dl class="params"><dt>Parameters</dt><dd> |
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123 | <table class="params"> |
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124 | <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr> |
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125 | <tr><td class="paramname">clkDiv</td><td>Clock divider for SPI serial clock (set to 3 for 160MHz bus) </td></tr> |
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126 | </table> |
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127 | </dd> |
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128 | </dl> |
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129 | </li> |
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130 | </ul> |
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131 | |
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132 | </div> |
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133 | </div> |
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134 | <a class="anchor" id="ga509f9e41d2bac1b3dbf1541709d1179c"></a> |
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135 | <div class="memitem"> |
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136 | <div class="memproto"> |
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137 | <table class="memname"> |
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138 | <tr> |
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139 | <td class="memname">int clk_config_outputs </td> |
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140 | <td>(</td> |
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141 | <td class="paramtype">u32 </td> |
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142 | <td class="paramname"><em>baseaddr</em>, </td> |
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143 | </tr> |
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144 | <tr> |
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145 | <td class="paramkey"></td> |
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146 | <td></td> |
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147 | <td class="paramtype">u8 </td> |
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148 | <td class="paramname"><em>clkOutMode</em>, </td> |
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149 | </tr> |
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150 | <tr> |
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151 | <td class="paramkey"></td> |
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152 | <td></td> |
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153 | <td class="paramtype">u32 </td> |
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154 | <td class="paramname"><em>clkOutSel</em> </td> |
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155 | </tr> |
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156 | <tr> |
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157 | <td></td> |
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158 | <td>)</td> |
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159 | <td></td><td></td> |
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160 | </tr> |
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161 | </table> |
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162 | </div><div class="memdoc"> |
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163 | |
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164 | <p>Configures which outputs are en/disabled in both AD9512 clock buffers. </p> |
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165 | <dl class="params"><dt>Parameters</dt><dd> |
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166 | <table class="params"> |
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167 | <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr> |
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168 | <tr><td class="paramname">clkOutMode</td><td>New mode for selected clock outputs; must be CLK_OUTPUT_ON or CLK_OUTPUT_OFF </td></tr> |
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169 | <tr><td class="paramname">clkOutSel</td><td>Masks to select which clock outputs to affect; must be OR'd combination of: <table class="doxtable"> |
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170 | <tr> |
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171 | <th>Mask </th><th>Selected Output</th></tr> |
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172 | <tr> |
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173 | <td>CLK_SAMP_OUTSEL_FMC </td><td>Sampling clock buffer to FMC slot </td></tr> |
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174 | <tr> |
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175 | <td>CLK_SAMP_OUTSEL_CLKMODHDR </td><td>Sampling clock buffer to clock module header </td></tr> |
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176 | <tr> |
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177 | <td>CLK_SAMP_OUTSEL_FPGA </td><td>Sampling clock buffer to FPGA </td></tr> |
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178 | <tr> |
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179 | <td>CLK_SAMP_OUTSEL_AD_RFA </td><td>Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) </td></tr> |
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180 | <tr> |
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181 | <td>CLK_SAMP_OUTSEL_AD_RFB </td><td>Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) </td></tr> |
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182 | <tr> |
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183 | <td>CLK_RFREF_OUTSEL_FMC </td><td>RF ref clock buffer to FMC </td></tr> |
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184 | <tr> |
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185 | <td>CLK_RFREF_OUTSEL_CLKMODHDR </td><td>RF ref clock buffer to clock module header </td></tr> |
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186 | <tr> |
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187 | <td>CLK_RFREF_OUTSEL_RFAB </td><td>RF ref clock buffer to RF A and B transceivers </td></tr> |
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188 | </table> |
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189 | </td></tr> |
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190 | </table> |
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191 | </dd> |
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192 | </dl> |
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193 | <dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl> |
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194 | |
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195 | </div> |
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196 | </div> |
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197 | <a class="anchor" id="ga58355f82b91625951cad329e82e3e2a6"></a> |
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198 | <div class="memitem"> |
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199 | <div class="memproto"> |
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200 | <table class="memname"> |
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201 | <tr> |
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202 | <td class="memname">int clk_config_dividers </td> |
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203 | <td>(</td> |
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204 | <td class="paramtype">u32 </td> |
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205 | <td class="paramname"><em>baseaddr</em>, </td> |
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206 | </tr> |
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207 | <tr> |
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208 | <td class="paramkey"></td> |
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209 | <td></td> |
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210 | <td class="paramtype">u8 </td> |
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211 | <td class="paramname"><em>clkDiv</em>, </td> |
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212 | </tr> |
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213 | <tr> |
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214 | <td class="paramkey"></td> |
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215 | <td></td> |
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216 | <td class="paramtype">u32 </td> |
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217 | <td class="paramname"><em>clkOutSel</em> </td> |
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218 | </tr> |
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219 | <tr> |
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220 | <td></td> |
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221 | <td>)</td> |
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222 | <td></td><td></td> |
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223 | </tr> |
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224 | </table> |
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225 | </div><div class="memdoc"> |
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226 | |
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227 | <p>Configures output dividers in both AD9512 clock buffers. </p> |
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228 | <dl class="params"><dt>Parameters</dt><dd> |
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229 | <table class="params"> |
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230 | <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr> |
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231 | <tr><td class="paramname">clkDiv</td><td>Divider value to set; must be 1 or even integer in [2,32] </td></tr> |
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232 | <tr><td class="paramname">clkOutSel</td><td>Masks to select which clock outputs to affect; must be OR'd combination of: <table class="doxtable"> |
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233 | <tr> |
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234 | <th>Mask </th><th>Selected Output</th></tr> |
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235 | <tr> |
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236 | <td>CLK_SAMP_OUTSEL_FMC </td><td>Sampling clock buffer to FMC slot </td></tr> |
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237 | <tr> |
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238 | <td>CLK_SAMP_OUTSEL_CLKMODHDR </td><td>Sampling clock buffer to clock module header </td></tr> |
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239 | <tr> |
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240 | <td>CLK_SAMP_OUTSEL_FPGA </td><td>Sampling clock buffer to FPGA </td></tr> |
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241 | <tr> |
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242 | <td>CLK_SAMP_OUTSEL_AD_RFA </td><td>Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) </td></tr> |
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243 | <tr> |
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244 | <td>CLK_SAMP_OUTSEL_AD_RFB </td><td>Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) </td></tr> |
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245 | <tr> |
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246 | <td>CLK_RFREF_OUTSEL_FMC </td><td>RF ref clock buffer to FMC </td></tr> |
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247 | <tr> |
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248 | <td>CLK_RFREF_OUTSEL_CLKMODHDR </td><td>RF ref clock buffer to clock module header </td></tr> |
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249 | <tr> |
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250 | <td>CLK_RFREF_OUTSEL_RFAB </td><td>RF ref clock buffer to RF A and B transceivers </td></tr> |
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251 | </table> |
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252 | </td></tr> |
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253 | </table> |
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254 | </dd> |
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255 | </dl> |
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256 | <dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl> |
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257 | |
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258 | </div> |
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259 | </div> |
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260 | <a class="anchor" id="ga0769cba992797225f0e3f8f58d9b6b1a"></a> |
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261 | <div class="memitem"> |
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262 | <div class="memproto"> |
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263 | <table class="memname"> |
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264 | <tr> |
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265 | <td class="memname">u32 clk_spi_read </td> |
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266 | <td>(</td> |
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267 | <td class="paramtype">u32 </td> |
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268 | <td class="paramname"><em>baseaddr</em>, </td> |
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269 | </tr> |
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270 | <tr> |
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271 | <td class="paramkey"></td> |
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272 | <td></td> |
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273 | <td class="paramtype">u32 </td> |
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274 | <td class="paramname"><em>csMask</em>, </td> |
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275 | </tr> |
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276 | <tr> |
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277 | <td class="paramkey"></td> |
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278 | <td></td> |
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279 | <td class="paramtype">u8 </td> |
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280 | <td class="paramname"><em>regAddr</em> </td> |
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281 | </tr> |
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282 | <tr> |
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283 | <td></td> |
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284 | <td>)</td> |
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285 | <td></td><td></td> |
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286 | </tr> |
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287 | </table> |
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288 | </div><div class="memdoc"> |
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289 | |
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290 | <p>Reads the specified register from both AD9963s. </p> |
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291 | <dl class="params"><dt>Parameters</dt><dd> |
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292 | <table class="params"> |
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293 | <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr> |
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294 | <tr><td class="paramname">csMask</td><td>OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS </td></tr> |
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295 | <tr><td class="paramname">regAddr</td><td>Address of register to read, in [0x00, 0x5A] </td></tr> |
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296 | </table> |
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297 | </dd> |
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298 | </dl> |
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299 | <dl class="section return"><dt>Returns</dt><dd>Returns concatenation of current values of the specified register for both AD9512s (if selected); samp clock buffer is LSB </dd></dl> |
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300 | |
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301 | </div> |
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302 | </div> |
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303 | <a class="anchor" id="ga35a167edcce1415775ea854c165408d4"></a> |
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304 | <div class="memitem"> |
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305 | <div class="memproto"> |
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306 | <table class="memname"> |
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307 | <tr> |
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308 | <td class="memname">void clk_spi_write </td> |
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309 | <td>(</td> |
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310 | <td class="paramtype">u32 </td> |
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311 | <td class="paramname"><em>baseaddr</em>, </td> |
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312 | </tr> |
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313 | <tr> |
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314 | <td class="paramkey"></td> |
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315 | <td></td> |
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316 | <td class="paramtype">u32 </td> |
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317 | <td class="paramname"><em>csMask</em>, </td> |
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318 | </tr> |
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319 | <tr> |
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320 | <td class="paramkey"></td> |
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321 | <td></td> |
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322 | <td class="paramtype">u8 </td> |
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323 | <td class="paramname"><em>regAddr</em>, </td> |
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324 | </tr> |
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325 | <tr> |
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326 | <td class="paramkey"></td> |
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327 | <td></td> |
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328 | <td class="paramtype">u8 </td> |
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329 | <td class="paramname"><em>txByte</em> </td> |
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330 | </tr> |
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331 | <tr> |
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332 | <td></td> |
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333 | <td>)</td> |
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334 | <td></td><td></td> |
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335 | </tr> |
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336 | </table> |
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337 | </div><div class="memdoc"> |
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338 | |
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339 | <p>Writes the specified register value to the selected AD9512 clock buffers. </p> |
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340 | <dl class="params"><dt>Parameters</dt><dd> |
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341 | <table class="params"> |
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342 | <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr> |
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343 | <tr><td class="paramname">csMask</td><td>OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS </td></tr> |
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344 | <tr><td class="paramname">regAddr</td><td>Address of register to write, in [0x00, 0x5A] </td></tr> |
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345 | <tr><td class="paramname">txByte</td><td>8-bit value to write </td></tr> |
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346 | </table> |
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347 | </dd> |
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348 | </dl> |
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349 | |
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350 | </div> |
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351 | </div> |
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352 | </div><!-- contents --> |
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353 | </div><!-- doc-content --> |
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354 | <!-- start footer part --> |
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355 | <div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> |
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356 | <ul> |
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357 | <li class="footer">Generated on Sun Aug 19 2012 21:58:59 for w3_clock_controller Driver by doxygen v1.8.2</li> |
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358 | </ul> |
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361 | </html> |
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