[1766] | 1 | //---------------------------------------------------------------------------- |
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| 2 | // user_logic.vhd - module |
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| 3 | //---------------------------------------------------------------------------- |
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| 4 | // |
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| 5 | // *************************************************************************** |
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| 6 | // ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. ** |
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| 7 | // ** ** |
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| 8 | // ** Xilinx, Inc. ** |
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| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
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| 22 | // ** ** |
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| 23 | // *************************************************************************** |
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| 24 | // |
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| 25 | //---------------------------------------------------------------------------- |
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| 26 | // Filename: user_logic.vhd |
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| 27 | // Version: 3.00.a |
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| 28 | // Description: User logic module. |
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| 29 | // Date: Mon May 14 12:21:28 2012 (by Create and Import Peripheral Wizard) |
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| 30 | // Verilog Standard: Verilog-2001 |
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| 31 | //---------------------------------------------------------------------------- |
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| 32 | // Naming Conventions: |
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| 33 | // active low signals: "*_n" |
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| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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| 35 | // reset signals: "rst", "rst_n" |
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| 36 | // generics: "C_*" |
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| 37 | // user defined types: "*_TYPE" |
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| 38 | // state machine next state: "*_ns" |
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| 39 | // state machine current state: "*_cs" |
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| 40 | // combinatorial signals: "*_com" |
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| 41 | // pipelined or register delay signals: "*_d#" |
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| 42 | // counter signals: "*cnt*" |
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| 43 | // clock enable signals: "*_ce" |
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| 44 | // internal version of output port: "*_i" |
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| 45 | // device pins: "*_pin" |
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| 46 | // ports: "- Names begin with Uppercase" |
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| 47 | // processes: "*_PROCESS" |
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| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 49 | //---------------------------------------------------------------------------- |
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| 50 | |
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| 51 | module user_logic |
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| 52 | ( |
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| 53 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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| 54 | |
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| 55 | samp_spi_sclk, |
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| 56 | samp_spi_mosi, |
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| 57 | samp_spi_miso, |
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| 58 | samp_spi_cs_n, |
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| 59 | samp_func, |
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| 60 | |
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| 61 | rfref_spi_sclk, |
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| 62 | rfref_spi_mosi, |
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| 63 | rfref_spi_miso, |
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| 64 | rfref_spi_cs_n, |
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| 65 | rfref_func, |
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| 66 | |
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| 67 | usr_reset0, |
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| 68 | usr_reset1, |
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| 69 | usr_reset2, |
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| 70 | usr_reset3, |
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| 71 | |
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| 72 | usr_status, |
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| 73 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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| 74 | |
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| 75 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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| 76 | // -- Bus protocol ports, do not add to or delete |
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| 77 | Bus2IP_Clk, // Bus to IP clock |
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| 78 | Bus2IP_Reset, // Bus to IP reset |
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| 79 | Bus2IP_Data, // Bus to IP data bus |
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| 80 | Bus2IP_BE, // Bus to IP byte enables |
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| 81 | Bus2IP_RdCE, // Bus to IP read chip enable |
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| 82 | Bus2IP_WrCE, // Bus to IP write chip enable |
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| 83 | IP2Bus_Data, // IP to Bus data bus |
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| 84 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
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| 85 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
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| 86 | IP2Bus_Error // IP to Bus error response |
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| 87 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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| 88 | ); // user_logic |
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| 89 | |
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| 90 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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| 91 | // --USER parameters added here |
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| 92 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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| 93 | |
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| 94 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 95 | // -- Bus protocol parameters, do not add to or delete |
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| 96 | parameter C_SLV_DWIDTH = 32; |
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| 97 | parameter C_NUM_REG = 8; |
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| 98 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 99 | |
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| 100 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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| 101 | |
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| 102 | output samp_spi_sclk; |
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| 103 | output samp_spi_mosi; |
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| 104 | input samp_spi_miso; |
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| 105 | output samp_spi_cs_n; |
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| 106 | output samp_func; |
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| 107 | |
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| 108 | output rfref_spi_sclk; |
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| 109 | output rfref_spi_mosi; |
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| 110 | input rfref_spi_miso; |
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| 111 | output rfref_spi_cs_n; |
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| 112 | output rfref_func; |
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| 113 | |
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| 114 | output usr_reset0; |
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| 115 | output usr_reset1; |
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| 116 | output usr_reset2; |
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| 117 | output usr_reset3; |
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| 118 | |
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| 119 | input [0:31] usr_status; |
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| 120 | |
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| 121 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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| 122 | |
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| 123 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 124 | // -- Bus protocol ports, do not add to or delete |
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| 125 | input Bus2IP_Clk; |
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| 126 | input Bus2IP_Reset; |
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| 127 | input [0 : C_SLV_DWIDTH-1] Bus2IP_Data; |
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| 128 | input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE; |
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| 129 | input [0 : C_NUM_REG-1] Bus2IP_RdCE; |
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| 130 | input [0 : C_NUM_REG-1] Bus2IP_WrCE; |
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| 131 | output [0 : C_SLV_DWIDTH-1] IP2Bus_Data; |
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| 132 | output IP2Bus_RdAck; |
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| 133 | output IP2Bus_WrAck; |
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| 134 | output IP2Bus_Error; |
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| 135 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 136 | |
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| 137 | //---------------------------------------------------------------------------- |
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| 138 | // Implementation |
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| 139 | //---------------------------------------------------------------------------- |
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| 140 | |
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| 141 | // --USER nets declarations added here, as needed for user logic |
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| 142 | |
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| 143 | // Nets for user logic slave model s/w accessible register example |
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| 144 | reg [0 : C_SLV_DWIDTH-1] slv_reg0; |
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| 145 | reg [0 : C_SLV_DWIDTH-1] slv_reg1; |
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| 146 | reg [0 : C_SLV_DWIDTH-1] slv_reg2; |
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| 147 | reg [0 : C_SLV_DWIDTH-1] slv_reg3; |
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| 148 | reg [0 : C_SLV_DWIDTH-1] slv_reg4; |
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| 149 | reg [0 : C_SLV_DWIDTH-1] slv_reg5; |
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| 150 | reg [0 : C_SLV_DWIDTH-1] slv_reg6; |
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| 151 | reg [0 : C_SLV_DWIDTH-1] slv_reg7; |
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| 152 | wire [0 : 7] slv_reg_write_sel; |
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| 153 | wire [0 : 7] slv_reg_read_sel; |
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| 154 | reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data; |
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| 155 | wire slv_read_ack; |
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| 156 | wire slv_write_ack; |
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| 157 | integer byte_index, bit_index; |
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| 158 | |
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| 159 | // --USER logic implementation added here |
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| 160 | |
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| 161 | // ------------------------------------------------------ |
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| 162 | // Example code to read/write user logic slave model s/w accessible registers |
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| 163 | // |
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| 164 | // Note: |
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| 165 | // The example code presented here is to show you one way of reading/writing |
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| 166 | // software accessible registers implemented in the user logic slave model. |
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| 167 | // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond |
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| 168 | // to one software accessible register by the top level template. For example, |
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| 169 | // if you have four 32 bit software accessible registers in the user logic, |
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| 170 | // you are basically operating on the following memory mapped registers: |
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| 171 | // |
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| 172 | // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register |
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| 173 | // "1000" C_BASEADDR + 0x0 |
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| 174 | // "0100" C_BASEADDR + 0x4 |
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| 175 | // "0010" C_BASEADDR + 0x8 |
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| 176 | // "0001" C_BASEADDR + 0xC |
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| 177 | // |
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| 178 | // ------------------------------------------------------ |
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| 179 | |
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| 180 | assign slv_reg_write_sel = Bus2IP_WrCE[0:7]; |
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| 181 | assign slv_reg_read_sel = Bus2IP_RdCE[0:7]; |
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| 182 | |
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| 183 | //Removed [1] from _ack list, so ack can be delayed following write to SPI Tx register |
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| 184 | assign slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7]; |
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| 185 | assign slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7]; |
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| 186 | |
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| 187 | // implement slave model register(s) |
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| 188 | always @( posedge Bus2IP_Clk ) |
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| 189 | begin: SLAVE_REG_WRITE_PROC |
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| 190 | |
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| 191 | if ( Bus2IP_Reset == 1 ) |
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| 192 | begin |
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| 193 | slv_reg0 <= 0; |
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| 194 | slv_reg1 <= 0; |
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| 195 | slv_reg2 <= 0; |
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| 196 | slv_reg3 <= 0; |
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| 197 | slv_reg4 <= 0; |
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| 198 | slv_reg5 <= 0; |
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| 199 | slv_reg6 <= 0; |
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| 200 | slv_reg7 <= 0; |
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| 201 | end |
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| 202 | else |
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| 203 | case ( slv_reg_write_sel ) |
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| 204 | 8'b10000000 : |
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| 205 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 206 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 207 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 208 | slv_reg0[bit_index] <= Bus2IP_Data[bit_index]; |
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| 209 | 8'b01000000 : |
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| 210 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 211 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 212 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 213 | slv_reg1[bit_index] <= Bus2IP_Data[bit_index]; |
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| 214 | 8'b00100000 : |
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| 215 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 216 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 217 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 218 | slv_reg2[bit_index] <= Bus2IP_Data[bit_index]; |
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| 219 | 8'b00010000 : |
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| 220 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 221 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 222 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 223 | slv_reg3[bit_index] <= Bus2IP_Data[bit_index]; |
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| 224 | 8'b00001000 : |
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| 225 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 226 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 227 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 228 | slv_reg4[bit_index] <= Bus2IP_Data[bit_index]; |
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| 229 | 8'b00000100 : |
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| 230 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 231 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 232 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 233 | slv_reg5[bit_index] <= Bus2IP_Data[bit_index]; |
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| 234 | 8'b00000010 : |
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| 235 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 236 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 237 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 238 | slv_reg6[bit_index] <= Bus2IP_Data[bit_index]; |
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| 239 | 8'b00000001 : |
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| 240 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 241 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 242 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 243 | slv_reg7[bit_index] <= Bus2IP_Data[bit_index]; |
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| 244 | default : ; |
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| 245 | endcase |
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| 246 | |
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| 247 | end // SLAVE_REG_WRITE_PROC |
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| 248 | |
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| 249 | wire [0:7] samp_spi_rx_byte; |
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| 250 | wire [0:7] rfref_spi_rx_byte; |
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| 251 | |
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| 252 | // implement slave model register read mux |
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| 253 | always @* //( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 ) |
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| 254 | begin: SLAVE_REG_READ_PROC |
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| 255 | |
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| 256 | case ( slv_reg_read_sel ) |
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| 257 | 8'b10000000 : slv_ip2bus_data <= slv_reg0; |
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| 258 | 8'b01000000 : slv_ip2bus_data <= slv_reg1; |
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| 259 | 8'b00100000 : slv_ip2bus_data <= {16'b0, rfref_spi_rx_byte, samp_spi_rx_byte}; |
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| 260 | 8'b00010000 : slv_ip2bus_data <= slv_reg3; |
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| 261 | 8'b00001000 : slv_ip2bus_data <= usr_status_d; |
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| 262 | 8'b00000100 : slv_ip2bus_data <= slv_reg5; |
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| 263 | 8'b00000010 : slv_ip2bus_data <= slv_reg6; |
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| 264 | 8'b00000001 : slv_ip2bus_data <= slv_reg7; |
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| 265 | default : slv_ip2bus_data <= 0; |
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| 266 | endcase |
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| 267 | |
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| 268 | end // SLAVE_REG_READ_PROC |
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| 269 | |
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| 270 | // ------------------------------------------------------------ |
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| 271 | // Example code to drive IP to Bus signals |
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| 272 | // ------------------------------------------------------------ |
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| 273 | |
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| 274 | assign IP2Bus_Data = slv_ip2bus_data; |
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| 275 | // assign IP2Bus_WrAck = slv_write_ack; //Overridden below |
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| 276 | assign IP2Bus_RdAck = slv_read_ack; |
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| 277 | assign IP2Bus_Error = 0; |
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| 278 | |
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| 279 | /* Address map: |
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| 280 | HDL is coded [MSB:LSB] = [0:31] |
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| 281 | regX[0] maps to 0x80000000 in C driver |
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| 282 | regX[31] maps to 0x00000001 in C driver |
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| 283 | |
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| 284 | 0: Config: {clk_div_sel[2:0], 1'b0, samp_func, rfref_func, 26'b0} |
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| 285 | [29:31] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x00000003 |
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| 286 | [28 ] Reserved |
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| 287 | [ 27] samp buf reset (active low) 0x00000010 |
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| 288 | [ 26] rf ref buf reset (active low) 0x00000020 |
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| 289 | [0 :25] Reserved |
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| 290 | |
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| 291 | 1: SPI Tx |
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| 292 | [24:31] Tx data byte |
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| 293 | [17:23] 7-bit register address (0x00 to 0xFF all valid) |
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| 294 | [11:16] 6'b0 (always zero) |
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| 295 | [ 9:10] Num bytes to Tx/Rx; must be 2'b0 for 1-byte Tx/Rx |
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| 296 | [ 8] RW# 1=Read, 0=Write |
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| 297 | [ 7] ad1 chip select mask |
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| 298 | [ 6] ad2 chip select mask |
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| 299 | [ 0: 5] Reserved |
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| 300 | |
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| 301 | 2: SPI Rx: {samp_rxByte, rfref_rxByte, 16'b0} |
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| 302 | [24:31] SPI Rx byte for samp buf 0x00FF |
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| 303 | [16:23] SPI Rx byte for rf ref buf 0xFF00 |
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| 304 | [ 0:15] Reserved 0xFFFF0000 |
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| 305 | |
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| 306 | 3: RW: User reset outputs |
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| 307 | [31] usr_reset0 |
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| 308 | [30] usr_reset1 |
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| 309 | [29] usr_reset2 |
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| 310 | [28] usr_reset3 |
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| 311 | [0:27] reserved |
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| 312 | |
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| 313 | 4: RO: User status inputs |
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| 314 | [0:31] usr_status input |
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| 315 | |
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| 316 | 5-15: Reserved |
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| 317 | */ |
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| 318 | |
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| 319 | |
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| 320 | `define AD9512_SPI_XFER_LEN 5'd24 |
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| 321 | |
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| 322 | wire spi_mosi; |
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| 323 | wire spi_sclk; |
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| 324 | wire spi_cs; |
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| 325 | wire spi_rnw; |
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| 326 | wire spi_tx_reg_write; |
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| 327 | wire [0:2] clk_div_sel; |
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| 328 | wire spi_xfer_done; |
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| 329 | |
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| 330 | wire samp_spi_cs, rfref_spi_cs; |
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| 331 | |
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| 332 | wire [0:31] samp_spi_rxData; |
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| 333 | wire [0:31] rfref_spi_rxData; |
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| 334 | |
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| 335 | reg [0:31] usr_status_d; |
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| 336 | |
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| 337 | //Register the usr_status input here, to ease timing closure of potentially fast host PLBs |
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| 338 | always @(posedge Bus2IP_Clk) |
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| 339 | usr_status_d <= usr_status; |
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| 340 | |
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| 341 | //Extract bits from IPIF slave registers and control signals |
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| 342 | |
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| 343 | //spi_io stores 32 bits for Tx/Rx |
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| 344 | // AD9512 only outputs 8-bit words during reads, always the last 8 bits of the transfer |
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| 345 | assign samp_spi_rx_byte = samp_spi_rxData[24:31]; |
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| 346 | assign rfref_spi_rx_byte = rfref_spi_rxData[24:31]; |
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| 347 | |
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| 348 | //SPI clock divider selection |
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| 349 | assign clk_div_sel = slv_reg0[29:31]; //0x3 from driver |
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| 350 | |
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| 351 | //SPI device resets (active low) |
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| 352 | assign samp_func = slv_reg0[27]; //0x10 from driver |
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| 353 | assign rfref_func = slv_reg0[26]; //0x20 from driver |
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| 354 | |
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| 355 | //SPI device chip selects (active high; inverted before use below) |
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| 356 | assign samp_spi_cs = slv_reg1[7]; //0x01000000 from driver |
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| 357 | assign rfref_spi_cs = slv_reg1[6]; //0x02000000 from driver |
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| 358 | |
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| 359 | //User reset outputs |
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| 360 | assign usr_reset0 = slv_reg3[31]; |
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| 361 | assign usr_reset1 = slv_reg3[30]; |
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| 362 | assign usr_reset2 = slv_reg3[29]; |
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| 363 | assign usr_reset3 = slv_reg3[28]; |
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| 364 | |
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| 365 | //Use the IPIC write-enable for the SPI Tx register as the SPI go |
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| 366 | // The bus will be paused until this core ACKs the write |
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| 367 | assign spi_tx_reg_write = Bus2IP_WrCE[1]; |
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| 368 | |
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| 369 | //spi_tx_reg_write (Bus2IP_WrCE[1]) de-asserts as soon as transaction is ACK'd |
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| 370 | // so this mux switches back to the generic ACK as soon as the SPI xfer is done |
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| 371 | //Thus, the duration of assertion for spi_xfer_done doesn't really matter |
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| 372 | //A bit fast-n-loose, but works ok |
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| 373 | assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack; |
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| 374 | |
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| 375 | //SPI device chip selects are active low |
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| 376 | assign samp_spi_cs_n = ~(samp_spi_cs & spi_cs); |
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| 377 | assign rfref_spi_cs_n = ~(rfref_spi_cs & spi_cs); |
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| 378 | |
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| 379 | //Mask each device's SPI clock output by its CS; no point toggling signals that will be ignored |
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| 380 | assign samp_spi_sclk = (spi_sclk & samp_spi_cs); |
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| 381 | assign rfref_spi_sclk = (spi_sclk & rfref_spi_cs); |
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| 382 | |
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| 383 | //All SPI devices driven by same serial data output; CS signals control who listens |
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| 384 | assign samp_spi_mosi = samp_spi_cs ? spi_mosi : 1'b0; |
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| 385 | assign rfref_spi_mosi = rfref_spi_cs ? spi_mosi : 1'b0; |
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| 386 | |
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| 387 | warp_spi_io #(.SPI_XFER_LEN(`AD9512_SPI_XFER_LEN)) spi_io |
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| 388 | ( |
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| 389 | .sys_clk(Bus2IP_Clk), |
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| 390 | .reset(Bus2IP_Reset), |
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| 391 | .go(spi_tx_reg_write), |
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| 392 | .done(spi_xfer_done), |
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| 393 | .clkDiv(clk_div_sel), |
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| 394 | |
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| 395 | .currBitNum(), |
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| 396 | |
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| 397 | .txData(slv_reg1), |
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| 398 | |
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| 399 | .rxData1(samp_spi_rxData), |
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| 400 | .rxData2(rfref_spi_rxData), |
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| 401 | .rxData3(), |
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| 402 | .rxData4(), |
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| 403 | |
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| 404 | .spi_cs(spi_cs), |
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| 405 | .spi_sclk(spi_sclk), |
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| 406 | |
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| 407 | .spi_mosi(spi_mosi), |
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| 408 | |
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| 409 | .spi_miso1(samp_spi_miso), |
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| 410 | .spi_miso2(rfref_spi_miso), |
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| 411 | .spi_miso3(1'b0), |
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| 412 | .spi_miso4(1'b0) |
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| 413 | ); |
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| 414 | endmodule |
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