source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_v3_01_a/hdl/verilog/at_boot_reg_writer.v

module at_boot_reg_writer
(
    input clk,

    input clk_src_sel, //1=on-board, 0=off-board

    output spi_running,
    
    output spi_mosi,
    output spi_sclk,
    output reg spi_csn = 1
);

parameter INCLUDE_IBUFGDS = 1;
parameter NUM_REGS = 3;

//AD9512 registers are 8 bits each, addressed by 7 bit addresses

//reg45[0]: clock src sel (0=CLK2=off-board, 1=CLK1=on-board)
parameter ADDR0 = 7'h45;
parameter DATA0 = 8'b0000_0000; //LSB to be overwritten by config input

//reg51[7]: bypass divider for OUT3 (1=bypass)
parameter ADDR1 = 7'h51;
parameter DATA1 = 8'b1000_0000;

//reg5A[0]: self-clearing reg update flag
parameter ADDR2 = 7'h5A;
parameter DATA2 = 8'b0000_0001;

reg [0:2] cnt_reg = 3'h0;
reg [0:4] cnt_bit = 5'h0;
reg [0:3] cnt_clk_en = 4'h0;

wire done;

wire clk_en;
assign clk_en = (cnt_clk_en == 4'hf);

reg [0:24*3-1] spi_shift_reg = {9'b0, ADDR0, DATA0, 9'b0, ADDR1, DATA1, 9'b0, ADDR2, DATA2};
//reg [0:24*3-1] spi_shift_reg = {24'h800001, 24'h800001, 24'h800001};//sim test vector
//reg [0:24*3-1] spi_shift_reg = {24'h800002, 24'h800003, 24'h800004};//sim test vector

always @(posedge clk) begin

    if(!done & clk_en) begin

        cnt_bit <= cnt_bit + 1;

        if(cnt_bit == 5'h1f) begin
            cnt_bit <= 5'h00;
            cnt_reg <= cnt_reg + 1;
        end
        
        if( (cnt_bit >= 4) && (cnt_bit < 28) ) begin
            spi_csn <= 1'b0;
        end
        else begin
            spi_csn <= 1'b1;
        end

        if( (cnt_bit > 4) && (cnt_bit <= 28) ) begin
            spi_shift_reg[0:24*NUM_REGS-1] <= {spi_shift_reg[1:24*NUM_REGS-1], 1'b0};
        end
        else begin
            spi_shift_reg <= spi_shift_reg;
        end
    end
end

assign done = ((cnt_bit == 5'h1f) && (cnt_reg == NUM_REGS-1));

//assign spi_mosi = (cnt_bit == 16 && cnt_reg == 0) ? (~clk_src_sel) : spi_shift_reg[0];
assign spi_mosi = (cnt_bit == 28 && cnt_reg == 0) ? (clk_src_sel) : spi_shift_reg[0];
assign spi_sclk = cnt_clk_en[0];
assign spi_running = (!done) || (cnt_reg==5'h0);

always @(posedge clk) begin
    if(!done)
        cnt_clk_en = cnt_clk_en + 1;
end

endmodule