[5058] | 1 | //---------------------------------------------------------------------------- |
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| 2 | // user_logic.v - module |
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| 3 | //---------------------------------------------------------------------------- |
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| 4 | // |
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| 5 | // *************************************************************************** |
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| 6 | // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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| 7 | // ** ** |
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| 8 | // ** Xilinx, Inc. ** |
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| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
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| 22 | // ** ** |
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| 23 | // *************************************************************************** |
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| 24 | // |
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| 25 | //---------------------------------------------------------------------------- |
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| 26 | // Filename: user_logic.v |
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| 27 | // Version: 1.00.b |
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| 28 | // Description: User logic module. |
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| 29 | // Date: Sat Feb 23 20:58:52 2013 (by Create and Import Peripheral Wizard) |
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| 30 | // Verilog Standard: Verilog-2001 |
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| 31 | //---------------------------------------------------------------------------- |
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| 32 | // Naming Conventions: |
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| 33 | // active low signals: "*_n" |
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| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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| 35 | // reset signals: "rst", "rst_n" |
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| 36 | // generics: "C_*" |
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| 37 | // user defined types: "*_TYPE" |
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| 38 | // state machine next state: "*_ns" |
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| 39 | // state machine current state: "*_cs" |
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| 40 | // combinatorial signals: "*_com" |
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| 41 | // pipelined or register delay signals: "*_d#" |
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| 42 | // counter signals: "*cnt*" |
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| 43 | // clock enable signals: "*_ce" |
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| 44 | // internal version of output port: "*_i" |
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| 45 | // device pins: "*_pin" |
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| 46 | // ports: "- Names begin with Uppercase" |
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| 47 | // processes: "*_PROCESS" |
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| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 49 | //---------------------------------------------------------------------------- |
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| 50 | |
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| 51 | `uselib lib=unisims_ver |
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| 52 | `uselib lib=proc_common_v3_00_a |
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| 53 | |
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| 54 | module user_logic |
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| 55 | ( |
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| 56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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| 57 | iic_sda_I, |
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| 58 | iic_sda_O, |
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| 59 | iic_sda_T, |
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| 60 | |
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| 61 | iic_scl_I, |
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| 62 | iic_scl_O, |
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| 63 | iic_scl_T, |
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| 64 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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| 65 | |
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| 66 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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| 67 | // -- Bus protocol ports, do not add to or delete |
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| 68 | Bus2IP_Clk, // Bus to IP clock |
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| 69 | Bus2IP_Resetn, // Bus to IP reset |
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| 70 | Bus2IP_Data, // Bus to IP data bus |
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| 71 | Bus2IP_BE, // Bus to IP byte enables |
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| 72 | Bus2IP_RdCE, // Bus to IP read chip enable |
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| 73 | Bus2IP_WrCE, // Bus to IP write chip enable |
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| 74 | IP2Bus_Data, // IP to Bus data bus |
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| 75 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
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| 76 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
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| 77 | IP2Bus_Error // IP to Bus error response |
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| 78 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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| 79 | ); // user_logic |
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| 80 | |
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| 81 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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| 82 | // --USER parameters added here |
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| 83 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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| 84 | |
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| 85 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 86 | // -- Bus protocol parameters, do not add to or delete |
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| 87 | parameter C_NUM_REG = 16; |
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| 88 | parameter C_SLV_DWIDTH = 32; |
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| 89 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 90 | |
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| 91 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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| 92 | input iic_sda_I; |
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| 93 | output iic_sda_O; |
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| 94 | output iic_sda_T; |
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| 95 | |
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| 96 | input iic_scl_I; |
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| 97 | output iic_scl_O; |
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| 98 | output iic_scl_T; |
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| 99 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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| 100 | |
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| 101 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 102 | // -- Bus protocol ports, do not add to or delete |
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| 103 | input Bus2IP_Clk; |
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| 104 | input Bus2IP_Resetn; |
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| 105 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; |
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| 106 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; |
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| 107 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE; |
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| 108 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE; |
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| 109 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; |
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| 110 | output IP2Bus_RdAck; |
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| 111 | output IP2Bus_WrAck; |
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| 112 | output IP2Bus_Error; |
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| 113 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 114 | |
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| 115 | //---------------------------------------------------------------------------- |
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| 116 | // Implementation |
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| 117 | //---------------------------------------------------------------------------- |
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| 118 | |
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| 119 | // --USER nets declarations added here, as needed for user logic |
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| 120 | |
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| 121 | // Nets for user logic slave model s/w accessible register example |
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| 122 | reg [C_SLV_DWIDTH-1 : 0] slv_reg00; |
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| 123 | reg [C_SLV_DWIDTH-1 : 0] slv_reg01; |
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| 124 | reg [C_SLV_DWIDTH-1 : 0] slv_reg02; |
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| 125 | reg [C_SLV_DWIDTH-1 : 0] slv_reg03; |
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| 126 | reg [C_SLV_DWIDTH-1 : 0] slv_reg04; |
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| 127 | reg [C_SLV_DWIDTH-1 : 0] slv_reg05; |
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| 128 | reg [C_SLV_DWIDTH-1 : 0] slv_reg06; |
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| 129 | reg [C_SLV_DWIDTH-1 : 0] slv_reg07; |
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| 130 | reg [C_SLV_DWIDTH-1 : 0] slv_reg08; |
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| 131 | reg [C_SLV_DWIDTH-1 : 0] slv_reg09; |
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| 132 | reg [C_SLV_DWIDTH-1 : 0] slv_reg10; |
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| 133 | reg [C_SLV_DWIDTH-1 : 0] slv_reg11; |
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| 134 | reg [C_SLV_DWIDTH-1 : 0] slv_reg12; |
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| 135 | reg [C_SLV_DWIDTH-1 : 0] slv_reg13; |
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| 136 | reg [C_SLV_DWIDTH-1 : 0] slv_reg14; |
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| 137 | reg [C_SLV_DWIDTH-1 : 0] slv_reg15; |
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| 138 | wire [15: 0] slv_reg_write_sel; |
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| 139 | wire [15: 0] slv_reg_read_sel; |
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| 140 | reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; |
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| 141 | wire slv_read_ack; |
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| 142 | wire slv_write_ack; |
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| 143 | integer byte_index, bit_index; |
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| 144 | |
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| 145 | // USER logic implementation added here |
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| 146 | |
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| 147 | // ------------------------------------------------------ |
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| 148 | // Example code to read/write user logic slave model s/w accessible registers |
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| 149 | // |
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| 150 | // Note: |
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| 151 | // The example code presented here is to show you one way of reading/writing |
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| 152 | // software accessible registers implemented in the user logic slave model. |
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| 153 | // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond |
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| 154 | // to one software accessible register by the top level template. For example, |
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| 155 | // if you have four 32 bit software accessible registers in the user logic, |
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| 156 | // you are basically operating on the following memory mapped registers: |
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| 157 | // |
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| 158 | // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register |
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| 159 | // "1000" C_BASEADDR + 0x0 |
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| 160 | // "0100" C_BASEADDR + 0x4 |
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| 161 | // "0010" C_BASEADDR + 0x8 |
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| 162 | // "0001" C_BASEADDR + 0xC |
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| 163 | // |
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| 164 | // ------------------------------------------------------ |
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| 165 | |
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| 166 | assign |
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| 167 | slv_reg_write_sel = Bus2IP_WrCE[15:0], |
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| 168 | slv_reg_read_sel = Bus2IP_RdCE[15:0], |
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| 169 | slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15], |
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| 170 | slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15]; |
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| 171 | |
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| 172 | // implement slave model register(s) |
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| 173 | always @( posedge Bus2IP_Clk ) |
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| 174 | begin |
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| 175 | |
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| 176 | if ( Bus2IP_Resetn == 1'b0 ) |
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| 177 | begin |
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| 178 | slv_reg00 <= 0; |
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| 179 | slv_reg01 <= 0; |
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| 180 | slv_reg02 <= 0; |
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| 181 | slv_reg03 <= 0; |
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| 182 | slv_reg04 <= 0; |
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| 183 | slv_reg05 <= 0; |
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| 184 | slv_reg06 <= 0; |
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| 185 | slv_reg07 <= 0; |
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| 186 | slv_reg08 <= 0; |
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| 187 | slv_reg09 <= 0; |
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| 188 | slv_reg10 <= 0; |
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| 189 | slv_reg11 <= 0; |
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| 190 | slv_reg12 <= 0; |
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| 191 | slv_reg13 <= 0; |
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| 192 | slv_reg14 <= 0; |
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| 193 | slv_reg15 <= 0; |
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| 194 | end |
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| 195 | else |
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| 196 | case ( slv_reg_write_sel ) |
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| 197 | 16'b1000000000000000 : |
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| 198 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 199 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 200 | slv_reg00[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 201 | 16'b0100000000000000 : |
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| 202 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 203 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 204 | slv_reg01[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 205 | 16'b0010000000000000 : |
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| 206 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 207 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 208 | slv_reg02[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 209 | 16'b0001000000000000 : |
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| 210 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 211 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 212 | slv_reg03[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 213 | |
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| 214 | // Mutex register |
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| 215 | // - [31] is a "lock" bit and is always writeable |
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| 216 | // - [30:0] are writeable only if [31] is zero |
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| 217 | // |
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| 218 | // NOTE: Both Bus2IP_BE and Bus2IP_Data are accessed with magic numbers vs the parameterized |
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| 219 | // values. If the data width of the slave interface is changed, then this must be updated. |
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| 220 | // |
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| 221 | 16'b0000100000000000 : |
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| 222 | if ( slv_reg04[31] == 0 ) // Check lock bit |
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| 223 | begin // Update all bytes that are enabled (includes lock bit) |
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| 224 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 225 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 226 | slv_reg04[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 227 | end |
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| 228 | else |
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| 229 | begin // Update only lock bit |
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| 230 | if ( Bus2IP_BE[3] == 1 ) |
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| 231 | slv_reg04[31] <= Bus2IP_Data[31]; |
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| 232 | end |
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| 233 | |
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| 234 | 16'b0000010000000000 : |
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| 235 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 236 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 237 | slv_reg05[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 238 | 16'b0000001000000000 : |
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| 239 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 240 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 241 | slv_reg06[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 242 | 16'b0000000100000000 : |
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| 243 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 244 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 245 | slv_reg07[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 246 | 16'b0000000010000000 : |
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| 247 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 248 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 249 | slv_reg08[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 250 | 16'b0000000001000000 : |
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| 251 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 252 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 253 | slv_reg09[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 254 | 16'b0000000000100000 : |
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| 255 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 256 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 257 | slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 258 | 16'b0000000000010000 : |
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| 259 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 260 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 261 | slv_reg11[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 262 | 16'b0000000000001000 : |
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| 263 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 264 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 265 | slv_reg12[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 266 | 16'b0000000000000100 : |
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| 267 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 268 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 269 | slv_reg13[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 270 | 16'b0000000000000010 : |
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| 271 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 272 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 273 | slv_reg14[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 274 | 16'b0000000000000001 : |
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| 275 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 276 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 277 | slv_reg15[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 278 | |
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| 279 | default : begin |
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| 280 | slv_reg00 <= slv_reg00; |
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| 281 | slv_reg01 <= slv_reg01; |
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| 282 | slv_reg02 <= slv_reg02; |
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| 283 | slv_reg03 <= slv_reg03; |
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| 284 | slv_reg04 <= slv_reg04; |
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| 285 | slv_reg05 <= slv_reg05; |
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| 286 | slv_reg06 <= slv_reg06; |
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| 287 | slv_reg07 <= slv_reg07; |
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| 288 | slv_reg08 <= slv_reg08; |
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| 289 | slv_reg09 <= slv_reg09; |
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| 290 | slv_reg10 <= slv_reg10; |
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| 291 | slv_reg11 <= slv_reg11; |
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| 292 | slv_reg12 <= slv_reg12; |
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| 293 | slv_reg13 <= slv_reg13; |
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| 294 | slv_reg14 <= slv_reg14; |
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| 295 | slv_reg15 <= slv_reg15; |
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| 296 | end |
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| 297 | endcase |
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| 298 | |
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| 299 | end // SLAVE_REG_WRITE_PROC |
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| 300 | |
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| 301 | // implement slave model register read mux |
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| 302 | always @* |
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| 303 | begin |
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| 304 | case ( slv_reg_read_sel ) |
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| 305 | 16'b1000000000000000 : slv_ip2bus_data <= slv_reg00_rd; |
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| 306 | 16'b0100000000000000 : slv_ip2bus_data <= slv_reg01; |
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| 307 | 16'b0010000000000000 : slv_ip2bus_data <= slv_reg02; |
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| 308 | 16'b0001000000000000 : slv_ip2bus_data <= slv_reg03_rd; |
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| 309 | 16'b0000100000000000 : slv_ip2bus_data <= slv_reg04; |
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| 310 | 16'b0000010000000000 : slv_ip2bus_data <= slv_reg05; |
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| 311 | 16'b0000001000000000 : slv_ip2bus_data <= slv_reg06; |
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| 312 | 16'b0000000100000000 : slv_ip2bus_data <= slv_reg07; |
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| 313 | 16'b0000000010000000 : slv_ip2bus_data <= slv_reg08; |
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| 314 | 16'b0000000001000000 : slv_ip2bus_data <= slv_reg09; |
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| 315 | 16'b0000000000100000 : slv_ip2bus_data <= slv_reg10; |
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| 316 | 16'b0000000000010000 : slv_ip2bus_data <= slv_reg11; |
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| 317 | 16'b0000000000001000 : slv_ip2bus_data <= slv_reg12; |
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| 318 | 16'b0000000000000100 : slv_ip2bus_data <= slv_reg13; |
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| 319 | 16'b0000000000000010 : slv_ip2bus_data <= slv_reg14; |
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| 320 | 16'b0000000000000001 : slv_ip2bus_data <= slv_reg15; |
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| 321 | default : slv_ip2bus_data <= 0; |
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| 322 | endcase |
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| 323 | |
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| 324 | end // SLAVE_REG_READ_PROC |
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| 325 | |
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| 326 | // ------------------------------------------------------------ |
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| 327 | // Example code to drive IP to Bus signals |
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| 328 | // ------------------------------------------------------------ |
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| 329 | assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; |
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| 330 | assign IP2Bus_WrAck = slv_write_ack; |
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| 331 | assign IP2Bus_RdAck = slv_read_ack; |
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| 332 | assign IP2Bus_Error = 0; |
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| 333 | |
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| 334 | /* Address map: |
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| 335 | HDL is coded [MSB:LSB] = [31:0] |
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| 336 | regX[31] maps to 0x80000000 in C driver |
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| 337 | regX[0] maps to 0x00000001 in C driver |
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| 338 | |
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| 339 | 00: Config/Status[31: 0]: RW |
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| 340 | [ 7: 0]: clk divider (see comments below for interpretation) RW 0x000000FF |
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| 341 | [8]: core enable (1=enabled, 0=disabled) RW 0x00000100 |
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| 342 | [15: 9]: Reserved (always zero) RO 0x0000FE00 |
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| 343 | [16]: RxACK: received ACK from slave (1=received ACK) RO 0x00010000 |
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| 344 | [17]: Busy: IIC bus busy (1 between Start and Stop events) RO 0x00020000 |
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| 345 | [18]: AL: Arbitration lost (1 when Stop detected but not requested) RO 0x00040000 |
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| 346 | [19]: TIP: Transfer in progress (1 during transfer) RO 0x00080000 |
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| 347 | [31:20]: Reserved RW 0xFFF00000 |
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| 348 | |
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| 349 | 01: Command[31: 0]: RW, self-clearing, uses local reg, not normal slv_reg1 |
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| 350 | [0]: Start: generate IIC start 0x01 |
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| 351 | [1]: Stop: generate IIC stop 0x02 |
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| 352 | [2]: Read: execute IIC read 0x04 |
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| 353 | [3]: Write: execute IIC write 0x08 |
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| 354 | [4]: ACK: send ACK for current transaction 0x10 |
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| 355 | [31: 5]: Reserved |
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| 356 | |
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| 357 | 02: Transmit[31: 0]: {24'b0, txByte[7:0]} RW |
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| 358 | [ 7: 0]: Tx Byte ([31]=RNW during control word writes) |
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| 359 | [31: 8]: Reserved |
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| 360 | |
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| 361 | 03: Receive[31: 0]: {24'b0, rxByte[7:0]} RO |
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| 362 | [ 7: 0]: Rx Byte |
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| 363 | [31: 8]: Reserved |
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| 364 | |
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| 365 | 04: Mutex[31: 0]: RW (with lock bit) |
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| 366 | [30: 0]: User bits |
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| 367 | [31] : Lock |
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| 368 | |
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| 369 | 05: Serial Number [31:0]: RW |
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| 370 | [31: 0]: Serial Number |
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| 371 | |
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| 372 | 06: Ethernet A MAC address 0[31: 0]: RW |
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| 373 | [31: 0]: Ethernet A MAC address [31: 0] |
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| 374 | |
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| 375 | 07: Ethernet A MAC address 1[31: 0]: RW |
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| 376 | [15: 0]: Ethernet A MAC address [47:32] |
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| 377 | [31:16]: Reserved |
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| 378 | |
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| 379 | 08: Ethernet B MAC address 0[31: 0]: RW |
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| 380 | [31: 0]: Ethernet B MAC address [31: 0] |
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| 381 | |
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| 382 | 09: Ethernet B MAC address 1[31: 0]: RW |
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| 383 | [15: 0]: Ethernet B MAC address [47:32] |
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| 384 | [31:16]: Reserved |
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| 385 | |
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| 386 | 10: FPGA DNA 0[31: 0]: RW |
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| 387 | [31: 0]: FPGA DNA [31: 0] |
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| 388 | |
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| 389 | 11: FPGA DNA 1[31: 0]: RW |
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| 390 | [31: 0]: FPGA DNA [63:32] |
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| 391 | |
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| 392 | 12: Reserved |
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| 393 | 13: Reserved |
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| 394 | 14: Reserved |
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| 395 | 15: Reserved |
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| 396 | |
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| 397 | */ |
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| 398 | |
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| 399 | reg [4:0] cmd_reg; |
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| 400 | wire core_en; |
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| 401 | wire [15:0] clk_div; |
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| 402 | wire cmd_start, cmd_stop, cmd_read, cmd_write, cmd_ack; |
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| 403 | |
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| 404 | wire [7:0] iic_tx_byte; |
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| 405 | wire [7:0] iic_rx_byte; |
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| 406 | |
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| 407 | wire iic_rx_ack; |
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| 408 | wire iic_bus_busy; |
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| 409 | wire iic_al; |
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| 410 | wire iic_done; |
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| 411 | wire iic_tip; |
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| 412 | |
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| 413 | wire slv_reg01_WE; |
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| 414 | |
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| 415 | assign slv_reg01_WE = Bus2IP_WrCE[14]; // WrCE/RdCE[15:0] map to slv_reg[0:15] |
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| 416 | |
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| 417 | // Custom command register logic, implements self-clearing bits |
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| 418 | always @( posedge Bus2IP_Clk ) |
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| 419 | begin |
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| 420 | if ( Bus2IP_Resetn == 1'b0 ) |
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| 421 | cmd_reg <= 5'b0; |
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| 422 | else if(slv_reg01_WE == 1'b1) |
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| 423 | cmd_reg[4:0] <= Bus2IP_Data[4:0]; |
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| 424 | else if(iic_done | iic_al) |
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| 425 | begin |
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| 426 | // Clear start, stop, read, write bits on transfer completion or arbitration loss |
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| 427 | cmd_reg[3:0] <= 4'b0; |
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| 428 | cmd_reg[4] <= cmd_reg[4]; |
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| 429 | end |
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| 430 | else |
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| 431 | cmd_reg[4:0] <= cmd_reg[4:0]; |
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| 432 | end |
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| 433 | |
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| 434 | assign cmd_start = cmd_reg[0]; // 0x01 from driver |
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| 435 | assign cmd_stop = cmd_reg[1]; // 0x02 |
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| 436 | assign cmd_read = cmd_reg[2]; // 0x04 |
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| 437 | assign cmd_write = cmd_reg[3]; // 0x08 |
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| 438 | assign cmd_ack = cmd_reg[4]; // 0x10 |
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| 439 | |
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| 440 | assign iic_tip = (cmd_read | cmd_write); // Register bits self-clear on transfer completion |
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| 441 | |
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| 442 | |
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| 443 | // Construct 32-bit vectors for read access to mixed RW/RO registers |
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| 444 | wire [31:0] slv_reg00_rd; |
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| 445 | wire [31:0] slv_reg03_rd; |
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| 446 | assign slv_reg00_rd = {slv_reg00[31:20], iic_tip, iic_al, iic_bus_busy, iic_rx_ack, 7'b0, slv_reg00[8], slv_reg00[7:0]}; |
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| 447 | assign slv_reg03_rd = {24'b0, iic_rx_byte[7:0]}; |
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| 448 | |
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| 449 | |
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| 450 | // IIC master divides down master clock to generate SCL |
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| 451 | // SCL rate is (sys_clk / (5*clk_div[0:15])) |
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| 452 | // For 200MHz sys_clk and 100kHz SCL, clk_div = 400 = 0x190 |
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| 453 | // Interpret user-provided clock divider as bits[6:13] of clk_div |
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| 454 | assign clk_div[15:0] = {6'b0, slv_reg00[7:0], 2'b0}; |
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| 455 | assign core_en = slv_reg00[8]; |
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| 456 | |
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| 457 | assign iic_tx_byte = slv_reg02[7:0]; |
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| 458 | |
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| 459 | wire sda_pad_i, sda_pad_o, sda_pad_oe; |
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| 460 | wire scl_pad_i, scl_pad_o, scl_pad_oe; |
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| 461 | |
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| 462 | i2c_master_byte_ctrl byte_controller ( |
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| 463 | .clk ( Bus2IP_Clk ), // master clock |
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| 464 | .rst ( ~Bus2IP_Resetn ), // synchronous reset, active high |
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| 465 | .nReset ( 1'b1 ), // asynchronous reset, active low |
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| 466 | .ena ( core_en ), // core enable, active high |
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| 467 | .clk_cnt ( clk_div ), // master-to-iic clock divider |
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| 468 | .start ( cmd_start ), // send iic start |
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| 469 | .stop ( cmd_stop ), // send iic stop |
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| 470 | .read ( cmd_read ), // perform iic read |
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| 471 | .write ( cmd_write ), // perform iic write |
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| 472 | .ack_in ( cmd_ack ), // send iic ack |
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| 473 | .din ( iic_tx_byte ), // byte to send |
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| 474 | .cmd_ack ( iic_done ), // xfer is done |
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| 475 | .ack_out ( iic_rx_ack ), // ack from slave |
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| 476 | .dout ( iic_rx_byte ), // byte read from slave |
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| 477 | .i2c_busy ( iic_bus_busy ), |
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| 478 | .i2c_al ( iic_al ), // arbitration lost output |
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| 479 | .scl_i ( iic_scl_I ), // iic scl input (pad -> logic) |
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| 480 | .scl_o ( iic_scl_O ), // iic scl output (logic -> pad) |
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| 481 | .scl_oen ( iic_scl_T ), // iic scl output enable (0=scl is logic-driven output) |
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| 482 | .sda_i ( iic_sda_I ), // iic sda input (pad -> logic) |
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| 483 | .sda_o ( iic_sda_O ), // iic sda output (logic -> pad) |
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| 484 | .sda_oen ( iic_sda_T ) // iic sda output enable (0=sda is logic-driven output) |
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| 485 | ); |
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| 486 | |
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| 487 | endmodule |
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