[5058] | 1 | --------------------------------------------------------------------- |
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| 2 | ---- ---- |
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| 3 | ---- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- |
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| 4 | ---- ---- |
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| 5 | ---- ---- |
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| 6 | ---- Author: Richard Herveille ---- |
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| 7 | ---- richard@asics.ws ---- |
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| 8 | ---- www.asics.ws ---- |
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| 9 | ---- ---- |
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| 10 | ---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- |
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| 11 | ---- ---- |
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| 12 | --------------------------------------------------------------------- |
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| 13 | ---- ---- |
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| 14 | ---- Copyright (C) 2000 Richard Herveille ---- |
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| 15 | ---- richard@asics.ws ---- |
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| 16 | ---- ---- |
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| 17 | ---- This source file may be used and distributed without ---- |
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| 18 | ---- restriction provided that this copyright statement is not ---- |
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| 19 | ---- removed from the file and that any derivative work contains ---- |
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| 20 | ---- the original copyright notice and the associated disclaimer.---- |
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| 21 | ---- ---- |
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| 22 | ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- |
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| 23 | ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- |
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| 24 | ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- |
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| 25 | ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- |
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| 26 | ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- |
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| 27 | ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- |
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| 28 | ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- |
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| 29 | ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- |
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| 30 | ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- |
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| 31 | ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- |
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| 32 | ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- |
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| 33 | ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- |
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| 34 | ---- POSSIBILITY OF SUCH DAMAGE. ---- |
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| 35 | ---- ---- |
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| 36 | --------------------------------------------------------------------- |
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| 37 | |
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| 38 | -- CVS Log |
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| 39 | -- |
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| 40 | -- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $ |
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| 41 | -- |
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| 42 | -- $Date: 2004-02-18 11:41:48 $ |
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| 43 | -- $Revision: 1.5 $ |
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| 44 | -- $Author: rherveille $ |
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| 45 | -- $Locker: $ |
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| 46 | -- $State: Exp $ |
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| 47 | -- |
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| 48 | -- Change History: |
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| 49 | -- $Log: not supported by cvs2svn $ |
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| 50 | -- Revision 1.4 2003/08/09 07:01:13 rherveille |
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| 51 | -- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. |
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| 52 | -- Fixed a potential bug in the byte controller's host-acknowledge generation. |
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| 53 | -- |
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| 54 | -- Revision 1.3 2002/12/26 16:05:47 rherveille |
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| 55 | -- Core is now a Multimaster I2C controller. |
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| 56 | -- |
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| 57 | -- Revision 1.2 2002/11/30 22:24:37 rherveille |
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| 58 | -- Cleaned up code |
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| 59 | -- |
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| 60 | -- Revision 1.1 2001/11/05 12:02:33 rherveille |
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| 61 | -- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. |
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| 62 | -- Code updated, is now up-to-date to doc. rev.0.4. |
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| 63 | -- Added headers. |
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| 64 | -- |
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| 65 | |
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| 66 | |
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| 67 | |
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| 68 | |
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| 69 | -- |
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| 70 | ------------------------------------------ |
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| 71 | -- Byte controller section |
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| 72 | ------------------------------------------ |
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| 73 | -- |
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| 74 | library ieee; |
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| 75 | use ieee.std_logic_1164.all; |
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| 76 | use ieee.std_logic_arith.all; |
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| 77 | |
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| 78 | entity i2c_master_byte_ctrl is |
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| 79 | port ( |
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| 80 | clk : in std_logic; |
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| 81 | rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) |
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| 82 | nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) |
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| 83 | ena : in std_logic; -- core enable signal |
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| 84 | |
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| 85 | clk_cnt : in unsigned(15 downto 0); -- 4x SCL |
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| 86 | |
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| 87 | -- input signals |
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| 88 | start, |
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| 89 | stop, |
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| 90 | read, |
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| 91 | write, |
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| 92 | ack_in : std_logic; |
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| 93 | din : in std_logic_vector(7 downto 0); |
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| 94 | |
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| 95 | -- output signals |
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| 96 | cmd_ack : out std_logic; -- command done |
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| 97 | ack_out : out std_logic; |
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| 98 | i2c_busy : out std_logic; -- arbitration lost |
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| 99 | i2c_al : out std_logic; -- i2c bus busy |
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| 100 | dout : out std_logic_vector(7 downto 0); |
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| 101 | |
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| 102 | -- i2c lines |
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| 103 | scl_i : in std_logic; -- i2c clock line input |
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| 104 | scl_o : out std_logic; -- i2c clock line output |
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| 105 | scl_oen : out std_logic; -- i2c clock line output enable, active low |
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| 106 | sda_i : in std_logic; -- i2c data line input |
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| 107 | sda_o : out std_logic; -- i2c data line output |
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| 108 | sda_oen : out std_logic -- i2c data line output enable, active low |
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| 109 | ); |
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| 110 | end entity i2c_master_byte_ctrl; |
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| 111 | |
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| 112 | architecture structural of i2c_master_byte_ctrl is |
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| 113 | component i2c_master_bit_ctrl is |
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| 114 | port ( |
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| 115 | clk : in std_logic; |
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| 116 | rst : in std_logic; |
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| 117 | nReset : in std_logic; |
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| 118 | ena : in std_logic; -- core enable signal |
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| 119 | |
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| 120 | clk_cnt : in unsigned(15 downto 0); -- clock prescale value |
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| 121 | |
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| 122 | cmd : in std_logic_vector(3 downto 0); |
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| 123 | cmd_ack : out std_logic; -- command done |
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| 124 | busy : out std_logic; -- i2c bus busy |
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| 125 | al : out std_logic; -- arbitration lost |
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| 126 | |
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| 127 | din : in std_logic; |
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| 128 | dout : out std_logic; |
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| 129 | |
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| 130 | -- i2c lines |
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| 131 | scl_i : in std_logic; -- i2c clock line input |
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| 132 | scl_o : out std_logic; -- i2c clock line output |
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| 133 | scl_oen : out std_logic; -- i2c clock line output enable, active low |
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| 134 | sda_i : in std_logic; -- i2c data line input |
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| 135 | sda_o : out std_logic; -- i2c data line output |
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| 136 | sda_oen : out std_logic -- i2c data line output enable, active low |
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| 137 | ); |
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| 138 | end component i2c_master_bit_ctrl; |
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| 139 | |
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| 140 | -- commands for bit_controller block |
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| 141 | constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; |
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| 142 | constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; |
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| 143 | constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; |
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| 144 | constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; |
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| 145 | constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; |
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| 146 | |
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| 147 | -- signals for bit_controller |
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| 148 | signal core_cmd : std_logic_vector(3 downto 0); |
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| 149 | signal core_ack, core_txd, core_rxd : std_logic; |
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| 150 | signal al : std_logic; |
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| 151 | |
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| 152 | -- signals for shift register |
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| 153 | signal sr : std_logic_vector(7 downto 0); -- 8bit shift register |
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| 154 | signal shift, ld : std_logic; |
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| 155 | |
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| 156 | -- signals for state machine |
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| 157 | signal go, host_ack : std_logic; |
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| 158 | signal dcnt : unsigned(2 downto 0); -- data counter |
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| 159 | signal cnt_done : std_logic; |
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| 160 | |
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| 161 | begin |
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| 162 | -- hookup bit_controller |
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| 163 | bit_ctrl: i2c_master_bit_ctrl port map( |
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| 164 | clk => clk, |
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| 165 | rst => rst, |
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| 166 | nReset => nReset, |
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| 167 | ena => ena, |
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| 168 | clk_cnt => clk_cnt, |
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| 169 | cmd => core_cmd, |
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| 170 | cmd_ack => core_ack, |
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| 171 | busy => i2c_busy, |
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| 172 | al => al, |
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| 173 | din => core_txd, |
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| 174 | dout => core_rxd, |
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| 175 | scl_i => scl_i, |
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| 176 | scl_o => scl_o, |
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| 177 | scl_oen => scl_oen, |
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| 178 | sda_i => sda_i, |
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| 179 | sda_o => sda_o, |
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| 180 | sda_oen => sda_oen |
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| 181 | ); |
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| 182 | i2c_al <= al; |
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| 183 | |
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| 184 | -- generate host-command-acknowledge |
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| 185 | cmd_ack <= host_ack; |
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| 186 | |
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| 187 | -- generate go-signal |
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| 188 | go <= (read or write or stop) and not host_ack; |
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| 189 | |
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| 190 | -- assign Dout output to shift-register |
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| 191 | dout <= sr; |
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| 192 | |
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| 193 | -- generate shift register |
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| 194 | shift_register: process(clk, nReset) |
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| 195 | begin |
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| 196 | if (nReset = '0') then |
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| 197 | sr <= (others => '0'); |
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| 198 | elsif (clk'event and clk = '1') then |
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| 199 | if (rst = '1') then |
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| 200 | sr <= (others => '0'); |
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| 201 | elsif (ld = '1') then |
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| 202 | sr <= din; |
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| 203 | elsif (shift = '1') then |
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| 204 | sr <= (sr(6 downto 0) & core_rxd); |
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| 205 | end if; |
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| 206 | end if; |
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| 207 | end process shift_register; |
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| 208 | |
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| 209 | -- generate data-counter |
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| 210 | data_cnt: process(clk, nReset) |
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| 211 | begin |
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| 212 | if (nReset = '0') then |
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| 213 | dcnt <= (others => '0'); |
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| 214 | elsif (clk'event and clk = '1') then |
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| 215 | if (rst = '1') then |
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| 216 | dcnt <= (others => '0'); |
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| 217 | elsif (ld = '1') then |
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| 218 | dcnt <= (others => '1'); -- load counter with 7 |
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| 219 | elsif (shift = '1') then |
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| 220 | dcnt <= dcnt -1; |
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| 221 | end if; |
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| 222 | end if; |
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| 223 | end process data_cnt; |
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| 224 | |
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| 225 | cnt_done <= '1' when (dcnt = 0) else '0'; |
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| 226 | |
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| 227 | -- |
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| 228 | -- state machine |
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| 229 | -- |
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| 230 | statemachine : block |
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| 231 | type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); |
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| 232 | signal c_state : states; |
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| 233 | begin |
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| 234 | -- |
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| 235 | -- command interpreter, translate complex commands into simpler I2C commands |
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| 236 | -- |
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| 237 | nxt_state_decoder: process(clk, nReset) |
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| 238 | begin |
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| 239 | if (nReset = '0') then |
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| 240 | core_cmd <= I2C_CMD_NOP; |
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| 241 | core_txd <= '0'; |
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| 242 | shift <= '0'; |
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| 243 | ld <= '0'; |
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| 244 | host_ack <= '0'; |
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| 245 | c_state <= st_idle; |
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| 246 | ack_out <= '0'; |
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| 247 | elsif (clk'event and clk = '1') then |
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| 248 | if (rst = '1' or al = '1') then |
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| 249 | core_cmd <= I2C_CMD_NOP; |
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| 250 | core_txd <= '0'; |
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| 251 | shift <= '0'; |
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| 252 | ld <= '0'; |
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| 253 | host_ack <= '0'; |
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| 254 | c_state <= st_idle; |
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| 255 | ack_out <= '0'; |
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| 256 | else |
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| 257 | -- initialy reset all signal |
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| 258 | core_txd <= sr(7); |
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| 259 | shift <= '0'; |
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| 260 | ld <= '0'; |
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| 261 | host_ack <= '0'; |
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| 262 | |
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| 263 | case c_state is |
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| 264 | when st_idle => |
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| 265 | if (go = '1') then |
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| 266 | if (start = '1') then |
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| 267 | c_state <= st_start; |
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| 268 | core_cmd <= I2C_CMD_START; |
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| 269 | elsif (read = '1') then |
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| 270 | c_state <= st_read; |
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| 271 | core_cmd <= I2C_CMD_READ; |
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| 272 | elsif (write = '1') then |
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| 273 | c_state <= st_write; |
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| 274 | core_cmd <= I2C_CMD_WRITE; |
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| 275 | else -- stop |
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| 276 | c_state <= st_stop; |
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| 277 | core_cmd <= I2C_CMD_STOP; |
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| 278 | end if; |
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| 279 | |
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| 280 | ld <= '1'; |
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| 281 | end if; |
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| 282 | |
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| 283 | when st_start => |
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| 284 | if (core_ack = '1') then |
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| 285 | if (read = '1') then |
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| 286 | c_state <= st_read; |
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| 287 | core_cmd <= I2C_CMD_READ; |
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| 288 | else |
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| 289 | c_state <= st_write; |
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| 290 | core_cmd <= I2C_CMD_WRITE; |
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| 291 | end if; |
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| 292 | |
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| 293 | ld <= '1'; |
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| 294 | end if; |
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| 295 | |
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| 296 | when st_write => |
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| 297 | if (core_ack = '1') then |
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| 298 | if (cnt_done = '1') then |
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| 299 | c_state <= st_ack; |
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| 300 | core_cmd <= I2C_CMD_READ; |
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| 301 | else |
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| 302 | c_state <= st_write; -- stay in same state |
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| 303 | core_cmd <= I2C_CMD_WRITE; -- write next bit |
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| 304 | shift <= '1'; |
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| 305 | end if; |
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| 306 | end if; |
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| 307 | |
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| 308 | when st_read => |
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| 309 | if (core_ack = '1') then |
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| 310 | if (cnt_done = '1') then |
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| 311 | c_state <= st_ack; |
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| 312 | core_cmd <= I2C_CMD_WRITE; |
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| 313 | else |
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| 314 | c_state <= st_read; -- stay in same state |
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| 315 | core_cmd <= I2C_CMD_READ; -- read next bit |
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| 316 | end if; |
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| 317 | |
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| 318 | shift <= '1'; |
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| 319 | core_txd <= ack_in; |
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| 320 | end if; |
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| 321 | |
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| 322 | when st_ack => |
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| 323 | if (core_ack = '1') then |
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| 324 | -- check for stop; Should a STOP command be generated ? |
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| 325 | if (stop = '1') then |
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| 326 | c_state <= st_stop; |
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| 327 | core_cmd <= I2C_CMD_STOP; |
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| 328 | else |
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| 329 | c_state <= st_idle; |
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| 330 | core_cmd <= I2C_CMD_NOP; |
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| 331 | |
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| 332 | -- generate command acknowledge signal |
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| 333 | host_ack <= '1'; |
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| 334 | end if; |
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| 335 | |
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| 336 | -- assign ack_out output to core_rxd (contains last received bit) |
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| 337 | ack_out <= core_rxd; |
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| 338 | |
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| 339 | core_txd <= '1'; |
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| 340 | else |
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| 341 | core_txd <= ack_in; |
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| 342 | end if; |
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| 343 | |
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| 344 | when st_stop => |
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| 345 | if (core_ack = '1') then |
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| 346 | c_state <= st_idle; |
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| 347 | core_cmd <= I2C_CMD_NOP; |
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| 348 | |
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| 349 | -- generate command acknowledge signal |
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| 350 | host_ack <= '1'; |
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| 351 | end if; |
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| 352 | |
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| 353 | when others => -- illegal states |
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| 354 | c_state <= st_idle; |
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| 355 | core_cmd <= I2C_CMD_NOP; |
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| 356 | report ("Byte controller entered illegal state."); |
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| 357 | |
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| 358 | end case; |
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| 359 | |
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| 360 | end if; |
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| 361 | end if; |
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| 362 | end process nxt_state_decoder; |
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| 363 | |
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| 364 | end block statemachine; |
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| 365 | |
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| 366 | end architecture structural; |
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| 367 | |
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