1 | ///////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// WISHBONE rev.B2 compliant I2C Master bit-controller //// |
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4 | //// //// |
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5 | //// //// |
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6 | //// Author: Richard Herveille //// |
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7 | //// richard@asics.ws //// |
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8 | //// www.asics.ws //// |
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9 | //// //// |
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10 | //// Downloaded from: http://www.opencores.org/projects/i2c/ //// |
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11 | //// //// |
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12 | ///////////////////////////////////////////////////////////////////// |
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13 | //// //// |
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14 | //// Copyright (C) 2001 Richard Herveille //// |
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15 | //// richard@asics.ws //// |
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16 | //// //// |
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17 | //// This source file may be used and distributed without //// |
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18 | //// restriction provided that this copyright statement is not //// |
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19 | //// removed from the file and that any derivative work contains //// |
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20 | //// the original copyright notice and the associated disclaimer.//// |
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21 | //// //// |
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22 | //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
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23 | //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
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24 | //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
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25 | //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
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26 | //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
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27 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
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28 | //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
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29 | //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
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30 | //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
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31 | //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
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32 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
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33 | //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
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34 | //// POSSIBILITY OF SUCH DAMAGE. //// |
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35 | //// //// |
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36 | ///////////////////////////////////////////////////////////////////// |
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37 | |
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38 | // CVS Log |
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39 | // |
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40 | // $Id: i2c_master_bit_ctrl.v,v 1.14 2009-01-20 10:25:29 rherveille Exp $ |
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41 | // |
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42 | // $Date: 2009-01-20 10:25:29 $ |
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43 | // $Revision: 1.14 $ |
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44 | // $Author: rherveille $ |
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45 | // $Locker: $ |
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46 | // $State: Exp $ |
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47 | // |
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48 | // Change History: |
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49 | // $Log: $ |
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50 | // Revision 1.14 2009/01/20 10:25:29 rherveille |
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51 | // Added clock synchronization logic |
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52 | // Fixed slave_wait signal |
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53 | // |
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54 | // Revision 1.13 2009/01/19 20:29:26 rherveille |
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55 | // Fixed synopsys miss spell (synopsis) |
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56 | // Fixed cr[0] register width |
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57 | // Fixed ! usage instead of ~ |
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58 | // Fixed bit controller parameter width to 18bits |
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59 | // |
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60 | // Revision 1.12 2006/09/04 09:08:13 rherveille |
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61 | // fixed short scl high pulse after clock stretch |
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62 | // fixed slave model not returning correct '(n)ack' signal |
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63 | // |
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64 | // Revision 1.11 2004/05/07 11:02:26 rherveille |
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65 | // Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. |
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66 | // |
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67 | // Revision 1.10 2003/08/09 07:01:33 rherveille |
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68 | // Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. |
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69 | // Fixed a potential bug in the byte controller's host-acknowledge generation. |
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70 | // |
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71 | // Revision 1.9 2003/03/10 14:26:37 rherveille |
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72 | // Fixed cmd_ack generation item (no bug). |
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73 | // |
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74 | // Revision 1.8 2003/02/05 00:06:10 rherveille |
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75 | // Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. |
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76 | // |
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77 | // Revision 1.7 2002/12/26 16:05:12 rherveille |
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78 | // Small code simplifications |
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79 | // |
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80 | // Revision 1.6 2002/12/26 15:02:32 rherveille |
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81 | // Core is now a Multimaster I2C controller |
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82 | // |
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83 | // Revision 1.5 2002/11/30 22:24:40 rherveille |
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84 | // Cleaned up code |
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85 | // |
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86 | // Revision 1.4 2002/10/30 18:10:07 rherveille |
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87 | // Fixed some reported minor start/stop generation timing issuess. |
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88 | // |
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89 | // Revision 1.3 2002/06/15 07:37:03 rherveille |
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90 | // Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. |
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91 | // |
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92 | // Revision 1.2 2001/11/05 11:59:25 rherveille |
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93 | // Fixed wb_ack_o generation bug. |
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94 | // Fixed bug in the byte_controller statemachine. |
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95 | // Added headers. |
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96 | // |
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97 | |
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98 | // |
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99 | ///////////////////////////////////// |
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100 | // Bit controller section |
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101 | ///////////////////////////////////// |
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102 | // |
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103 | // Translate simple commands into SCL/SDA transitions |
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104 | // Each command has 5 states, A/B/C/D/idle |
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105 | // |
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106 | // start: SCL ~~~~~~~~~~\____ |
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107 | // SDA ~~~~~~~~\______ |
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108 | // x | A | B | C | D | i |
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109 | // |
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110 | // repstart SCL ____/~~~~\___ |
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111 | // SDA __/~~~\______ |
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112 | // x | A | B | C | D | i |
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113 | // |
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114 | // stop SCL ____/~~~~~~~~ |
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115 | // SDA ==\____/~~~~~ |
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116 | // x | A | B | C | D | i |
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117 | // |
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118 | //- write SCL ____/~~~~\____ |
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119 | // SDA ==X=========X= |
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120 | // x | A | B | C | D | i |
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121 | // |
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122 | //- read SCL ____/~~~~\____ |
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123 | // SDA XXXX=====XXXX |
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124 | // x | A | B | C | D | i |
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125 | // |
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126 | |
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127 | // Timing: Normal mode Fast mode |
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128 | /////////////////////////////////////////////////////////////////////// |
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129 | // Fscl 100KHz 400KHz |
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130 | // Th_scl 4.0us 0.6us High period of SCL |
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131 | // Tl_scl 4.7us 1.3us Low period of SCL |
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132 | // Tsu:sta 4.7us 0.6us setup time for a repeated start condition |
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133 | // Tsu:sto 4.0us 0.6us setup time for a stop conditon |
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134 | // Tbuf 4.7us 1.3us Bus free time between a stop and start condition |
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135 | // |
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136 | |
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137 | // synopsys translate_off |
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138 | `include "timescale.v" |
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139 | // synopsys translate_on |
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140 | |
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141 | `include "i2c_master_defines.v" |
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142 | |
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143 | module i2c_master_bit_ctrl ( |
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144 | input clk, // system clock |
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145 | input rst, // synchronous active high reset |
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146 | input nReset, // asynchronous active low reset |
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147 | input ena, // core enable signal |
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148 | |
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149 | input [15:0] clk_cnt, // clock prescale value |
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150 | |
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151 | input [ 3:0] cmd, // command (from byte controller) |
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152 | output reg cmd_ack, // command complete acknowledge |
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153 | output reg busy, // i2c bus busy |
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154 | output reg al, // i2c bus arbitration lost |
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155 | |
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156 | input din, |
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157 | output reg dout, |
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158 | |
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159 | input scl_i, // i2c clock line input |
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160 | output scl_o, // i2c clock line output |
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161 | output reg scl_oen, // i2c clock line output enable (active low) |
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162 | input sda_i, // i2c data line input |
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163 | output sda_o, // i2c data line output |
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164 | output reg sda_oen // i2c data line output enable (active low) |
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165 | ); |
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166 | |
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167 | |
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168 | // |
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169 | // variable declarations |
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170 | // |
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171 | |
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172 | reg [ 1:0] cSCL, cSDA; // capture SCL and SDA |
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173 | reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs |
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174 | reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs |
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175 | reg dSCL, dSDA; // delayed versions of sSCL and sSDA |
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176 | reg dscl_oen; // delayed scl_oen |
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177 | reg sda_chk; // check SDA output (Multi-master arbitration) |
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178 | reg clk_en; // clock generation signals |
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179 | reg slave_wait; // slave inserts wait states |
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180 | reg [15:0] cnt; // clock divider counter (synthesis) |
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181 | reg [13:0] filter_cnt; // clock divider for filter |
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182 | |
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183 | |
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184 | // state machine variable |
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185 | reg [17:0] c_state; // synopsys enum_state |
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186 | |
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187 | // |
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188 | // module body |
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189 | // |
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190 | |
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191 | // whenever the slave is not ready it can delay the cycle by pulling SCL low |
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192 | // delay scl_oen |
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193 | always @(posedge clk) |
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194 | dscl_oen <= #1 scl_oen; |
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195 | |
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196 | // slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low |
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197 | // slave_wait remains asserted until the slave releases SCL |
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198 | always @(posedge clk or negedge nReset) |
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199 | if (!nReset) slave_wait <= 1'b0; |
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200 | else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL); |
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201 | |
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202 | // master drives SCL high, but another master pulls it low |
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203 | // master start counting down its low cycle now (clock synchronization) |
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204 | wire scl_sync = dSCL & ~sSCL & scl_oen; |
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205 | |
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206 | |
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207 | // generate clk enable signal |
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208 | always @(posedge clk or negedge nReset) |
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209 | if (~nReset) |
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210 | begin |
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211 | cnt <= #1 16'h0; |
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212 | clk_en <= #1 1'b1; |
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213 | end |
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214 | else if (rst || ~|cnt || !ena || scl_sync) |
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215 | begin |
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216 | cnt <= #1 clk_cnt; |
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217 | clk_en <= #1 1'b1; |
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218 | end |
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219 | else if (slave_wait) |
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220 | begin |
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221 | cnt <= #1 cnt; |
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222 | clk_en <= #1 1'b0; |
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223 | end |
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224 | else |
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225 | begin |
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226 | cnt <= #1 cnt - 16'h1; |
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227 | clk_en <= #1 1'b0; |
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228 | end |
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229 | |
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230 | |
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231 | // generate bus status controller |
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232 | |
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233 | // capture SDA and SCL |
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234 | // reduce metastability risk |
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235 | always @(posedge clk or negedge nReset) |
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236 | if (!nReset) |
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237 | begin |
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238 | cSCL <= #1 2'b00; |
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239 | cSDA <= #1 2'b00; |
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240 | end |
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241 | else if (rst) |
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242 | begin |
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243 | cSCL <= #1 2'b00; |
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244 | cSDA <= #1 2'b00; |
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245 | end |
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246 | else |
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247 | begin |
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248 | cSCL <= {cSCL[0],scl_i}; |
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249 | cSDA <= {cSDA[0],sda_i}; |
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250 | end |
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251 | |
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252 | |
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253 | // filter SCL and SDA signals; (attempt to) remove glitches |
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254 | always @(posedge clk or negedge nReset) |
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255 | if (!nReset ) filter_cnt <= 14'h0; |
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256 | else if (rst || !ena ) filter_cnt <= 14'h0; |
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257 | else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency |
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258 | else filter_cnt <= filter_cnt -1; |
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259 | |
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260 | |
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261 | always @(posedge clk or negedge nReset) |
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262 | if (!nReset) |
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263 | begin |
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264 | fSCL <= 3'b111; |
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265 | fSDA <= 3'b111; |
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266 | end |
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267 | else if (rst) |
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268 | begin |
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269 | fSCL <= 3'b111; |
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270 | fSDA <= 3'b111; |
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271 | end |
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272 | else if (~|filter_cnt) |
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273 | begin |
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274 | fSCL <= {fSCL[1:0],cSCL[1]}; |
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275 | fSDA <= {fSDA[1:0],cSDA[1]}; |
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276 | end |
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277 | |
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278 | |
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279 | // generate filtered SCL and SDA signals |
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280 | always @(posedge clk or negedge nReset) |
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281 | if (~nReset) |
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282 | begin |
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283 | sSCL <= #1 1'b1; |
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284 | sSDA <= #1 1'b1; |
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285 | |
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286 | dSCL <= #1 1'b1; |
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287 | dSDA <= #1 1'b1; |
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288 | end |
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289 | else if (rst) |
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290 | begin |
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291 | sSCL <= #1 1'b1; |
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292 | sSDA <= #1 1'b1; |
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293 | |
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294 | dSCL <= #1 1'b1; |
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295 | dSDA <= #1 1'b1; |
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296 | end |
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297 | else |
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298 | begin |
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299 | sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]); |
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300 | sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]); |
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301 | |
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302 | dSCL <= #1 sSCL; |
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303 | dSDA <= #1 sSDA; |
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304 | end |
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305 | |
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306 | // detect start condition => detect falling edge on SDA while SCL is high |
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307 | // detect stop condition => detect rising edge on SDA while SCL is high |
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308 | reg sta_condition; |
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309 | reg sto_condition; |
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310 | always @(posedge clk or negedge nReset) |
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311 | if (~nReset) |
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312 | begin |
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313 | sta_condition <= #1 1'b0; |
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314 | sto_condition <= #1 1'b0; |
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315 | end |
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316 | else if (rst) |
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317 | begin |
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318 | sta_condition <= #1 1'b0; |
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319 | sto_condition <= #1 1'b0; |
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320 | end |
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321 | else |
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322 | begin |
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323 | sta_condition <= #1 ~sSDA & dSDA & sSCL; |
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324 | sto_condition <= #1 sSDA & ~dSDA & sSCL; |
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325 | end |
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326 | |
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327 | |
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328 | // generate i2c bus busy signal |
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329 | always @(posedge clk or negedge nReset) |
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330 | if (!nReset) busy <= #1 1'b0; |
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331 | else if (rst ) busy <= #1 1'b0; |
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332 | else busy <= #1 (sta_condition | busy) & ~sto_condition; |
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333 | |
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334 | |
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335 | // generate arbitration lost signal |
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336 | // aribitration lost when: |
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337 | // 1) master drives SDA high, but the i2c bus is low |
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338 | // 2) stop detected while not requested |
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339 | reg cmd_stop; |
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340 | always @(posedge clk or negedge nReset) |
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341 | if (~nReset) |
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342 | cmd_stop <= #1 1'b0; |
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343 | else if (rst) |
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344 | cmd_stop <= #1 1'b0; |
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345 | else if (clk_en) |
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346 | cmd_stop <= #1 cmd == `I2C_CMD_STOP; |
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347 | |
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348 | always @(posedge clk or negedge nReset) |
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349 | if (~nReset) |
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350 | al <= #1 1'b0; |
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351 | else if (rst) |
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352 | al <= #1 1'b0; |
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353 | else |
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354 | al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop); |
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355 | |
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356 | |
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357 | // generate dout signal (store SDA on rising edge of SCL) |
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358 | always @(posedge clk) |
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359 | if (sSCL & ~dSCL) dout <= #1 sSDA; |
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360 | |
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361 | |
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362 | // generate statemachine |
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363 | |
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364 | // nxt_state decoder |
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365 | parameter [17:0] idle = 18'b0_0000_0000_0000_0000; |
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366 | parameter [17:0] start_a = 18'b0_0000_0000_0000_0001; |
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367 | parameter [17:0] start_b = 18'b0_0000_0000_0000_0010; |
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368 | parameter [17:0] start_c = 18'b0_0000_0000_0000_0100; |
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369 | parameter [17:0] start_d = 18'b0_0000_0000_0000_1000; |
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370 | parameter [17:0] start_e = 18'b0_0000_0000_0001_0000; |
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371 | parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000; |
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372 | parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000; |
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373 | parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000; |
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374 | parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000; |
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375 | parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000; |
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376 | parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000; |
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377 | parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000; |
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378 | parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000; |
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379 | parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000; |
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380 | parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000; |
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381 | parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000; |
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382 | parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000; |
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383 | |
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384 | always @(posedge clk or negedge nReset) |
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385 | if (!nReset) |
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386 | begin |
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387 | c_state <= #1 idle; |
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388 | cmd_ack <= #1 1'b0; |
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389 | scl_oen <= #1 1'b1; |
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390 | sda_oen <= #1 1'b1; |
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391 | sda_chk <= #1 1'b0; |
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392 | end |
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393 | else if (rst | al) |
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394 | begin |
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395 | c_state <= #1 idle; |
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396 | cmd_ack <= #1 1'b0; |
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397 | scl_oen <= #1 1'b1; |
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398 | sda_oen <= #1 1'b1; |
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399 | sda_chk <= #1 1'b0; |
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400 | end |
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401 | else |
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402 | begin |
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403 | cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle |
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404 | |
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405 | if (clk_en) |
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406 | case (c_state) // synopsys full_case parallel_case |
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407 | // idle state |
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408 | idle: |
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409 | begin |
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410 | case (cmd) // synopsys full_case parallel_case |
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411 | `I2C_CMD_START: c_state <= #1 start_a; |
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412 | `I2C_CMD_STOP: c_state <= #1 stop_a; |
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413 | `I2C_CMD_WRITE: c_state <= #1 wr_a; |
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414 | `I2C_CMD_READ: c_state <= #1 rd_a; |
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415 | default: c_state <= #1 idle; |
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416 | endcase |
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417 | |
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418 | scl_oen <= #1 scl_oen; // keep SCL in same state |
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419 | sda_oen <= #1 sda_oen; // keep SDA in same state |
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420 | sda_chk <= #1 1'b0; // don't check SDA output |
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421 | end |
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422 | |
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423 | // start |
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424 | start_a: |
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425 | begin |
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426 | c_state <= #1 start_b; |
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427 | scl_oen <= #1 scl_oen; // keep SCL in same state |
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428 | sda_oen <= #1 1'b1; // set SDA high |
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429 | sda_chk <= #1 1'b0; // don't check SDA output |
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430 | end |
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431 | |
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432 | start_b: |
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433 | begin |
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434 | c_state <= #1 start_c; |
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435 | scl_oen <= #1 1'b1; // set SCL high |
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436 | sda_oen <= #1 1'b1; // keep SDA high |
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437 | sda_chk <= #1 1'b0; // don't check SDA output |
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438 | end |
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439 | |
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440 | start_c: |
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441 | begin |
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442 | c_state <= #1 start_d; |
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443 | scl_oen <= #1 1'b1; // keep SCL high |
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444 | sda_oen <= #1 1'b0; // set SDA low |
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445 | sda_chk <= #1 1'b0; // don't check SDA output |
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446 | end |
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447 | |
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448 | start_d: |
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449 | begin |
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450 | c_state <= #1 start_e; |
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451 | scl_oen <= #1 1'b1; // keep SCL high |
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452 | sda_oen <= #1 1'b0; // keep SDA low |
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453 | sda_chk <= #1 1'b0; // don't check SDA output |
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454 | end |
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455 | |
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456 | start_e: |
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457 | begin |
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458 | c_state <= #1 idle; |
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459 | cmd_ack <= #1 1'b1; |
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460 | scl_oen <= #1 1'b0; // set SCL low |
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461 | sda_oen <= #1 1'b0; // keep SDA low |
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462 | sda_chk <= #1 1'b0; // don't check SDA output |
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463 | end |
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464 | |
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465 | // stop |
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466 | stop_a: |
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467 | begin |
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468 | c_state <= #1 stop_b; |
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469 | scl_oen <= #1 1'b0; // keep SCL low |
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470 | sda_oen <= #1 1'b0; // set SDA low |
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471 | sda_chk <= #1 1'b0; // don't check SDA output |
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472 | end |
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473 | |
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474 | stop_b: |
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475 | begin |
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476 | c_state <= #1 stop_c; |
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477 | scl_oen <= #1 1'b1; // set SCL high |
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478 | sda_oen <= #1 1'b0; // keep SDA low |
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479 | sda_chk <= #1 1'b0; // don't check SDA output |
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480 | end |
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481 | |
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482 | stop_c: |
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483 | begin |
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484 | c_state <= #1 stop_d; |
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485 | scl_oen <= #1 1'b1; // keep SCL high |
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486 | sda_oen <= #1 1'b0; // keep SDA low |
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487 | sda_chk <= #1 1'b0; // don't check SDA output |
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488 | end |
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489 | |
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490 | stop_d: |
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491 | begin |
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492 | c_state <= #1 idle; |
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493 | cmd_ack <= #1 1'b1; |
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494 | scl_oen <= #1 1'b1; // keep SCL high |
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495 | sda_oen <= #1 1'b1; // set SDA high |
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496 | sda_chk <= #1 1'b0; // don't check SDA output |
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497 | end |
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498 | |
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499 | // read |
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500 | rd_a: |
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501 | begin |
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502 | c_state <= #1 rd_b; |
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503 | scl_oen <= #1 1'b0; // keep SCL low |
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504 | sda_oen <= #1 1'b1; // tri-state SDA |
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505 | sda_chk <= #1 1'b0; // don't check SDA output |
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506 | end |
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507 | |
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508 | rd_b: |
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509 | begin |
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510 | c_state <= #1 rd_c; |
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511 | scl_oen <= #1 1'b1; // set SCL high |
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512 | sda_oen <= #1 1'b1; // keep SDA tri-stated |
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513 | sda_chk <= #1 1'b0; // don't check SDA output |
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514 | end |
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515 | |
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516 | rd_c: |
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517 | begin |
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518 | c_state <= #1 rd_d; |
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519 | scl_oen <= #1 1'b1; // keep SCL high |
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520 | sda_oen <= #1 1'b1; // keep SDA tri-stated |
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521 | sda_chk <= #1 1'b0; // don't check SDA output |
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522 | end |
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523 | |
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524 | rd_d: |
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525 | begin |
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526 | c_state <= #1 idle; |
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527 | cmd_ack <= #1 1'b1; |
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528 | scl_oen <= #1 1'b0; // set SCL low |
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529 | sda_oen <= #1 1'b1; // keep SDA tri-stated |
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530 | sda_chk <= #1 1'b0; // don't check SDA output |
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531 | end |
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532 | |
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533 | // write |
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534 | wr_a: |
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535 | begin |
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536 | c_state <= #1 wr_b; |
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537 | scl_oen <= #1 1'b0; // keep SCL low |
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538 | sda_oen <= #1 din; // set SDA |
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539 | sda_chk <= #1 1'b0; // don't check SDA output (SCL low) |
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540 | end |
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541 | |
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542 | wr_b: |
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543 | begin |
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544 | c_state <= #1 wr_c; |
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545 | scl_oen <= #1 1'b1; // set SCL high |
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546 | sda_oen <= #1 din; // keep SDA |
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547 | sda_chk <= #1 1'b0; // don't check SDA output yet |
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548 | // allow some time for SDA and SCL to settle |
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549 | end |
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550 | |
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551 | wr_c: |
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552 | begin |
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553 | c_state <= #1 wr_d; |
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554 | scl_oen <= #1 1'b1; // keep SCL high |
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555 | sda_oen <= #1 din; |
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556 | sda_chk <= #1 1'b1; // check SDA output |
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557 | end |
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558 | |
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559 | wr_d: |
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560 | begin |
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561 | c_state <= #1 idle; |
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562 | cmd_ack <= #1 1'b1; |
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563 | scl_oen <= #1 1'b0; // set SCL low |
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564 | sda_oen <= #1 din; |
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565 | sda_chk <= #1 1'b0; // don't check SDA output (SCL low) |
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566 | end |
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567 | |
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568 | endcase |
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569 | end |
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570 | |
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571 | |
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572 | // assign scl and sda output (always gnd) |
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573 | assign scl_o = 1'b0; |
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574 | assign sda_o = 1'b0; |
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575 | |
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576 | endmodule |
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