1 | ///////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// WISHBONE rev.B2 compliant I2C Master byte-controller //// |
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4 | //// //// |
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5 | //// //// |
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6 | //// Author: Richard Herveille //// |
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7 | //// richard@asics.ws //// |
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8 | //// www.asics.ws //// |
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9 | //// //// |
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10 | //// Downloaded from: http://www.opencores.org/projects/i2c/ //// |
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11 | //// //// |
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12 | ///////////////////////////////////////////////////////////////////// |
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13 | //// //// |
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14 | //// Copyright (C) 2001 Richard Herveille //// |
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15 | //// richard@asics.ws //// |
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16 | //// //// |
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17 | //// This source file may be used and distributed without //// |
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18 | //// restriction provided that this copyright statement is not //// |
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19 | //// removed from the file and that any derivative work contains //// |
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20 | //// the original copyright notice and the associated disclaimer.//// |
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21 | //// //// |
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22 | //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
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23 | //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
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24 | //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
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25 | //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
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26 | //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
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27 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
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28 | //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
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29 | //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
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30 | //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
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31 | //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
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32 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
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33 | //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
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34 | //// POSSIBILITY OF SUCH DAMAGE. //// |
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35 | //// //// |
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36 | ///////////////////////////////////////////////////////////////////// |
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37 | |
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38 | // CVS Log |
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39 | // |
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40 | // $Id: i2c_master_byte_ctrl.v,v 1.8 2009-01-19 20:29:26 rherveille Exp $ |
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41 | // |
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42 | // $Date: 2009-01-19 20:29:26 $ |
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43 | // $Revision: 1.8 $ |
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44 | // $Author: rherveille $ |
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45 | // $Locker: $ |
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46 | // $State: Exp $ |
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47 | // |
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48 | // Change History: |
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49 | // $Log: not supported by cvs2svn $ |
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50 | // Revision 1.7 2004/02/18 11:40:46 rherveille |
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51 | // Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. |
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52 | // |
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53 | // Revision 1.6 2003/08/09 07:01:33 rherveille |
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54 | // Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. |
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55 | // Fixed a potential bug in the byte controller's host-acknowledge generation. |
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56 | // |
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57 | // Revision 1.5 2002/12/26 15:02:32 rherveille |
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58 | // Core is now a Multimaster I2C controller |
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59 | // |
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60 | // Revision 1.4 2002/11/30 22:24:40 rherveille |
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61 | // Cleaned up code |
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62 | // |
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63 | // Revision 1.3 2001/11/05 11:59:25 rherveille |
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64 | // Fixed wb_ack_o generation bug. |
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65 | // Fixed bug in the byte_controller statemachine. |
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66 | // Added headers. |
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67 | // |
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68 | |
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69 | // synopsys translate_off |
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70 | `include "timescale.v" |
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71 | // synopsys translate_on |
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72 | |
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73 | `include "i2c_master_defines.v" |
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74 | |
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75 | module i2c_master_byte_ctrl ( |
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76 | clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din, |
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77 | cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen ); |
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78 | |
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79 | // |
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80 | // inputs & outputs |
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81 | // |
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82 | input clk; // master clock |
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83 | input rst; // synchronous active high reset |
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84 | input nReset; // asynchronous active low reset |
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85 | input ena; // core enable signal |
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86 | |
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87 | input [15:0] clk_cnt; // 4x SCL |
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88 | |
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89 | // control inputs |
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90 | input start; |
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91 | input stop; |
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92 | input read; |
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93 | input write; |
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94 | input ack_in; |
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95 | input [7:0] din; |
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96 | |
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97 | // status outputs |
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98 | output cmd_ack; |
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99 | reg cmd_ack; |
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100 | output ack_out; |
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101 | reg ack_out; |
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102 | output i2c_busy; |
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103 | output i2c_al; |
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104 | output [7:0] dout; |
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105 | |
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106 | // I2C signals |
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107 | input scl_i; |
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108 | output scl_o; |
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109 | output scl_oen; |
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110 | input sda_i; |
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111 | output sda_o; |
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112 | output sda_oen; |
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113 | |
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114 | |
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115 | // |
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116 | // Variable declarations |
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117 | // |
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118 | |
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119 | // statemachine |
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120 | parameter [4:0] ST_IDLE = 5'b0_0000; |
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121 | parameter [4:0] ST_START = 5'b0_0001; |
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122 | parameter [4:0] ST_READ = 5'b0_0010; |
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123 | parameter [4:0] ST_WRITE = 5'b0_0100; |
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124 | parameter [4:0] ST_ACK = 5'b0_1000; |
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125 | parameter [4:0] ST_STOP = 5'b1_0000; |
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126 | |
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127 | // signals for bit_controller |
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128 | reg [3:0] core_cmd; |
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129 | reg core_txd; |
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130 | wire core_ack, core_rxd; |
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131 | |
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132 | // signals for shift register |
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133 | reg [7:0] sr; //8bit shift register |
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134 | reg shift, ld; |
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135 | |
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136 | // signals for state machine |
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137 | wire go; |
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138 | reg [2:0] dcnt; |
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139 | wire cnt_done; |
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140 | |
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141 | // |
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142 | // Module body |
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143 | // |
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144 | |
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145 | // hookup bit_controller |
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146 | i2c_master_bit_ctrl bit_controller ( |
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147 | .clk ( clk ), |
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148 | .rst ( rst ), |
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149 | .nReset ( nReset ), |
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150 | .ena ( ena ), |
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151 | .clk_cnt ( clk_cnt ), |
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152 | .cmd ( core_cmd ), |
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153 | .cmd_ack ( core_ack ), |
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154 | .busy ( i2c_busy ), |
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155 | .al ( i2c_al ), |
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156 | .din ( core_txd ), |
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157 | .dout ( core_rxd ), |
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158 | .scl_i ( scl_i ), |
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159 | .scl_o ( scl_o ), |
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160 | .scl_oen ( scl_oen ), |
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161 | .sda_i ( sda_i ), |
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162 | .sda_o ( sda_o ), |
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163 | .sda_oen ( sda_oen ) |
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164 | ); |
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165 | |
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166 | // generate go-signal |
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167 | assign go = (read | write | stop) & ~cmd_ack; |
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168 | |
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169 | // assign dout output to shift-register |
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170 | assign dout = sr; |
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171 | |
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172 | // generate shift register |
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173 | always @(posedge clk or negedge nReset) |
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174 | if (!nReset) |
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175 | sr <= #1 8'h0; |
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176 | else if (rst) |
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177 | sr <= #1 8'h0; |
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178 | else if (ld) |
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179 | sr <= #1 din; |
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180 | else if (shift) |
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181 | sr <= #1 {sr[6:0], core_rxd}; |
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182 | |
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183 | // generate counter |
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184 | always @(posedge clk or negedge nReset) |
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185 | if (!nReset) |
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186 | dcnt <= #1 3'h0; |
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187 | else if (rst) |
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188 | dcnt <= #1 3'h0; |
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189 | else if (ld) |
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190 | dcnt <= #1 3'h7; |
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191 | else if (shift) |
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192 | dcnt <= #1 dcnt - 3'h1; |
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193 | |
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194 | assign cnt_done = ~(|dcnt); |
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195 | |
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196 | // |
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197 | // state machine |
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198 | // |
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199 | reg [4:0] c_state; // synopsys enum_state |
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200 | |
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201 | always @(posedge clk or negedge nReset) |
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202 | if (!nReset) |
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203 | begin |
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204 | core_cmd <= #1 `I2C_CMD_NOP; |
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205 | core_txd <= #1 1'b0; |
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206 | shift <= #1 1'b0; |
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207 | ld <= #1 1'b0; |
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208 | cmd_ack <= #1 1'b0; |
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209 | c_state <= #1 ST_IDLE; |
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210 | ack_out <= #1 1'b0; |
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211 | end |
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212 | else if (rst | i2c_al) |
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213 | begin |
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214 | core_cmd <= #1 `I2C_CMD_NOP; |
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215 | core_txd <= #1 1'b0; |
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216 | shift <= #1 1'b0; |
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217 | ld <= #1 1'b0; |
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218 | cmd_ack <= #1 1'b0; |
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219 | c_state <= #1 ST_IDLE; |
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220 | ack_out <= #1 1'b0; |
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221 | end |
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222 | else |
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223 | begin |
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224 | // initially reset all signals |
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225 | core_txd <= #1 sr[7]; |
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226 | shift <= #1 1'b0; |
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227 | ld <= #1 1'b0; |
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228 | cmd_ack <= #1 1'b0; |
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229 | |
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230 | case (c_state) // synopsys full_case parallel_case |
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231 | ST_IDLE: |
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232 | if (go) |
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233 | begin |
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234 | if (start) |
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235 | begin |
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236 | c_state <= #1 ST_START; |
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237 | core_cmd <= #1 `I2C_CMD_START; |
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238 | end |
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239 | else if (read) |
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240 | begin |
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241 | c_state <= #1 ST_READ; |
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242 | core_cmd <= #1 `I2C_CMD_READ; |
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243 | end |
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244 | else if (write) |
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245 | begin |
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246 | c_state <= #1 ST_WRITE; |
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247 | core_cmd <= #1 `I2C_CMD_WRITE; |
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248 | end |
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249 | else // stop |
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250 | begin |
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251 | c_state <= #1 ST_STOP; |
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252 | core_cmd <= #1 `I2C_CMD_STOP; |
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253 | end |
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254 | |
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255 | ld <= #1 1'b1; |
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256 | end |
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257 | |
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258 | ST_START: |
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259 | if (core_ack) |
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260 | begin |
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261 | if (read) |
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262 | begin |
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263 | c_state <= #1 ST_READ; |
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264 | core_cmd <= #1 `I2C_CMD_READ; |
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265 | end |
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266 | else |
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267 | begin |
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268 | c_state <= #1 ST_WRITE; |
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269 | core_cmd <= #1 `I2C_CMD_WRITE; |
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270 | end |
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271 | |
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272 | ld <= #1 1'b1; |
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273 | end |
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274 | |
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275 | ST_WRITE: |
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276 | if (core_ack) |
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277 | if (cnt_done) |
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278 | begin |
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279 | c_state <= #1 ST_ACK; |
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280 | core_cmd <= #1 `I2C_CMD_READ; |
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281 | end |
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282 | else |
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283 | begin |
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284 | c_state <= #1 ST_WRITE; // stay in same state |
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285 | core_cmd <= #1 `I2C_CMD_WRITE; // write next bit |
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286 | shift <= #1 1'b1; |
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287 | end |
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288 | |
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289 | ST_READ: |
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290 | if (core_ack) |
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291 | begin |
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292 | if (cnt_done) |
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293 | begin |
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294 | c_state <= #1 ST_ACK; |
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295 | core_cmd <= #1 `I2C_CMD_WRITE; |
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296 | end |
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297 | else |
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298 | begin |
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299 | c_state <= #1 ST_READ; // stay in same state |
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300 | core_cmd <= #1 `I2C_CMD_READ; // read next bit |
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301 | end |
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302 | |
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303 | shift <= #1 1'b1; |
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304 | core_txd <= #1 ack_in; |
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305 | end |
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306 | |
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307 | ST_ACK: |
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308 | if (core_ack) |
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309 | begin |
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310 | if (stop) |
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311 | begin |
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312 | c_state <= #1 ST_STOP; |
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313 | core_cmd <= #1 `I2C_CMD_STOP; |
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314 | end |
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315 | else |
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316 | begin |
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317 | c_state <= #1 ST_IDLE; |
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318 | core_cmd <= #1 `I2C_CMD_NOP; |
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319 | |
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320 | // generate command acknowledge signal |
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321 | cmd_ack <= #1 1'b1; |
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322 | end |
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323 | |
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324 | // assign ack_out output to bit_controller_rxd (contains last received bit) |
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325 | ack_out <= #1 core_rxd; |
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326 | |
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327 | core_txd <= #1 1'b1; |
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328 | end |
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329 | else |
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330 | core_txd <= #1 ack_in; |
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331 | |
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332 | ST_STOP: |
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333 | if (core_ack) |
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334 | begin |
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335 | c_state <= #1 ST_IDLE; |
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336 | core_cmd <= #1 `I2C_CMD_NOP; |
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337 | |
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338 | // generate command acknowledge signal |
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339 | cmd_ack <= #1 1'b1; |
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340 | end |
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341 | |
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342 | endcase |
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343 | end |
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344 | endmodule |
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