[1766] | 1 | --------------------------------------------------------------------- |
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| 2 | ---- ---- |
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| 3 | ---- WISHBONE revB2 I2C Master Core; bit-controller ---- |
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| 4 | ---- ---- |
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| 5 | ---- ---- |
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| 6 | ---- Author: Richard Herveille ---- |
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| 7 | ---- richard@asics.ws ---- |
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| 8 | ---- www.asics.ws ---- |
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| 9 | ---- ---- |
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| 10 | ---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- |
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| 11 | ---- ---- |
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| 12 | --------------------------------------------------------------------- |
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| 13 | ---- ---- |
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| 14 | ---- Copyright (C) 2000 Richard Herveille ---- |
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| 15 | ---- richard@asics.ws ---- |
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| 16 | ---- ---- |
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| 17 | ---- This source file may be used and distributed without ---- |
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| 18 | ---- restriction provided that this copyright statement is not ---- |
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| 19 | ---- removed from the file and that any derivative work contains ---- |
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| 20 | ---- the original copyright notice and the associated disclaimer.---- |
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| 21 | ---- ---- |
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| 22 | ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- |
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| 23 | ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- |
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| 24 | ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- |
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| 25 | ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- |
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| 26 | ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- |
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| 27 | ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- |
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| 28 | ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- |
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| 29 | ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- |
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| 30 | ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- |
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| 31 | ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- |
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| 32 | ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- |
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| 33 | ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- |
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| 34 | ---- POSSIBILITY OF SUCH DAMAGE. ---- |
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| 35 | ---- ---- |
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| 36 | --------------------------------------------------------------------- |
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| 37 | |
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| 38 | -- CVS Log |
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| 39 | -- |
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| 40 | -- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $ |
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| 41 | -- |
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| 42 | -- $Date: 2009-02-04 20:17:34 $ |
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| 43 | -- $Revision: 1.17 $ |
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| 44 | -- $Author: rherveille $ |
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| 45 | -- $Locker: $ |
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| 46 | -- $State: Exp $ |
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| 47 | -- |
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| 48 | -- Change History: |
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| 49 | -- $Log: not supported by cvs2svn $ |
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| 50 | -- Revision 1.16 2009/01/20 20:40:36 rherveille |
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| 51 | -- Fixed type iscl_oen instead of scl_oen |
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| 52 | -- |
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| 53 | -- Revision 1.15 2009/01/20 10:34:51 rherveille |
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| 54 | -- Added SCL clock synchronization logic |
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| 55 | -- Fixed slave_wait signal generation |
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| 56 | -- |
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| 57 | -- Revision 1.14 2006/10/11 12:10:13 rherveille |
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| 58 | -- Added missing semicolons ';' on endif |
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| 59 | -- |
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| 60 | -- Revision 1.13 2006/10/06 10:48:24 rherveille |
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| 61 | -- fixed short scl high pulse after clock stretch |
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| 62 | -- |
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| 63 | -- Revision 1.12 2004/05/07 11:53:31 rherveille |
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| 64 | -- Fixed previous fix :) Made a variable vs signal mistake. |
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| 65 | -- |
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| 66 | -- Revision 1.11 2004/05/07 11:04:00 rherveille |
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| 67 | -- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. |
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| 68 | -- |
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| 69 | -- Revision 1.10 2004/02/27 07:49:43 rherveille |
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| 70 | -- Fixed a bug in the arbitration-lost signal generation. VHDL version only. |
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| 71 | -- |
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| 72 | -- Revision 1.9 2003/08/12 14:48:37 rherveille |
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| 73 | -- Forgot an 'end if' :-/ |
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| 74 | -- |
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| 75 | -- Revision 1.8 2003/08/09 07:01:13 rherveille |
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| 76 | -- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. |
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| 77 | -- Fixed a potential bug in the byte controller's host-acknowledge generation. |
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| 78 | -- |
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| 79 | -- Revision 1.7 2003/02/05 00:06:02 rherveille |
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| 80 | -- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. |
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| 81 | -- |
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| 82 | -- Revision 1.6 2003/02/01 02:03:06 rherveille |
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| 83 | -- Fixed a few 'arbitration lost' bugs. VHDL version only. |
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| 84 | -- |
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| 85 | -- Revision 1.5 2002/12/26 16:05:47 rherveille |
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| 86 | -- Core is now a Multimaster I2C controller. |
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| 87 | -- |
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| 88 | -- Revision 1.4 2002/11/30 22:24:37 rherveille |
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| 89 | -- Cleaned up code |
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| 90 | -- |
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| 91 | -- Revision 1.3 2002/10/30 18:09:53 rherveille |
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| 92 | -- Fixed some reported minor start/stop generation timing issuess. |
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| 93 | -- |
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| 94 | -- Revision 1.2 2002/06/15 07:37:04 rherveille |
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| 95 | -- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. |
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| 96 | -- |
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| 97 | -- Revision 1.1 2001/11/05 12:02:33 rherveille |
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| 98 | -- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. |
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| 99 | -- Code updated, is now up-to-date to doc. rev.0.4. |
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| 100 | -- Added headers. |
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| 101 | -- |
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| 102 | |
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| 103 | |
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| 104 | -- |
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| 105 | ------------------------------------- |
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| 106 | -- Bit controller section |
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| 107 | ------------------------------------ |
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| 108 | -- |
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| 109 | -- Translate simple commands into SCL/SDA transitions |
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| 110 | -- Each command has 5 states, A/B/C/D/idle |
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| 111 | -- |
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| 112 | -- start: SCL ~~~~~~~~~~~~~~\____ |
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| 113 | -- SDA XX/~~~~~~~\______ |
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| 114 | -- x | A | B | C | D | i |
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| 115 | -- |
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| 116 | -- repstart SCL ______/~~~~~~~\___ |
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| 117 | -- SDA __/~~~~~~~\______ |
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| 118 | -- x | A | B | C | D | i |
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| 119 | -- |
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| 120 | -- stop SCL _______/~~~~~~~~~~~ |
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| 121 | -- SDA ==\___________/~~~~~ |
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| 122 | -- x | A | B | C | D | i |
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| 123 | -- |
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| 124 | --- write SCL ______/~~~~~~~\____ |
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| 125 | -- SDA XXX===============XX |
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| 126 | -- x | A | B | C | D | i |
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| 127 | -- |
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| 128 | --- read SCL ______/~~~~~~~\____ |
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| 129 | -- SDA XXXXXXX=XXXXXXXXXXX |
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| 130 | -- x | A | B | C | D | i |
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| 131 | -- |
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| 132 | |
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| 133 | -- Timing: Normal mode Fast mode |
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| 134 | ----------------------------------------------------------------- |
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| 135 | -- Fscl 100KHz 400KHz |
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| 136 | -- Th_scl 4.0us 0.6us High period of SCL |
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| 137 | -- Tl_scl 4.7us 1.3us Low period of SCL |
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| 138 | -- Tsu:sta 4.7us 0.6us setup time for a repeated start condition |
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| 139 | -- Tsu:sto 4.0us 0.6us setup time for a stop conditon |
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| 140 | -- Tbuf 4.7us 1.3us Bus free time between a stop and start condition |
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| 141 | -- |
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| 142 | |
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| 143 | library ieee; |
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| 144 | use ieee.std_logic_1164.all; |
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| 145 | use ieee.numeric_std.all; |
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| 146 | |
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| 147 | entity i2c_master_bit_ctrl is |
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| 148 | port ( |
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| 149 | clk : in std_logic; |
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| 150 | rst : in std_logic; |
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| 151 | nReset : in std_logic; |
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| 152 | ena : in std_logic; -- core enable signal |
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| 153 | |
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| 154 | clk_cnt : in unsigned(15 downto 0); -- clock prescale value |
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| 155 | |
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| 156 | cmd : in std_logic_vector(3 downto 0); |
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| 157 | cmd_ack : out std_logic; -- command completed |
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| 158 | busy : out std_logic; -- i2c bus busy |
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| 159 | al : out std_logic; -- arbitration lost |
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| 160 | |
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| 161 | din : in std_logic; |
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| 162 | dout : out std_logic; |
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| 163 | |
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| 164 | -- i2c lines |
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| 165 | scl_i : in std_logic; -- i2c clock line input |
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| 166 | scl_o : out std_logic; -- i2c clock line output |
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| 167 | scl_oen : out std_logic; -- i2c clock line output enable, active low |
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| 168 | sda_i : in std_logic; -- i2c data line input |
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| 169 | sda_o : out std_logic; -- i2c data line output |
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| 170 | sda_oen : out std_logic -- i2c data line output enable, active low |
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| 171 | ); |
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| 172 | end entity i2c_master_bit_ctrl; |
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| 173 | |
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| 174 | architecture structural of i2c_master_bit_ctrl is |
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| 175 | constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; |
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| 176 | constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; |
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| 177 | constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; |
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| 178 | constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; |
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| 179 | constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; |
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| 180 | |
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| 181 | type states is (idle, start_a, start_b, start_c, start_d, start_e, |
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| 182 | stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); |
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| 183 | signal c_state : states; |
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| 184 | |
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| 185 | signal iscl_oen, isda_oen : std_logic; -- internal I2C lines |
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| 186 | signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) |
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| 187 | signal dscl_oen : std_logic; -- delayed scl_oen signals |
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| 188 | signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs |
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| 189 | signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA |
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| 190 | signal clk_en : std_logic; -- statemachine clock enable |
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| 191 | signal scl_sync, slave_wait : std_logic; -- clock generation signals |
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| 192 | signal ial : std_logic; -- internal arbitration lost signal |
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| 193 | signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) |
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| 194 | |
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| 195 | begin |
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| 196 | -- whenever the slave is not ready it can delay the cycle by pulling SCL low |
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| 197 | -- delay scl_oen |
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| 198 | process (clk, nReset) |
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| 199 | begin |
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| 200 | if (nReset = '0') then |
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| 201 | dscl_oen <= '0'; |
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| 202 | elsif (clk'event and clk = '1') then |
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| 203 | dscl_oen <= iscl_oen; |
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| 204 | end if; |
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| 205 | end process; |
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| 206 | |
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| 207 | -- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low |
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| 208 | -- slave_wait remains asserted until the slave releases SCL |
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| 209 | process (clk, nReset) |
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| 210 | begin |
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| 211 | if (nReset = '0') then |
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| 212 | slave_wait <= '0'; |
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| 213 | elsif (clk'event and clk = '1') then |
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| 214 | slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL); |
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| 215 | end if; |
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| 216 | end process; |
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| 217 | |
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| 218 | -- master drives SCL high, but another master pulls it low |
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| 219 | -- master start counting down its low cycle now (clock synchronization) |
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| 220 | scl_sync <= dSCL and not sSCL and iscl_oen; |
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| 221 | |
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| 222 | -- generate clk enable signal |
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| 223 | gen_clken: process(clk, nReset) |
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| 224 | begin |
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| 225 | if (nReset = '0') then |
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| 226 | cnt <= (others => '0'); |
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| 227 | clk_en <= '1'; |
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| 228 | elsif (clk'event and clk = '1') then |
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| 229 | if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then |
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| 230 | cnt <= clk_cnt; |
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| 231 | clk_en <= '1'; |
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| 232 | elsif (slave_wait = '1') then |
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| 233 | cnt <= cnt; |
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| 234 | clk_en <= '0'; |
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| 235 | else |
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| 236 | cnt <= cnt -1; |
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| 237 | clk_en <= '0'; |
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| 238 | end if; |
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| 239 | end if; |
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| 240 | end process gen_clken; |
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| 241 | |
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| 242 | |
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| 243 | -- generate bus status controller |
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| 244 | bus_status_ctrl: block |
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| 245 | signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL |
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| 246 | signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA |
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| 247 | signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter |
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| 248 | signal sta_condition : std_logic; -- start detected |
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| 249 | signal sto_condition : std_logic; -- stop detected |
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| 250 | signal cmd_stop : std_logic; -- STOP command |
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| 251 | signal ibusy : std_logic; -- internal busy signal |
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| 252 | begin |
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| 253 | -- capture SCL and SDA |
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| 254 | capture_scl_sda: process(clk, nReset) |
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| 255 | begin |
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| 256 | if (nReset = '0') then |
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| 257 | cSCL <= "00"; |
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| 258 | cSDA <= "00"; |
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| 259 | elsif (clk'event and clk = '1') then |
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| 260 | if (rst = '1') then |
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| 261 | cSCL <= "00"; |
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| 262 | cSDA <= "00"; |
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| 263 | else |
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| 264 | cSCL <= (cSCL(0) & scl_i); |
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| 265 | cSDA <= (cSDA(0) & sda_i); |
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| 266 | end if; |
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| 267 | end if; |
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| 268 | end process capture_scl_sda; |
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| 269 | |
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| 270 | -- filter SCL and SDA; (attempt to) remove glitches |
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| 271 | filter_divider: process(clk, nReset) |
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| 272 | begin |
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| 273 | if (nReset = '0') then |
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| 274 | filter_cnt <= (others => '0'); |
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| 275 | elsif (clk'event and clk = '1') then |
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| 276 | if ( (rst = '1') or (ena = '0') ) then |
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| 277 | filter_cnt <= (others => '0'); |
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| 278 | elsif (filter_cnt = 0) then |
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| 279 | filter_cnt <= clk_cnt(15 downto 2); |
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| 280 | else |
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| 281 | filter_cnt <= filter_cnt -1; |
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| 282 | end if; |
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| 283 | end if; |
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| 284 | end process filter_divider; |
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| 285 | |
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| 286 | filter_scl_sda: process(clk, nReset) |
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| 287 | begin |
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| 288 | if (nReset = '0') then |
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| 289 | fSCL <= (others => '1'); |
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| 290 | fSDA <= (others => '1'); |
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| 291 | elsif (clk'event and clk = '1') then |
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| 292 | if (rst = '1') then |
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| 293 | fSCL <= (others => '1'); |
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| 294 | fSDA <= (others => '1'); |
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| 295 | elsif (filter_cnt = 0) then |
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| 296 | fSCL <= (fSCL(1 downto 0) & cSCL(1)); |
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| 297 | fSDA <= (fSDA(1 downto 0) & cSDA(1)); |
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| 298 | end if; |
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| 299 | end if; |
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| 300 | end process filter_scl_sda; |
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| 301 | |
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| 302 | -- generate filtered SCL and SDA signals |
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| 303 | scl_sda: process(clk, nReset) |
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| 304 | begin |
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| 305 | if (nReset = '0') then |
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| 306 | sSCL <= '1'; |
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| 307 | sSDA <= '1'; |
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| 308 | |
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| 309 | dSCL <= '1'; |
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| 310 | dSDA <= '1'; |
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| 311 | elsif (clk'event and clk = '1') then |
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| 312 | if (rst = '1') then |
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| 313 | sSCL <= '1'; |
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| 314 | sSDA <= '1'; |
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| 315 | |
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| 316 | dSCL <= '1'; |
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| 317 | dSDA <= '1'; |
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| 318 | else |
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| 319 | sSCL <= (fSCL(2) and fSCL(1)) or |
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| 320 | (fSCL(2) and fSCL(0)) or |
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| 321 | (fSCL(1) and fSCL(0)); |
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| 322 | sSDA <= (fSDA(2) and fSDA(1)) or |
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| 323 | (fSDA(2) and fSDA(0)) or |
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| 324 | (fSDA(1) and fSDA(0)); |
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| 325 | |
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| 326 | dSCL <= sSCL; |
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| 327 | dSDA <= sSDA; |
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| 328 | end if; |
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| 329 | end if; |
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| 330 | end process scl_sda; |
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| 331 | |
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| 332 | |
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| 333 | -- detect start condition => detect falling edge on SDA while SCL is high |
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| 334 | -- detect stop condition => detect rising edge on SDA while SCL is high |
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| 335 | detect_sta_sto: process(clk, nReset) |
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| 336 | begin |
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| 337 | if (nReset = '0') then |
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| 338 | sta_condition <= '0'; |
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| 339 | sto_condition <= '0'; |
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| 340 | elsif (clk'event and clk = '1') then |
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| 341 | if (rst = '1') then |
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| 342 | sta_condition <= '0'; |
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| 343 | sto_condition <= '0'; |
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| 344 | else |
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| 345 | sta_condition <= (not sSDA and dSDA) and sSCL; |
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| 346 | sto_condition <= (sSDA and not dSDA) and sSCL; |
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| 347 | end if; |
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| 348 | end if; |
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| 349 | end process detect_sta_sto; |
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| 350 | |
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| 351 | |
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| 352 | -- generate i2c-bus busy signal |
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| 353 | gen_busy: process(clk, nReset) |
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| 354 | begin |
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| 355 | if (nReset = '0') then |
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| 356 | ibusy <= '0'; |
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| 357 | elsif (clk'event and clk = '1') then |
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| 358 | if (rst = '1') then |
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| 359 | ibusy <= '0'; |
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| 360 | else |
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| 361 | ibusy <= (sta_condition or ibusy) and not sto_condition; |
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| 362 | end if; |
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| 363 | end if; |
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| 364 | end process gen_busy; |
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| 365 | busy <= ibusy; |
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| 366 | |
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| 367 | |
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| 368 | -- generate arbitration lost signal |
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| 369 | -- aribitration lost when: |
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| 370 | -- 1) master drives SDA high, but the i2c bus is low |
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| 371 | -- 2) stop detected while not requested (detect during 'idle' state) |
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| 372 | gen_al: process(clk, nReset) |
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| 373 | begin |
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| 374 | if (nReset = '0') then |
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| 375 | cmd_stop <= '0'; |
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| 376 | ial <= '0'; |
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| 377 | elsif (clk'event and clk = '1') then |
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| 378 | if (rst = '1') then |
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| 379 | cmd_stop <= '0'; |
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| 380 | ial <= '0'; |
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| 381 | else |
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| 382 | if (clk_en = '1') then |
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| 383 | if (cmd = I2C_CMD_STOP) then |
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| 384 | cmd_stop <= '1'; |
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| 385 | else |
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| 386 | cmd_stop <= '0'; |
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| 387 | end if; |
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| 388 | end if; |
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| 389 | |
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| 390 | if (c_state = idle) then |
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| 391 | ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop); |
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| 392 | else |
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| 393 | ial <= (sda_chk and not sSDA and isda_oen); |
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| 394 | end if; |
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| 395 | end if; |
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| 396 | end if; |
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| 397 | end process gen_al; |
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| 398 | al <= ial; |
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| 399 | |
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| 400 | |
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| 401 | -- generate dout signal, store dout on rising edge of SCL |
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| 402 | gen_dout: process(clk, nReset) |
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| 403 | begin |
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| 404 | if (nReset = '0') then |
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| 405 | dout <= '0'; |
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| 406 | elsif (clk'event and clk = '1') then |
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| 407 | if (sSCL = '1' and dSCL = '0') then |
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| 408 | dout <= sSDA; |
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| 409 | end if; |
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| 410 | end if; |
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| 411 | end process gen_dout; |
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| 412 | end block bus_status_ctrl; |
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| 413 | |
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| 414 | |
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| 415 | -- generate statemachine |
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| 416 | nxt_state_decoder : process (clk, nReset) |
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| 417 | begin |
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| 418 | if (nReset = '0') then |
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| 419 | c_state <= idle; |
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| 420 | cmd_ack <= '0'; |
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| 421 | iscl_oen <= '1'; |
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| 422 | isda_oen <= '1'; |
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| 423 | sda_chk <= '0'; |
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| 424 | elsif (clk'event and clk = '1') then |
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| 425 | if (rst = '1' or ial = '1') then |
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| 426 | c_state <= idle; |
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| 427 | cmd_ack <= '0'; |
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| 428 | iscl_oen <= '1'; |
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| 429 | isda_oen <= '1'; |
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| 430 | sda_chk <= '0'; |
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| 431 | else |
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| 432 | cmd_ack <= '0'; -- default no acknowledge |
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| 433 | |
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| 434 | if (clk_en = '1') then |
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| 435 | case (c_state) is |
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| 436 | -- idle |
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| 437 | when idle => |
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| 438 | case cmd is |
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| 439 | when I2C_CMD_START => c_state <= start_a; |
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| 440 | when I2C_CMD_STOP => c_state <= stop_a; |
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| 441 | when I2C_CMD_WRITE => c_state <= wr_a; |
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| 442 | when I2C_CMD_READ => c_state <= rd_a; |
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| 443 | when others => c_state <= idle; -- NOP command |
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| 444 | end case; |
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| 445 | |
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| 446 | iscl_oen <= iscl_oen; -- keep SCL in same state |
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| 447 | isda_oen <= isda_oen; -- keep SDA in same state |
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| 448 | sda_chk <= '0'; -- don't check SDA |
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| 449 | |
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| 450 | -- start |
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| 451 | when start_a => |
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| 452 | c_state <= start_b; |
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| 453 | iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start) |
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| 454 | isda_oen <= '1'; -- set SDA high |
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| 455 | sda_chk <= '0'; -- don't check SDA |
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| 456 | |
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| 457 | when start_b => |
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| 458 | c_state <= start_c; |
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| 459 | iscl_oen <= '1'; -- set SCL high |
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| 460 | isda_oen <= '1'; -- keep SDA high |
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| 461 | sda_chk <= '0'; -- don't check SDA |
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| 462 | |
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| 463 | when start_c => |
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| 464 | c_state <= start_d; |
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| 465 | iscl_oen <= '1'; -- keep SCL high |
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| 466 | isda_oen <= '0'; -- set SDA low |
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| 467 | sda_chk <= '0'; -- don't check SDA |
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| 468 | |
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| 469 | when start_d => |
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| 470 | c_state <= start_e; |
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| 471 | iscl_oen <= '1'; -- keep SCL high |
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| 472 | isda_oen <= '0'; -- keep SDA low |
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| 473 | sda_chk <= '0'; -- don't check SDA |
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| 474 | |
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| 475 | when start_e => |
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| 476 | c_state <= idle; |
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| 477 | cmd_ack <= '1'; -- command completed |
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| 478 | iscl_oen <= '0'; -- set SCL low |
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| 479 | isda_oen <= '0'; -- keep SDA low |
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| 480 | sda_chk <= '0'; -- don't check SDA |
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| 481 | |
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| 482 | -- stop |
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| 483 | when stop_a => |
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| 484 | c_state <= stop_b; |
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| 485 | iscl_oen <= '0'; -- keep SCL low |
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| 486 | isda_oen <= '0'; -- set SDA low |
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| 487 | sda_chk <= '0'; -- don't check SDA |
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| 488 | |
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| 489 | when stop_b => |
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| 490 | c_state <= stop_c; |
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| 491 | iscl_oen <= '1'; -- set SCL high |
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| 492 | isda_oen <= '0'; -- keep SDA low |
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| 493 | sda_chk <= '0'; -- don't check SDA |
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| 494 | |
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| 495 | when stop_c => |
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| 496 | c_state <= stop_d; |
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| 497 | iscl_oen <= '1'; -- keep SCL high |
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| 498 | isda_oen <= '0'; -- keep SDA low |
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| 499 | sda_chk <= '0'; -- don't check SDA |
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| 500 | |
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| 501 | when stop_d => |
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| 502 | c_state <= idle; |
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| 503 | cmd_ack <= '1'; -- command completed |
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| 504 | iscl_oen <= '1'; -- keep SCL high |
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| 505 | isda_oen <= '1'; -- set SDA high |
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| 506 | sda_chk <= '0'; -- don't check SDA |
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| 507 | |
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| 508 | -- read |
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| 509 | when rd_a => |
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| 510 | c_state <= rd_b; |
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| 511 | iscl_oen <= '0'; -- keep SCL low |
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| 512 | isda_oen <= '1'; -- tri-state SDA |
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| 513 | sda_chk <= '0'; -- don't check SDA |
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| 514 | |
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| 515 | when rd_b => |
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| 516 | c_state <= rd_c; |
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| 517 | iscl_oen <= '1'; -- set SCL high |
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| 518 | isda_oen <= '1'; -- tri-state SDA |
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| 519 | sda_chk <= '0'; -- don't check SDA |
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| 520 | |
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| 521 | when rd_c => |
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| 522 | c_state <= rd_d; |
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| 523 | iscl_oen <= '1'; -- keep SCL high |
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| 524 | isda_oen <= '1'; -- tri-state SDA |
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| 525 | sda_chk <= '0'; -- don't check SDA |
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| 526 | |
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| 527 | when rd_d => |
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| 528 | c_state <= idle; |
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| 529 | cmd_ack <= '1'; -- command completed |
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| 530 | iscl_oen <= '0'; -- set SCL low |
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| 531 | isda_oen <= '1'; -- tri-state SDA |
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| 532 | sda_chk <= '0'; -- don't check SDA |
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| 533 | |
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| 534 | -- write |
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| 535 | when wr_a => |
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| 536 | c_state <= wr_b; |
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| 537 | iscl_oen <= '0'; -- keep SCL low |
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| 538 | isda_oen <= din; -- set SDA |
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| 539 | sda_chk <= '0'; -- don't check SDA (SCL low) |
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| 540 | |
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| 541 | when wr_b => |
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| 542 | c_state <= wr_c; |
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| 543 | iscl_oen <= '1'; -- set SCL high |
---|
| 544 | isda_oen <= din; -- keep SDA |
---|
| 545 | sda_chk <= '0'; -- don't check SDA yet |
---|
| 546 | -- Allow some more time for SDA and SCL to settle |
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| 547 | |
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| 548 | when wr_c => |
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| 549 | c_state <= wr_d; |
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| 550 | iscl_oen <= '1'; -- keep SCL high |
---|
| 551 | isda_oen <= din; -- keep SDA |
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| 552 | sda_chk <= '1'; -- check SDA |
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| 553 | |
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| 554 | when wr_d => |
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| 555 | c_state <= idle; |
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| 556 | cmd_ack <= '1'; -- command completed |
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| 557 | iscl_oen <= '0'; -- set SCL low |
---|
| 558 | isda_oen <= din; -- keep SDA |
---|
| 559 | sda_chk <= '0'; -- don't check SDA (SCL low) |
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| 560 | |
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| 561 | when others => |
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| 562 | |
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| 563 | end case; |
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| 564 | end if; |
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| 565 | end if; |
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| 566 | end if; |
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| 567 | end process nxt_state_decoder; |
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| 568 | |
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| 569 | |
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| 570 | -- assign outputs |
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| 571 | scl_o <= '0'; |
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| 572 | scl_oen <= iscl_oen; |
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| 573 | sda_o <= '0'; |
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| 574 | sda_oen <= isda_oen; |
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| 575 | end architecture structural; |
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| 576 | |
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