1 | BEGIN w3_sd_spi
|
---|
2 |
|
---|
3 | ## Peripheral Options
|
---|
4 | OPTION IPTYPE = PERIPHERAL
|
---|
5 | OPTION IMP_NETLIST = TRUE
|
---|
6 | OPTION HDL = MIXED
|
---|
7 | OPTION IP_GROUP = MICROBLAZE:USER
|
---|
8 | OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
|
---|
9 | OPTION DESC = WARP v3 AD Controller (AXI)
|
---|
10 | OPTION LONG_DESC="Implements SD/SPI master and I/O for controlling FPGA configuration CPLD on WARP v3"
|
---|
11 |
|
---|
12 | IO_INTERFACE IO_IF = SPI_PINS, IO_TYPE = SPI_PINS
|
---|
13 |
|
---|
14 | ## Bus Interfaces
|
---|
15 | BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
|
---|
16 |
|
---|
17 | ## Generics for VHDL or Parameters for Verilog
|
---|
18 | PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
|
---|
19 | PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
|
---|
20 | PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
|
---|
21 | PARAMETER C_USE_WSTRB = 0, DT = INTEGER
|
---|
22 | PARAMETER C_DPHASE_TIMEOUT = 0, DT = INTEGER
|
---|
23 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
|
---|
24 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
|
---|
25 | PARAMETER C_FAMILY = virtex6, DT = STRING
|
---|
26 | PARAMETER C_NUM_REG = 1, DT = INTEGER
|
---|
27 | PARAMETER C_NUM_MEM = 1, DT = INTEGER
|
---|
28 | PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
|
---|
29 | PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
|
---|
30 | PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
|
---|
31 |
|
---|
32 | ## Ports
|
---|
33 | PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
|
---|
34 | PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
|
---|
35 | PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
|
---|
36 | PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
|
---|
37 | PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
|
---|
38 | PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
|
---|
39 | PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
|
---|
40 | PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
|
---|
41 | PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
|
---|
42 | PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
|
---|
43 | PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
|
---|
44 | PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
|
---|
45 | PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
|
---|
46 | PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
|
---|
47 | PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
|
---|
48 | PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
|
---|
49 | PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
|
---|
50 | PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
|
---|
51 | PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
|
---|
52 |
|
---|
53 | PORT spi_sclk = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_sclk
|
---|
54 | PORT spi_cs_n = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_cs_n
|
---|
55 | PORT spi_mosi = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_mosi
|
---|
56 | PORT spi_miso = "", DIR = I, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_miso
|
---|
57 |
|
---|
58 | PORT spi_enable_n = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_enable_n
|
---|
59 | PORT cfg_req_n = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_cfg_req_n
|
---|
60 | PORT cfg_sel = "", DIR = O, VEC = [2:0], IO_IF=SPI_PINS, IO_IS=SPI_PINS_cfg_sel
|
---|
61 |
|
---|
62 | END
|
---|