Reading FPGA DNA

Macros
#define	userio_read_fpga_dna_lsb(baseaddr)   Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET)
#define	userio_read_fpga_dna_msb(baseaddr)   Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET)

Detailed Description

Every Virtex-6 FPGA has a unique "DNA" value embedded in the device. The w3_userio core implements logic to read this value into software-accessible registers. The DNA value is 56 bits, so two 32-bit registers are used to store the full value.

Hardware requirements:

• A clock signal slower than 100MHz must be connected to the w3_userio core DNA_Port_Clk port
• The w3_userio core parameter INCLUDE_DNA_READ_LOGIC must be enabled

If both requirements aren't met the DNA register values are undefined.

The FPGA DNA value is also stored in the WARP v3 board EEPROM. Refer to the user guide EEPROM page for details.

Macro Definition Documentation

#define userio_read_fpga_dna_lsb

(

baseaddr

)

Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET)

Returns the 32 LSB of the FPGA DNA.

#define userio_read_fpga_dna_msb

(

baseaddr

)

Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET)

Returns the 24 MSB of the FPGA DNA.