[1042] | 1 | ## Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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| 2 |
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| 3 | ## You may copy and modify these files for your own internal use solely with
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| 4 | ## Xilinx programmable logic devices and Xilinx EDK system or create IP
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| 5 | ## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
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| 6 | ## No rights are granted to distribute any files unless they are distributed in
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| 7 | ## Xilinx programmable logic devices.
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| 8 |
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| 9 | BEGIN warp_timer_plbw
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| 10 |
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| 11 | ## Peripheral Options
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| 12 | OPTION RUN_NGCBUILD = TRUE
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| 13 | OPTION IMP_NETLIST = TRUE
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| 14 | OPTION STYLE = MIX
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| 15 | OPTION HDL = MIXED
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| 16 | OPTION IPTYPE = PERIPHERAL
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| 17 | OPTION LAST_UPDATED = 10.1.2.1250
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| 18 | OPTION USAGE_LEVEL = BASE_USER
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| 19 |
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| 20 |
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| 21 | ## Bus Interfaces
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| 22 | BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
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| 23 |
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| 24 | ## Generics for VHDL or Parameters for Verilog
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| 25 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x1000, ASSIGNMENT = REQUIRE
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| 26 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = HIGH, PAIR = C_BASEADDR, ASSIGNMENT = REQUIRE
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| 27 | PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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| 28 | PARAMETER C_SPLB_DWIDTH = 32, DT = INTEGER, BUS = SPLB
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| 29 | PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB
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| 30 | PARAMETER C_SPLB_MID_WIDTH = 1, DT = INTEGER, BUS = SPLB
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| 31 | PARAMETER C_SPLB_NUM_MASTERS = 1, DT = INTEGER, BUS = SPLB
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| 32 | PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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| 33 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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| 34 |
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| 35 | # Memory Map Information
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| 36 | # From Registers
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| 37 | PARAMETER C_MEMMAP_TIMER0_TIMELEFT = 0x814, DT = integer, ASSIGNMENT = CONSTANT
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| 38 | PARAMETER C_MEMMAP_TIMER0_TIMELEFT_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 39 | PARAMETER C_MEMMAP_TIMER0_TIMELEFT_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 40 | PARAMETER C_MEMMAP_TIMER1_TIMELEFT = 0x818, DT = integer, ASSIGNMENT = CONSTANT
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| 41 | PARAMETER C_MEMMAP_TIMER1_TIMELEFT_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 42 | PARAMETER C_MEMMAP_TIMER1_TIMELEFT_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 43 | PARAMETER C_MEMMAP_TIMER2_TIMELEFT = 0x81C, DT = integer, ASSIGNMENT = CONSTANT
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| 44 | PARAMETER C_MEMMAP_TIMER2_TIMELEFT_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 45 | PARAMETER C_MEMMAP_TIMER2_TIMELEFT_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 46 | PARAMETER C_MEMMAP_TIMER3_TIMELEFT = 0x820, DT = integer, ASSIGNMENT = CONSTANT
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| 47 | PARAMETER C_MEMMAP_TIMER3_TIMELEFT_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 48 | PARAMETER C_MEMMAP_TIMER3_TIMELEFT_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 49 | PARAMETER C_MEMMAP_TIMER_CONTROL_R = 0x824, DT = integer, ASSIGNMENT = CONSTANT
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| 50 | PARAMETER C_MEMMAP_TIMER_CONTROL_R_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 51 | PARAMETER C_MEMMAP_TIMER_CONTROL_R_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 52 | PARAMETER C_MEMMAP_TIMER_STATUS = 0x828, DT = integer, ASSIGNMENT = CONSTANT
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| 53 | PARAMETER C_MEMMAP_TIMER_STATUS_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 54 | PARAMETER C_MEMMAP_TIMER_STATUS_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 55 | # To Registers
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| 56 | PARAMETER C_MEMMAP_TIMER0_COUNTTO = 0x800, DT = integer, ASSIGNMENT = CONSTANT
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| 57 | PARAMETER C_MEMMAP_TIMER0_COUNTTO_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 58 | PARAMETER C_MEMMAP_TIMER0_COUNTTO_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 59 | PARAMETER C_MEMMAP_TIMER1_COUNTTO = 0x804, DT = integer, ASSIGNMENT = CONSTANT
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| 60 | PARAMETER C_MEMMAP_TIMER1_COUNTTO_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 61 | PARAMETER C_MEMMAP_TIMER1_COUNTTO_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 62 | PARAMETER C_MEMMAP_TIMER2_COUNTTO = 0x808, DT = integer, ASSIGNMENT = CONSTANT
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| 63 | PARAMETER C_MEMMAP_TIMER2_COUNTTO_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 64 | PARAMETER C_MEMMAP_TIMER2_COUNTTO_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 65 | PARAMETER C_MEMMAP_TIMER3_COUNTTO = 0x80C, DT = integer, ASSIGNMENT = CONSTANT
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| 66 | PARAMETER C_MEMMAP_TIMER3_COUNTTO_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 67 | PARAMETER C_MEMMAP_TIMER3_COUNTTO_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 68 | PARAMETER C_MEMMAP_TIMER_CONTROL_W = 0x810, DT = integer, ASSIGNMENT = CONSTANT
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| 69 | PARAMETER C_MEMMAP_TIMER_CONTROL_W_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
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| 70 | PARAMETER C_MEMMAP_TIMER_CONTROL_W_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
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| 71 | # From FIFOs
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| 72 | # To FIFOs
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| 73 | # Shared RAMs
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| 74 |
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| 75 | # Ports (Export flow)
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| 76 | PORT splb_clk = "", DIR = I, SIGIS = clk, BUS = SPLB
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| 77 | PORT idlefordifs = "", DIR = I
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| 78 | PORT plb_abus = plb_abus, DIR = I, VEC = [0:(32-1)], BUS = SPLB
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| 79 | PORT plb_pavalid = plb_pavalid, DIR = I, BUS = SPLB
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| 80 | PORT plb_rnw = plb_rnw, DIR = I, BUS = SPLB
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| 81 | PORT plb_wrdbus = plb_wrdbus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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| 82 | PORT splb_rst = splb_rst, DIR = I, SIGIS = rst, BUS = SPLB
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| 83 |
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| 84 | PORT sl_addrack = sl_addrack, DIR = O, BUS = SPLB
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| 85 | PORT sl_rdcomp = sl_rdcomp, DIR = O, BUS = SPLB
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| 86 | PORT sl_rddack = sl_rddack, DIR = O, BUS = SPLB
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| 87 | PORT sl_rddbus = sl_rddbus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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| 88 | PORT sl_wait = sl_wait, DIR = O, BUS = SPLB
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| 89 | PORT sl_wrcomp = sl_wrcomp, DIR = O, BUS = SPLB
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| 90 | PORT sl_wrdack = sl_wrdack, DIR = O, BUS = SPLB
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| 91 | PORT timer0_active = "", DIR = O
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| 92 | PORT timer1_active = "", DIR = O
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| 93 | PORT timer2_active = "", DIR = O
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| 94 | PORT timer3_active = "", DIR = O
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| 95 | PORT timerexpire = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = HIGH
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| 96 |
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| 97 |
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| 98 |
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| 99 | END
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