-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation, implementation and creation of -- -- design files limited to Xilinx devices or technologies. Use -- -- with non-Xilinx devices or technologies is expressly prohibited -- -- and immediately terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support -- -- appliances, devices, or systems. Use in such applications are -- -- expressly prohibited. -- -- -- -- (c) Copyright 1995-2007 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -- You must compile the wrapper file adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e.vhd when simulating -- the core, adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e IS port ( A: IN std_logic_VECTOR(32 downto 0); B: IN std_logic_VECTOR(32 downto 0); S: OUT std_logic_VECTOR(32 downto 0)); END adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e; ARCHITECTURE adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e_a OF adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e IS -- synthesis translate_off component wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e port ( A: IN std_logic_VECTOR(32 downto 0); B: IN std_logic_VECTOR(32 downto 0); S: OUT std_logic_VECTOR(32 downto 0)); end component; -- Configuration specification for all : wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral) generic map( c_has_bypass_with_cin => 0, c_a_type => 0, c_has_sclr => 0, c_sync_priority => 1, c_has_aset => 0, c_has_b_out => 0, c_has_s => 1, c_has_q => 0, c_bypass_enable => 0, c_b_constant => 0, c_has_ovfl => 0, c_high_bit => 32, c_latency => 0, c_sinit_val => "0", c_has_bypass => 0, c_pipe_stages => 1, c_has_sset => 0, c_has_ainit => 0, c_has_a_signed => 0, c_has_q_c_out => 0, c_b_type => 0, c_has_add => 0, c_has_sinit => 0, c_has_b_in => 0, c_has_b_signed => 0, c_bypass_low => 0, c_enable_rlocs => 1, c_b_value => "0", c_add_mode => 1, c_has_aclr => 0, c_out_width => 33, c_ainit_val => "0000", c_low_bit => 0, c_has_q_ovfl => 0, c_has_q_b_out => 0, c_has_c_out => 0, c_b_width => 33, c_a_width => 33, c_sync_enable => 0, c_has_ce => 1, c_has_c_in => 0); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e port map ( A => A, B => B, S => S); -- synthesis translate_on END adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation, implementation and creation of -- -- design files limited to Xilinx devices or technologies. Use -- -- with non-Xilinx devices or technologies is expressly prohibited -- -- and immediately terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support -- -- appliances, devices, or systems. Use in such applications are -- -- expressly prohibited. -- -- -- -- (c) Copyright 1995-2007 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -- You must compile the wrapper file binary_counter_virtex2p_7_0_b57302a6bcbb6876.vhd when simulating -- the core, binary_counter_virtex2p_7_0_b57302a6bcbb6876. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY binary_counter_virtex2p_7_0_b57302a6bcbb6876 IS port ( Q: OUT std_logic_VECTOR(31 downto 0); CLK: IN std_logic; CE: IN std_logic; SINIT: IN std_logic); END binary_counter_virtex2p_7_0_b57302a6bcbb6876; ARCHITECTURE binary_counter_virtex2p_7_0_b57302a6bcbb6876_a OF binary_counter_virtex2p_7_0_b57302a6bcbb6876 IS -- synthesis translate_off component wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876 port ( Q: OUT std_logic_VECTOR(31 downto 0); CLK: IN std_logic; CE: IN std_logic; SINIT: IN std_logic); end component; -- Configuration specification for all : wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral) generic map( c_count_mode => 0, c_load_enable => 1, c_has_aset => 0, c_load_low => 0, c_count_to => "1111111111111111", c_sync_priority => 1, c_has_iv => 0, c_restrict_count => 0, c_has_sclr => 0, c_width => 32, c_has_q_thresh1 => 0, c_enable_rlocs => 0, c_has_q_thresh0 => 0, c_thresh1_value => "1111111111111111", c_has_load => 0, c_thresh_early => 1, c_has_up => 0, c_has_thresh1 => 0, c_has_thresh0 => 0, c_ainit_val => "0000", c_has_ce => 1, c_pipe_stages => 0, c_has_aclr => 0, c_sync_enable => 0, c_has_ainit => 0, c_sinit_val => "0000", c_has_sset => 0, c_has_sinit => 1, c_count_by => "0001", c_has_l => 0, c_thresh0_value => "1111111111111111"); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876 port map ( Q => Q, CLK => CLK, CE => CE, SINIT => SINIT); -- synthesis translate_on END binary_counter_virtex2p_7_0_b57302a6bcbb6876_a; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg is constant simulating : boolean := false -- synopsys translate_off or true -- synopsys translate_on ; constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2; constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string; attribute syn_keep : boolean; function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed; function signed_to_unsigned(inp : signed) return unsigned; function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean; function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width: integer) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector; function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean; function boolean_to_signed (inp : boolean; width: integer) return signed; function boolean_to_unsigned (inp : boolean; width: integer) return unsigned; function boolean_to_vector (inp : boolean) return std_logic_vector; function std_logic_to_vector (inp : std_logic) return std_logic_vector; function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer; function std_logic_to_integer(constant inp : std_logic := '0') return integer; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector; function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector; function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean; function is_binary_string_undefined (inp : string) return boolean; function is_XorU(inp : std_logic_vector) return boolean; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector; function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector; constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean; function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string; type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg; package body conv_pkg is function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned is begin return unsigned (inp); end; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector is begin return std_logic_vector(inp); end; function std_logic_vector_to_signed(inp : std_logic_vector) return signed is begin return signed (inp); end; function signed_to_std_logic_vector(inp : signed) return std_logic_vector is begin return std_logic_vector(inp); end; function unsigned_to_signed (inp : unsigned) return signed is begin return signed(std_logic_vector(inp)); end; function signed_to_unsigned (inp : signed) return unsigned is begin return unsigned(std_logic_vector(inp)); end; function pos(inp : std_logic_vector; arith : INTEGER) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end; function max_signed(width : INTEGER) return std_logic_vector is variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin ones := (others => '1'); result(width-1) := '0'; result(width-2 downto 0) := ones; return result; end; function min_signed(width : INTEGER) return std_logic_vector is variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin zeros := (others => '0'); result(width-1) := '1'; result(width-2 downto 0) := zeros; return result; end; function and_reduce(inp: std_logic_vector) return std_logic is variable result: std_logic; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := vec(0); if width > 1 then for i in 1 to width-1 loop result := result and vec(i); end loop; end if; return result; end; function all_same(inp: std_logic_vector) return boolean is variable result: boolean; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := true; if width > 0 then for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end; function all_zeros(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean; begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end; function is_point_five(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (width > 1) then if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end; function all_ones(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean; begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end; function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable result : integer; begin result := old_width + 2; return result; end; function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable right_of_dp, left_of_dp, result : integer; begin right_of_dp := max(new_bin_pt, old_bin_pt); left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt); return result; end; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector is constant fp_width : integer := full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith; variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer := quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith; variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin result := (others => '0'); full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith); if (quantization = xlRound) then quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); elsif (quantization = xlRoundBanker) then quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); else quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); end if; if (overflow = xlSaturate) then result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); end if; return result; end; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt); constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer; begin vec := inp; for i in new_width-1 downto 0 loop j := i - right_of_dp; if ( j > old_width-1) then if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector is begin return inp(upper downto lower); end; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); end; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end; function boolean_to_signed (inp : boolean; width : integer) return signed is variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_unsigned (inp : boolean; width : integer) return unsigned is variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_vector (inp : boolean) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function std_logic_to_vector (inp : std_logic) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result(0) := inp; return result; end; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; return result; end; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if; if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1'; end if; end if; if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then one_or_zero(0) := '0'; end if; else one_or_zero(0) := '0'; end if; else if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1); else one_or_zero(0) := vec(right_of_dp); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean; begin vec := inp; overflow := true; result := (others => '0'); if (new_width >= old_width) then overflow := false; end if; if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if; if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then overflow := false; end if; end if; end if; if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if overflow then if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then vec := (others => '0'); end if; end if; if new_width <= old_width then result := vec(new_width-1 downto 0); else if new_arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; end if; end if; return result; end; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer; begin if (old_arith = xlSigned) and (new_arith = xlUnsigned) then result_arith := xlSigned; end if; result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result; end; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin return max(a_bin_pt, b_bin_pt); end; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is begin return max(a_width - a_bin_pt, b_width - b_bin_pt); end; function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; constant pad_pos : integer := new_width - orig_width - 1; begin vec := inp; pos := new_width-1; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pad_pos >= 0 then for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := vec(old_width-1); end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := '0'; end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); begin result(0) := inp; for i in new_width-1 downto 1 loop result(i) := '0'; end loop; return result; end; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; return result; end; function pad_LSB(inp : std_logic_vector; new_width, arith: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; begin vec := inp; pos := new_width-1; if (arith = xlUnsigned) then result(pos) := '0'; pos := pos - 1; else result(pos) := vec(orig_width-1); pos := pos - 1; end if; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pos >= 0 then for i in pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector is variable vec : std_logic_vector(old_width-1 downto 0); variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; function max(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; function "="(left,right: STRING) return boolean is begin if (left'length /= right'length) then return false; else test : for i in 1 to left'length loop if left(i) /= right(i) then return false; end if; end loop test; return true; end if; end; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'X' ) then result := true; end if; end loop; return result; end; function is_binary_string_undefined (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'U' ) then result := true; end if; end loop; return result; end; function is_XorU(inp : std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; result := false; for i in 0 to width-1 loop if (vec(i) = 'U') or (vec(i) = 'X') then result := true; end if; end loop; return result; end; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real is variable vec : std_logic_vector(inp'length-1 downto 0); variable result, shift_val, undefined_real : real; variable neg_num : boolean; begin vec := inp; result := 0.0; neg_num := false; if vec(inp'length-1) = '1' then neg_num := true; end if; for i in 0 to inp'length-1 loop if vec(i) = 'U' or vec(i) = 'X' then return undefined_real; end if; if arith = xlSigned then if neg_num then if vec(i) = '0' then result := result + 2.0**i; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; end loop; if arith = xlSigned then if neg_num then result := result + 1.0; result := result * (-1.0); end if; end if; shift_val := 2.0**(-1*bin_pt); result := result * shift_val; return result; end; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real is variable result : real := 0.0; begin if inp = '1' then result := 1.0; end if; if arith = xlSigned then assert false report "It doesn't make sense to convert a 1 bit number to a signed real."; end if; return result; end; -- synopsys translate_on function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); begin if (arith = xlSigned) then signed_val := to_signed(inp, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(inp, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer is constant width : integer := inp'length; variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); variable result : integer; begin if (arith = xlSigned) then signed_val := std_logic_vector_to_signed(inp); result := to_integer(signed_val); else unsigned_val := std_logic_vector_to_unsigned(inp); result := to_integer(unsigned_val); end if; return result; end; function std_logic_to_integer(constant inp : std_logic := '0') return integer is begin if inp = '1' then return 1; else return 0; end if; end; function makeZeroBinStr (width : integer) return STRING is variable result : string(1 to width+3); begin result(1) := '0'; result(2) := 'b'; for i in 3 to width+2 loop result(i) := '0'; end loop; result(width+3) := '.'; return result; end; -- synopsys translate_off function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); begin result := (others => '0'); return result; end; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector is variable real_val : real; variable int_val : integer; variable result : std_logic_vector(width-1 downto 0) := (others => '0'); variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); variable signed_val : signed(width-1 downto 0) := (others => '0'); begin real_val := inp; int_val := integer(real_val * 2.0**(bin_pt)); if (arith = xlSigned) then signed_val := to_signed(int_val, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(int_val, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; -- synopsys translate_on function valid_bin_string (inp : string) return boolean is variable vec : string(1 to inp'length); begin vec := inp; if (vec(1) = '0' and vec(2) = 'b') then return true; else return false; end if; end; function hex_string_to_std_logic_vector(inp: string; width : integer) return std_logic_vector is constant strlen : integer := inp'LENGTH; variable result : std_logic_vector(width-1 downto 0); variable bitval : std_logic_vector((strlen*4)-1 downto 0); variable posn : integer; variable ch : character; variable vec : string(1 to strlen); begin vec := inp; result := (others => '0'); posn := (strlen*4)-1; for i in 1 to strlen loop ch := vec(i); case ch is when '0' => bitval(posn downto posn-3) := "0000"; when '1' => bitval(posn downto posn-3) := "0001"; when '2' => bitval(posn downto posn-3) := "0010"; when '3' => bitval(posn downto posn-3) := "0011"; when '4' => bitval(posn downto posn-3) := "0100"; when '5' => bitval(posn downto posn-3) := "0101"; when '6' => bitval(posn downto posn-3) := "0110"; when '7' => bitval(posn downto posn-3) := "0111"; when '8' => bitval(posn downto posn-3) := "1000"; when '9' => bitval(posn downto posn-3) := "1001"; when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; when others => bitval(posn downto posn-3) := "XXXX"; -- synopsys translate_off ASSERT false REPORT "Invalid hex value" SEVERITY ERROR; -- synopsys translate_on end case; posn := posn - 4; end loop; if (width <= strlen*4) then result := bitval(width-1 downto 0); else result((strlen*4)-1 downto 0) := bitval; end if; return result; end; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector is variable pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(inp'length-1 downto 0); begin vec := inp; pos := inp'length-1; result := (others => '0'); for i in 1 to vec'length loop -- synopsys translate_off if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then assert false report "Input string is larger than output std_logic_vector. Truncating output."; return result; end if; -- synopsys translate_on if vec(i) = '0' then result(pos) := '0'; pos := pos - 1; end if; if vec(i) = '1' then result(pos) := '1'; pos := pos - 1; end if; -- synopsys translate_off if (vec(i) = 'X' or vec(i) = 'U') then result(pos) := 'U'; pos := pos - 1; end if; -- synopsys translate_on end loop; return result; end; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector is constant str_width : integer := width + 4; constant inp_len : integer := inp'length; constant num_elements : integer := (inp_len + 1)/str_width; constant reverse_index : integer := (num_elements-1) - index; variable left_pos : integer; variable right_pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(width-1 downto 0); begin vec := inp; result := (others => '0'); if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := 1; right_pos := width + 3; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := (reverse_index * str_width) + 1; right_pos := left_pos + width + 2; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; return result; end; -- synopsys translate_off function std_logic_vector_to_bin_string(inp : std_logic_vector) return string is variable vec : std_logic_vector(1 to inp'length); variable result : string(vec'range); begin vec := inp; for i in vec'range loop result(i) := to_char(vec(i)); end loop; return result; end; function std_logic_to_bin_string(inp : std_logic) return string is variable result : string(1 to 3); begin result(1) := '0'; result(2) := 'b'; result(3) := to_char(inp); return result; end; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string is variable width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable str_pos : integer; variable result : string(1 to width+3); begin vec := inp; str_pos := 1; result(str_pos) := '0'; str_pos := 2; result(str_pos) := 'b'; str_pos := 3; for i in width-1 downto 0 loop if (((width+3) - bin_pt) = str_pos) then result(str_pos) := '.'; str_pos := str_pos + 1; end if; result(str_pos) := to_char(vec(i)); str_pos := str_pos + 1; end loop; if (bin_pt = 0) then result(str_pos) := '.'; end if; return result; end; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string is variable result : string(1 to width); variable vec : std_logic_vector(width-1 downto 0); begin vec := real_to_std_logic_vector(inp, width, bin_pt, arith); result := std_logic_vector_to_bin_string(vec); return result; end; function real_to_string (inp : real) return string is variable result : string(1 to display_precision) := (others => ' '); begin result(real'image(inp)'range) := real'image(inp); return result; end; -- synopsys translate_on end conv_pkg; library IEEE; use IEEE.std_logic_1164.all; package clock_pkg is -- synopsys translate_off signal int_clk : std_logic; -- synopsys translate_on end clock_pkg; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity srl17e is generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end srl17e; architecture structural of srl17e is component SRL16E port (D : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; Q : out STD_ULOGIC); end component; attribute syn_black_box of SRL16E : component is true; attribute fpga_dont_touch of SRL16E : component is "true"; component FDE port( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC); end component; attribute syn_black_box of FDE : component is true; attribute fpga_dont_touch of FDE : component is "true"; constant a : std_logic_vector(4 downto 0) := integer_to_std_logic_vector(latency-2,5,xlSigned); signal d_delayed : std_logic_vector(width-1 downto 0); signal srl16_out : std_logic_vector(width-1 downto 0); begin d_delayed <= d after 200 ps; reg_array : for i in 0 to width-1 generate srl16_used: if latency > 1 generate u1 : srl16e port map(clk => clk, d => d_delayed(i), q => srl16_out(i), ce => ce, a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3)); end generate; srl16_not_used: if latency <= 1 generate srl16_out(i) <= d_delayed(i); end generate; fde_used: if latency /= 0 generate u2 : fde port map(c => clk, d => srl16_out(i), q => q(i), ce => ce); end generate; fde_not_used: if latency = 0 generate q(i) <= srl16_out(i); end generate; end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg; architecture structural of synth_reg is component srl17e generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end component; function calc_num_srl17es (latency : integer) return integer is variable remaining_latency : integer; variable result : integer; begin result := latency / 17; remaining_latency := latency - (result * 17); if (remaining_latency /= 0) then result := result + 1; end if; return result; end; constant complete_num_srl17es : integer := latency / 17; constant num_srl17es : integer := calc_num_srl17es(latency); constant remaining_latency : integer := latency - (complete_num_srl17es * 17); type register_array is array (num_srl17es downto 0) of std_logic_vector(width-1 downto 0); signal z : register_array; begin z(0) <= i; complete_ones : if complete_num_srl17es > 0 generate srl17e_array: for i in 0 to complete_num_srl17es-1 generate delay_comp : srl17e generic map (width => width, latency => 17) port map (clk => clk, ce => ce, d => z(i), q => z(i+1)); end generate; end generate; partial_one : if remaining_latency > 0 generate last_srl17e : srl17e generic map (width => width, latency => remaining_latency) port map (clk => clk, ce => ce, d => z(num_srl17es-1), q => z(num_srl17es)); end generate; o <= z(num_srl17es); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg_reg; architecture behav of synth_reg_reg is type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); signal reg_bank : reg_array_type := (others => (others => '0')); signal reg_bank_in : reg_array_type := (others => (others => '0')); attribute syn_allow_retiming : boolean; attribute syn_srlstyle : string; attribute syn_allow_retiming of reg_bank : signal is true; attribute syn_allow_retiming of reg_bank_in : signal is true; attribute syn_srlstyle of reg_bank : signal is "registers"; attribute syn_srlstyle of reg_bank_in : signal is "registers"; begin latency_eq_0: if latency = 0 generate o <= i; end generate latency_eq_0; latency_gt_0: if latency >= 1 generate o <= reg_bank(latency-1); reg_bank_in(0) <= i; loop_gen: for idx in latency-2 downto 0 generate reg_bank_in(idx+1) <= reg_bank(idx); end generate loop_gen; sync_loop: for sync_idx in latency-1 downto 0 generate sync_proc: process (clk) begin if clk'event and clk = '1' then if ce = '1' then reg_bank(sync_idx) <= reg_bank_in(sync_idx); end if; end if; end process sync_proc; end generate sync_loop; end generate latency_gt_0; end behav; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity single_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end single_reg_w_init; architecture structural of single_reg_w_init is function build_init_const(width: integer; init_index: integer; init_value: bit_vector) return std_logic_vector is variable result: std_logic_vector(width - 1 downto 0); begin if init_index = 0 then result := (others => '0'); elsif init_index = 1 then result := (others => '0'); result(0) := '1'; else result := to_stdlogicvector(init_value); end if; return result; end; component fdre port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; r: in std_ulogic ); end component; attribute syn_black_box of fdre: component is true; attribute fpga_dont_touch of fdre: component is "true"; component fdse port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; s: in std_ulogic ); end component; attribute syn_black_box of fdse: component is true; attribute fpga_dont_touch of fdse: component is "true"; constant init_const: std_logic_vector(width - 1 downto 0) := build_init_const(width, init_index, init_value); begin fd_prim_array: for index in 0 to width - 1 generate bit_is_0: if (init_const(index) = '0') generate fdre_comp: fdre port map ( c => clk, d => i(index), q => o(index), ce => ce, r => clr ); end generate; bit_is_1: if (init_const(index) = '1') generate fdse_comp: fdse port map ( c => clk, d => i(index), q => o(index), ce => ce, s => clr ); end generate; end generate; end architecture structural; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000"; latency: integer := 1 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end synth_reg_w_init; architecture structural of synth_reg_w_init is component single_reg_w_init generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); signal dly_clr: std_logic; begin latency_eq_0: if (latency = 0) generate o <= i; end generate; latency_gt_0: if (latency >= 1) generate dly_i((latency + 1) * width - 1 downto latency * width) <= i after 200 ps; dly_clr <= clr after 200 ps; fd_array: for index in latency downto 1 generate reg_comp: single_reg_w_init generic map ( width => width, init_index => init_index, init_value => init_value ) port map ( clk => clk, i => dly_i((index + 1) * width - 1 downto index * width), o => dly_i(index * width - 1 downto (index - 1) * width), ce => ce, clr => dly_clr ); end generate; o <= dly_i(width - 1 downto 0); end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_963ed6358a is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_963ed6358a; architecture behavior of constant_963ed6358a is begin op <= "0"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_b389f41afb is port ( plbrst : in std_logic_vector((1 - 1) downto 0); plbabus : in std_logic_vector((32 - 1) downto 0); plbpavalid : in std_logic_vector((1 - 1) downto 0); plbrnw : in std_logic_vector((1 - 1) downto 0); plbwrdbus : in std_logic_vector((32 - 1) downto 0); rddata : in std_logic_vector((32 - 1) downto 0); addrpref : in std_logic_vector((20 - 1) downto 0); wrdbusreg : out std_logic_vector((32 - 1) downto 0); addrack : out std_logic_vector((1 - 1) downto 0); rdcomp : out std_logic_vector((1 - 1) downto 0); wrdack : out std_logic_vector((1 - 1) downto 0); bankaddr : out std_logic_vector((2 - 1) downto 0); rnwreg : out std_logic_vector((1 - 1) downto 0); rddack : out std_logic_vector((1 - 1) downto 0); rddbus : out std_logic_vector((32 - 1) downto 0); linearaddr : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_b389f41afb; architecture behavior of mcode_block_b389f41afb is signal plbrst_2_20: unsigned((1 - 1) downto 0); signal plbabus_2_28: unsigned((32 - 1) downto 0); signal plbpavalid_2_37: unsigned((1 - 1) downto 0); signal plbrnw_2_49: unsigned((1 - 1) downto 0); signal plbwrdbus_2_57: unsigned((32 - 1) downto 0); signal rddata_2_68: unsigned((32 - 1) downto 0); signal addrpref_2_76: unsigned((20 - 1) downto 0); signal plbrstreg_13_24_next: boolean; signal plbrstreg_13_24: boolean := false; signal plbabusreg_14_25_next: unsigned((32 - 1) downto 0); signal plbabusreg_14_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal plbpavalidreg_15_28_next: boolean; signal plbpavalidreg_15_28: boolean := false; signal plbrnwreg_16_24_next: unsigned((1 - 1) downto 0); signal plbrnwreg_16_24: unsigned((1 - 1) downto 0) := "0"; signal plbwrdbusreg_17_27_next: unsigned((32 - 1) downto 0); signal plbwrdbusreg_17_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal avalidreg_29_23_next: boolean; signal avalidreg_29_23: boolean := false; signal ps1reg_40_20_next: boolean; signal ps1reg_40_20: boolean := false; signal psreg_48_19_next: boolean; signal psreg_48_19: boolean := false; type array_type_rdcompdelay_59_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0); signal rdcompdelay_59_25: array_type_rdcompdelay_59_25 := ( "0", "0", "0"); signal rdcompdelay_59_25_front_din: unsigned((1 - 1) downto 0); signal rdcompdelay_59_25_back: unsigned((1 - 1) downto 0); signal rdcompdelay_59_25_push_front_pop_back_en: std_logic; signal rdcompreg_63_23_next: unsigned((1 - 1) downto 0); signal rdcompreg_63_23: unsigned((1 - 1) downto 0) := "0"; signal rddackreg_67_23_next: unsigned((1 - 1) downto 0); signal rddackreg_67_23: unsigned((1 - 1) downto 0) := "0"; signal wrdackreg_71_23_next: unsigned((1 - 1) downto 0); signal wrdackreg_71_23: unsigned((1 - 1) downto 0) := "0"; signal rddbusreg_85_23_next: unsigned((32 - 1) downto 0); signal rddbusreg_85_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_21_1_slice: unsigned((2 - 1) downto 0); signal linearaddr_22_1_slice: unsigned((8 - 1) downto 0); signal addrpref_in_33_1_slice: unsigned((20 - 1) downto 0); signal rel_34_4: boolean; signal ps1_join_34_1: boolean; signal ps_43_1_bit: boolean; signal bitnot_50_49: boolean; signal bitnot_50_73: boolean; signal bit_50_49: boolean; signal addrack_50_1_convert: unsigned((1 - 1) downto 0); signal bit_56_43: unsigned((1 - 1) downto 0); signal bitnot_73_35: unsigned((1 - 1) downto 0); signal wrdackreg_73_1_bit: unsigned((1 - 1) downto 0); signal rdsel_77_1_bit: unsigned((1 - 1) downto 0); signal rel_79_4: boolean; signal rddbus1_join_79_1: unsigned((32 - 1) downto 0); signal plbwrdbusreg_98_1_slice: unsigned((32 - 1) downto 0); signal plbrstreg_13_24_next_x_000000: boolean; signal plbpavalidreg_15_28_next_x_000000: boolean; begin plbrst_2_20 <= std_logic_vector_to_unsigned(plbrst); plbabus_2_28 <= std_logic_vector_to_unsigned(plbabus); plbpavalid_2_37 <= std_logic_vector_to_unsigned(plbpavalid); plbrnw_2_49 <= std_logic_vector_to_unsigned(plbrnw); plbwrdbus_2_57 <= std_logic_vector_to_unsigned(plbwrdbus); rddata_2_68 <= std_logic_vector_to_unsigned(rddata); addrpref_2_76 <= std_logic_vector_to_unsigned(addrpref); proc_plbrstreg_13_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrstreg_13_24 <= plbrstreg_13_24_next; end if; end if; end process proc_plbrstreg_13_24; proc_plbabusreg_14_25: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbabusreg_14_25 <= plbabusreg_14_25_next; end if; end if; end process proc_plbabusreg_14_25; proc_plbpavalidreg_15_28: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbpavalidreg_15_28 <= plbpavalidreg_15_28_next; end if; end if; end process proc_plbpavalidreg_15_28; proc_plbrnwreg_16_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrnwreg_16_24 <= plbrnwreg_16_24_next; end if; end if; end process proc_plbrnwreg_16_24; proc_plbwrdbusreg_17_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbwrdbusreg_17_27 <= plbwrdbusreg_17_27_next; end if; end if; end process proc_plbwrdbusreg_17_27; proc_avalidreg_29_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then avalidreg_29_23 <= avalidreg_29_23_next; end if; end if; end process proc_avalidreg_29_23; proc_ps1reg_40_20: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ps1reg_40_20 <= ps1reg_40_20_next; end if; end if; end process proc_ps1reg_40_20; proc_psreg_48_19: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then psreg_48_19 <= psreg_48_19_next; end if; end if; end process proc_psreg_48_19; rdcompdelay_59_25_back <= rdcompdelay_59_25(2); proc_rdcompdelay_59_25: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (rdcompdelay_59_25_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop rdcompdelay_59_25(i) <= rdcompdelay_59_25(i-1); end loop; rdcompdelay_59_25(0) <= rdcompdelay_59_25_front_din; end if; end if; end process proc_rdcompdelay_59_25; proc_rdcompreg_63_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rdcompreg_63_23 <= rdcompreg_63_23_next; end if; end if; end process proc_rdcompreg_63_23; proc_rddackreg_67_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddackreg_67_23 <= rddackreg_67_23_next; end if; end if; end process proc_rddackreg_67_23; proc_wrdackreg_71_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then wrdackreg_71_23 <= wrdackreg_71_23_next; end if; end if; end process proc_wrdackreg_71_23; proc_rddbusreg_85_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddbusreg_85_23 <= rddbusreg_85_23_next; end if; end if; end process proc_rddbusreg_85_23; bankaddr_21_1_slice <= u2u_slice(plbabusreg_14_25, 11, 10); linearaddr_22_1_slice <= u2u_slice(plbabusreg_14_25, 9, 2); addrpref_in_33_1_slice <= u2u_slice(plbabusreg_14_25, 31, 12); rel_34_4 <= addrpref_in_33_1_slice = addrpref_2_76; proc_if_34_1: process (rel_34_4) is begin if rel_34_4 then ps1_join_34_1 <= true; else ps1_join_34_1 <= false; end if; end process proc_if_34_1; ps_43_1_bit <= ((boolean_to_vector(ps1_join_34_1) and boolean_to_vector(plbpavalidreg_15_28)) = "1"); bitnot_50_49 <= ((not boolean_to_vector(plbrstreg_13_24)) = "1"); bitnot_50_73 <= ((not boolean_to_vector(psreg_48_19)) = "1"); bit_50_49 <= ((boolean_to_vector(bitnot_50_49) and boolean_to_vector(ps_43_1_bit) and boolean_to_vector(bitnot_50_73)) = "1"); addrack_50_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_50_49)), 0, 1, 0); bit_56_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_16_24)); bitnot_73_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_16_24)); wrdackreg_73_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(bitnot_73_35)); rdsel_77_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_59_25_back) or unsigned_to_std_logic_vector(rdcompreg_63_23)); rel_79_4 <= rdsel_77_1_bit = std_logic_vector_to_unsigned("1"); proc_if_79_1: process (rddata_2_68, rel_79_4) is begin if rel_79_4 then rddbus1_join_79_1 <= rddata_2_68; else rddbus1_join_79_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); end if; end process proc_if_79_1; plbwrdbusreg_98_1_slice <= u2u_slice(plbwrdbus_2_57, 31, 0); plbrstreg_13_24_next_x_000000 <= (plbrst_2_20 /= "0"); plbrstreg_13_24_next <= plbrstreg_13_24_next_x_000000; plbabusreg_14_25_next <= plbabus_2_28; plbpavalidreg_15_28_next_x_000000 <= (plbpavalid_2_37 /= "0"); plbpavalidreg_15_28_next <= plbpavalidreg_15_28_next_x_000000; plbrnwreg_16_24_next <= plbrnw_2_49; plbwrdbusreg_17_27_next <= plbwrdbusreg_98_1_slice; avalidreg_29_23_next <= plbpavalidreg_15_28; ps1reg_40_20_next <= ps1_join_34_1; psreg_48_19_next <= ps_43_1_bit; rdcompdelay_59_25_front_din <= bit_56_43; rdcompdelay_59_25_push_front_pop_back_en <= '1'; rdcompreg_63_23_next <= rdcompdelay_59_25_back; rddackreg_67_23_next <= rdcompreg_63_23; wrdackreg_71_23_next <= wrdackreg_73_1_bit; rddbusreg_85_23_next <= rddbus1_join_79_1; wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_17_27); addrack <= unsigned_to_std_logic_vector(addrack_50_1_convert); rdcomp <= unsigned_to_std_logic_vector(rdcompreg_63_23); wrdack <= unsigned_to_std_logic_vector(wrdackreg_71_23); bankaddr <= unsigned_to_std_logic_vector(bankaddr_21_1_slice); rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_16_24); rddack <= unsigned_to_std_logic_vector(rddackreg_67_23); rddbus <= unsigned_to_std_logic_vector(rddbusreg_85_23); linearaddr <= unsigned_to_std_logic_vector(linearaddr_22_1_slice); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_b59e0d51fc is port ( wrdbus : in std_logic_vector((32 - 1) downto 0); bankaddr : in std_logic_vector((2 - 1) downto 0); linearaddr : in std_logic_vector((8 - 1) downto 0); rnwreg : in std_logic_vector((1 - 1) downto 0); addrack : in std_logic_vector((1 - 1) downto 0); sm_timer0_timeleft : in std_logic_vector((32 - 1) downto 0); sm_timer1_timeleft : in std_logic_vector((32 - 1) downto 0); sm_timer2_timeleft : in std_logic_vector((32 - 1) downto 0); sm_timer3_timeleft : in std_logic_vector((32 - 1) downto 0); sm_timer_control_r : in std_logic_vector((32 - 1) downto 0); sm_timer_status : in std_logic_vector((32 - 1) downto 0); sm_timer0_countto : in std_logic_vector((32 - 1) downto 0); sm_timer1_countto : in std_logic_vector((32 - 1) downto 0); sm_timer2_countto : in std_logic_vector((32 - 1) downto 0); sm_timer3_countto : in std_logic_vector((32 - 1) downto 0); sm_timer_control_w : in std_logic_vector((32 - 1) downto 0); read_bank_out : out std_logic_vector((32 - 1) downto 0); sm_timer0_countto_din : out std_logic_vector((32 - 1) downto 0); sm_timer0_countto_en : out std_logic_vector((1 - 1) downto 0); sm_timer1_countto_din : out std_logic_vector((32 - 1) downto 0); sm_timer1_countto_en : out std_logic_vector((1 - 1) downto 0); sm_timer2_countto_din : out std_logic_vector((32 - 1) downto 0); sm_timer2_countto_en : out std_logic_vector((1 - 1) downto 0); sm_timer3_countto_din : out std_logic_vector((32 - 1) downto 0); sm_timer3_countto_en : out std_logic_vector((1 - 1) downto 0); sm_timer_control_w_din : out std_logic_vector((32 - 1) downto 0); sm_timer_control_w_en : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_b59e0d51fc; architecture behavior of mcode_block_b59e0d51fc is signal wrdbus_1_273: unsigned((32 - 1) downto 0); signal bankaddr_1_281: unsigned((2 - 1) downto 0); signal linearaddr_1_291: unsigned((8 - 1) downto 0); signal rnwreg_1_303: unsigned((1 - 1) downto 0); signal addrack_1_311: unsigned((1 - 1) downto 0); signal sm_timer0_timeleft_1_320: unsigned((32 - 1) downto 0); signal sm_timer1_timeleft_1_340: unsigned((32 - 1) downto 0); signal sm_timer2_timeleft_1_360: unsigned((32 - 1) downto 0); signal sm_timer3_timeleft_1_380: unsigned((32 - 1) downto 0); signal sm_timer_control_r_1_400: unsigned((32 - 1) downto 0); signal sm_timer_status_1_420: unsigned((32 - 1) downto 0); signal sm_timer0_countto_1_437: unsigned((32 - 1) downto 0); signal sm_timer1_countto_1_456: unsigned((32 - 1) downto 0); signal sm_timer2_countto_1_475: unsigned((32 - 1) downto 0); signal sm_timer3_countto_1_494: unsigned((32 - 1) downto 0); signal sm_timer_control_w_1_513: unsigned((32 - 1) downto 0); signal reg_bank_out_reg_47_30_next: unsigned((32 - 1) downto 0); signal reg_bank_out_reg_47_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal read_bank_out_reg_158_31_next: unsigned((32 - 1) downto 0); signal read_bank_out_reg_158_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_reg_161_26_next: unsigned((2 - 1) downto 0); signal bankaddr_reg_161_26: unsigned((2 - 1) downto 0) := "00"; signal rel_50_4: boolean; signal rel_52_8: boolean; signal rel_54_8: boolean; signal rel_56_8: boolean; signal rel_58_8: boolean; signal rel_60_8: boolean; signal rel_62_8: boolean; signal rel_64_8: boolean; signal rel_66_8: boolean; signal rel_68_8: boolean; signal rel_70_8: boolean; signal reg_bank_out_reg_join_50_1: unsigned((32 - 1) downto 0); signal opcode_81_1_concat: unsigned((12 - 1) downto 0); signal rel_102_4: boolean; signal sm_timer0_countto_en_join_102_1: boolean; signal rel_108_4: boolean; signal sm_timer1_countto_en_join_108_1: boolean; signal rel_114_4: boolean; signal sm_timer2_countto_en_join_114_1: boolean; signal rel_120_4: boolean; signal sm_timer3_countto_en_join_120_1: boolean; signal rel_126_4: boolean; signal sm_timer_control_w_en_join_126_1: boolean; signal slice_141_42: unsigned((32 - 1) downto 0); signal slice_144_42: unsigned((32 - 1) downto 0); signal slice_147_42: unsigned((32 - 1) downto 0); signal slice_150_42: unsigned((32 - 1) downto 0); signal slice_153_43: unsigned((32 - 1) downto 0); signal rel_163_4: boolean; signal rel_166_8: boolean; signal rel_169_8: boolean; signal rel_172_8: boolean; signal read_bank_out_reg_join_163_1: unsigned((32 - 1) downto 0); begin wrdbus_1_273 <= std_logic_vector_to_unsigned(wrdbus); bankaddr_1_281 <= std_logic_vector_to_unsigned(bankaddr); linearaddr_1_291 <= std_logic_vector_to_unsigned(linearaddr); rnwreg_1_303 <= std_logic_vector_to_unsigned(rnwreg); addrack_1_311 <= std_logic_vector_to_unsigned(addrack); sm_timer0_timeleft_1_320 <= std_logic_vector_to_unsigned(sm_timer0_timeleft); sm_timer1_timeleft_1_340 <= std_logic_vector_to_unsigned(sm_timer1_timeleft); sm_timer2_timeleft_1_360 <= std_logic_vector_to_unsigned(sm_timer2_timeleft); sm_timer3_timeleft_1_380 <= std_logic_vector_to_unsigned(sm_timer3_timeleft); sm_timer_control_r_1_400 <= std_logic_vector_to_unsigned(sm_timer_control_r); sm_timer_status_1_420 <= std_logic_vector_to_unsigned(sm_timer_status); sm_timer0_countto_1_437 <= std_logic_vector_to_unsigned(sm_timer0_countto); sm_timer1_countto_1_456 <= std_logic_vector_to_unsigned(sm_timer1_countto); sm_timer2_countto_1_475 <= std_logic_vector_to_unsigned(sm_timer2_countto); sm_timer3_countto_1_494 <= std_logic_vector_to_unsigned(sm_timer3_countto); sm_timer_control_w_1_513 <= std_logic_vector_to_unsigned(sm_timer_control_w); proc_reg_bank_out_reg_47_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then reg_bank_out_reg_47_30 <= reg_bank_out_reg_47_30_next; end if; end if; end process proc_reg_bank_out_reg_47_30; proc_read_bank_out_reg_158_31: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then read_bank_out_reg_158_31 <= read_bank_out_reg_158_31_next; end if; end if; end process proc_read_bank_out_reg_158_31; proc_bankaddr_reg_161_26: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then bankaddr_reg_161_26 <= bankaddr_reg_161_26_next; end if; end if; end process proc_bankaddr_reg_161_26; rel_50_4 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000101"); rel_52_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000110"); rel_54_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000111"); rel_56_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001000"); rel_58_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001001"); rel_60_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001010"); rel_62_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000000"); rel_64_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000001"); rel_66_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000010"); rel_68_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000011"); rel_70_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000100"); proc_if_50_1: process (reg_bank_out_reg_47_30, rel_50_4, rel_52_8, rel_54_8, rel_56_8, rel_58_8, rel_60_8, rel_62_8, rel_64_8, rel_66_8, rel_68_8, rel_70_8, sm_timer0_countto_1_437, sm_timer0_timeleft_1_320, sm_timer1_countto_1_456, sm_timer1_timeleft_1_340, sm_timer2_countto_1_475, sm_timer2_timeleft_1_360, sm_timer3_countto_1_494, sm_timer3_timeleft_1_380, sm_timer_control_r_1_400, sm_timer_control_w_1_513, sm_timer_status_1_420) is begin if rel_50_4 then reg_bank_out_reg_join_50_1 <= sm_timer0_timeleft_1_320; elsif rel_52_8 then reg_bank_out_reg_join_50_1 <= sm_timer1_timeleft_1_340; elsif rel_54_8 then reg_bank_out_reg_join_50_1 <= sm_timer2_timeleft_1_360; elsif rel_56_8 then reg_bank_out_reg_join_50_1 <= sm_timer3_timeleft_1_380; elsif rel_58_8 then reg_bank_out_reg_join_50_1 <= sm_timer_control_r_1_400; elsif rel_60_8 then reg_bank_out_reg_join_50_1 <= sm_timer_status_1_420; elsif rel_62_8 then reg_bank_out_reg_join_50_1 <= sm_timer0_countto_1_437; elsif rel_64_8 then reg_bank_out_reg_join_50_1 <= sm_timer1_countto_1_456; elsif rel_66_8 then reg_bank_out_reg_join_50_1 <= sm_timer2_countto_1_475; elsif rel_68_8 then reg_bank_out_reg_join_50_1 <= sm_timer3_countto_1_494; elsif rel_70_8 then reg_bank_out_reg_join_50_1 <= sm_timer_control_w_1_513; else reg_bank_out_reg_join_50_1 <= reg_bank_out_reg_47_30; end if; end process proc_if_50_1; opcode_81_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_311) & unsigned_to_std_logic_vector(rnwreg_1_303) & unsigned_to_std_logic_vector(bankaddr_1_281) & unsigned_to_std_logic_vector(linearaddr_1_291)); rel_102_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000000"); proc_if_102_1: process (rel_102_4) is begin if rel_102_4 then sm_timer0_countto_en_join_102_1 <= true; else sm_timer0_countto_en_join_102_1 <= false; end if; end process proc_if_102_1; rel_108_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000001"); proc_if_108_1: process (rel_108_4) is begin if rel_108_4 then sm_timer1_countto_en_join_108_1 <= true; else sm_timer1_countto_en_join_108_1 <= false; end if; end process proc_if_108_1; rel_114_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000010"); proc_if_114_1: process (rel_114_4) is begin if rel_114_4 then sm_timer2_countto_en_join_114_1 <= true; else sm_timer2_countto_en_join_114_1 <= false; end if; end process proc_if_114_1; rel_120_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000011"); proc_if_120_1: process (rel_120_4) is begin if rel_120_4 then sm_timer3_countto_en_join_120_1 <= true; else sm_timer3_countto_en_join_120_1 <= false; end if; end process proc_if_120_1; rel_126_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000100"); proc_if_126_1: process (rel_126_4) is begin if rel_126_4 then sm_timer_control_w_en_join_126_1 <= true; else sm_timer_control_w_en_join_126_1 <= false; end if; end process proc_if_126_1; slice_141_42 <= u2u_slice(wrdbus_1_273, 31, 0); slice_144_42 <= u2u_slice(wrdbus_1_273, 31, 0); slice_147_42 <= u2u_slice(wrdbus_1_273, 31, 0); slice_150_42 <= u2u_slice(wrdbus_1_273, 31, 0); slice_153_43 <= u2u_slice(wrdbus_1_273, 31, 0); rel_163_4 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("00"); rel_166_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("01"); rel_169_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("10"); rel_172_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("11"); proc_if_163_1: process (read_bank_out_reg_158_31, reg_bank_out_reg_47_30, rel_163_4, rel_166_8, rel_169_8, rel_172_8) is begin if rel_163_4 then read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_166_8 then read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_169_8 then read_bank_out_reg_join_163_1 <= reg_bank_out_reg_47_30; elsif rel_172_8 then read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); else read_bank_out_reg_join_163_1 <= read_bank_out_reg_158_31; end if; end process proc_if_163_1; reg_bank_out_reg_47_30_next <= reg_bank_out_reg_join_50_1; read_bank_out_reg_158_31_next <= read_bank_out_reg_join_163_1; bankaddr_reg_161_26_next <= bankaddr_1_281; read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_158_31); sm_timer0_countto_din <= unsigned_to_std_logic_vector(slice_141_42); sm_timer0_countto_en <= boolean_to_vector(sm_timer0_countto_en_join_102_1); sm_timer1_countto_din <= unsigned_to_std_logic_vector(slice_144_42); sm_timer1_countto_en <= boolean_to_vector(sm_timer1_countto_en_join_108_1); sm_timer2_countto_din <= unsigned_to_std_logic_vector(slice_147_42); sm_timer2_countto_en <= boolean_to_vector(sm_timer2_countto_en_join_114_1); sm_timer3_countto_din <= unsigned_to_std_logic_vector(slice_150_42); sm_timer3_countto_en <= boolean_to_vector(sm_timer3_countto_en_join_120_1); sm_timer_control_w_din <= unsigned_to_std_logic_vector(slice_153_43); sm_timer_control_w_en <= boolean_to_vector(sm_timer_control_w_en_join_126_1); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e5b38cca3b is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e5b38cca3b; architecture behavior of inverter_e5b38cca3b is signal ip_1_26: boolean; type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean; signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => false); signal op_mem_22_20_front_din: boolean; signal op_mem_22_20_back: boolean; signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: boolean; begin ip_1_26 <= ((ip) = "1"); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1"); op_mem_22_20_push_front_pop_back_en <= '0'; op <= boolean_to_vector(internal_ip_12_1_bitnot); end behavior; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlregister is generic (d_width : integer := 5; init_value : bit_vector := b"00"); port (d : in std_logic_vector (d_width-1 downto 0); rst : in std_logic_vector(0 downto 0) := "0"; en : in std_logic_vector(0 downto 0) := "1"; ce : in std_logic; clk : in std_logic; q : out std_logic_vector (d_width-1 downto 0)); end xlregister; architecture behavior of xlregister is component synth_reg_w_init generic (width : integer; init_index : integer; init_value : bit_vector; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; -- synopsys translate_off signal real_d, real_q : real; -- synopsys translate_on signal internal_clr : std_logic; signal internal_ce : std_logic; begin internal_clr <= rst(0) and ce; internal_ce <= en(0) and ce; synth_reg_inst : synth_reg_w_init generic map (width => d_width, init_index => 2, init_value => init_value, latency => 1) port map (i => d, ce => internal_ce, clr => internal_clr, clk => clk, o => q); end architecture behavior; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xldelay is generic(width : integer := -1; latency : integer := -1; reg_retiming : integer := 0); port(d : in std_logic_vector (width-1 downto 0); ce : in std_logic; clk : in std_logic; en : in std_logic; q : out std_logic_vector (width-1 downto 0)); end xldelay; architecture behavior of xldelay is component synth_reg generic (width : integer; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; component synth_reg_reg generic (width : integer; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; signal internal_ce : std_logic; begin internal_ce <= ce and en; srl_delay: if (reg_retiming = 0) or (latency < 1) generate synth_reg_srl_inst : synth_reg generic map ( width => width, latency => latency) port map ( i => d, ce => internal_ce, clr => '0', clk => clk, o => q); end generate srl_delay; reg_delay: if (reg_retiming = 1) and (latency >= 1) generate synth_reg_reg_inst : synth_reg_reg generic map ( width => width, latency => latency) port map ( i => d, ce => internal_ce, clr => '0', clk => clk, o => q); end generate reg_delay; end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity logical_80f90b97d0 is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end logical_80f90b97d0; architecture behavior of logical_80f90b97d0 is signal d0_1_24: std_logic; signal d1_1_27: std_logic; signal fully_2_1_bit: std_logic; begin d0_1_24 <= d0(0); d1_1_27 <= d1(0); fully_2_1_bit <= d0_1_24 and d1_1_27; y <= std_logic_to_vector(fully_2_1_bit); end behavior; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xladdsub is generic ( core_name0: string := ""; a_width: integer := 16; a_bin_pt: integer := 4; a_arith: integer := xlUnsigned; c_in_width: integer := 16; c_in_bin_pt: integer := 4; c_in_arith: integer := xlUnsigned; c_out_width: integer := 16; c_out_bin_pt: integer := 4; c_out_arith: integer := xlUnsigned; b_width: integer := 8; b_bin_pt: integer := 2; b_arith: integer := xlUnsigned; s_width: integer := 17; s_bin_pt: integer := 4; s_arith: integer := xlUnsigned; rst_width: integer := 1; rst_bin_pt: integer := 0; rst_arith: integer := xlUnsigned; en_width: integer := 1; en_bin_pt: integer := 0; en_arith: integer := xlUnsigned; full_s_width: integer := 17; full_s_arith: integer := xlUnsigned; mode: integer := xlAddMode; extra_registers: integer := 0; latency: integer := 0; quantization: integer := xlTruncate; overflow: integer := xlWrap; c_latency: integer := 0; c_output_width: integer := 17; c_has_q : integer := 1; c_has_s : integer := 0; c_has_c_out : integer := 0; c_has_q_c_out : integer := 0; c_has_b_out : integer := 0; c_has_q_b_out : integer := 0; c_has_q_ovfl : integer := 0; c_has_ovfl : integer := 0 ); port ( a: in std_logic_vector(a_width - 1 downto 0); b: in std_logic_vector(b_width - 1 downto 0); c_in : in std_logic_vector (0 downto 0) := "0"; ce: in std_logic; clr: in std_logic := '0'; clk: in std_logic; rst: in std_logic_vector(rst_width - 1 downto 0) := "0"; en: in std_logic_vector(en_width - 1 downto 0) := "1"; c_out : out std_logic_vector (0 downto 0); s: out std_logic_vector(s_width - 1 downto 0) ); end xladdsub ; architecture behavior of xladdsub is component synth_reg generic ( width: integer := 16; latency: integer := 5 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function format_input(inp: std_logic_vector; old_width, delta, new_arith, new_width: integer) return std_logic_vector is variable vec: std_logic_vector(old_width-1 downto 0); variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0); variable result: std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt); constant full_a_width: integer := full_s_width; constant full_b_width: integer := full_s_width; signal full_a: std_logic_vector(full_a_width - 1 downto 0); signal full_b: std_logic_vector(full_b_width - 1 downto 0); signal core_s: std_logic_vector(full_s_width - 1 downto 0); signal conv_s: std_logic_vector(s_width - 1 downto 0); signal temp_cout : std_logic; signal internal_clr: std_logic; signal internal_ce: std_logic; signal extra_reg_ce: std_logic; signal override: std_logic; signal logic1: std_logic_vector(0 downto 0); component adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e port ( a: in std_logic_vector( 33 - 1 downto 0); s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(33 - 1 downto 0) ); end component; attribute syn_black_box of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e: component is true; attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e: component is "true"; attribute box_type of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e: component is "black_box"; begin internal_clr <= (clr or (rst(0))) and ce; internal_ce <= ce and en(0); logic1(0) <= '1'; addsub_process: process(a, b, core_s) begin full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width); full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width); conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith, s_width, s_bin_pt, s_arith, quantization, overflow); end process addsub_process; comp0: if ((core_name0 = "adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e")) generate core_instance0: adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e port map ( a => full_a, s => core_s, b => full_b ); end generate; latency_test: if (extra_registers > 0) generate override_test: if (c_latency > 1) generate override_pipe: synth_reg generic map ( width => 1, latency => c_latency) port map ( i => logic1, ce => internal_ce, clr => internal_clr, clk => clk, o(0) => override); extra_reg_ce <= ce and en(0) and override; end generate override_test; no_override: if (c_latency = 0) or (c_latency = 1) generate extra_reg_ce <= ce and en(0); end generate no_override; extra_reg: synth_reg generic map ( width => s_width, latency => extra_registers ) port map ( i => conv_s, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => s ); cout_test : if((c_has_c_out = 1) or (c_has_b_out = 1) or (c_has_q_c_out = 1) or (c_has_q_b_out = 1)) generate c_out_extra_reg: synth_reg generic map ( width => 1, latency => extra_registers ) port map ( i(0) => temp_cout, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => c_out ); end generate cout_test; end generate; latency_s: if ((latency = 0) or (extra_registers = 0)) generate s <= conv_s; end generate latency_s; latency0: if ( ((latency = 0) or (extra_registers = 0)) and ((c_has_b_out = 1) or (c_has_q_c_out = 1) or (c_has_c_out = 1) or (c_has_q_b_out = 1))) generate c_out(0) <= temp_cout; end generate latency0; tie_dangling_cout: if ((c_has_c_out = 0) and (c_has_b_out = 0) and (c_has_q_c_out = 0) and (c_has_q_b_out = 0)) generate c_out <= "0"; end generate tie_dangling_cout; end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_6293007044 is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_6293007044; architecture behavior of constant_6293007044 is begin op <= "1"; end behavior; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity convert_func_call is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end convert_func_call; architecture behavior of convert_func_call is begin result <= convert_type(din, din_width, din_bin_pt, din_arith, dout_width, dout_bin_pt, dout_arith, quantization, overflow); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlconvert is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; bool_conversion : integer :=0; latency : integer := 0; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; dout : out std_logic_vector (dout_width-1 downto 0)); end xlconvert; architecture behavior of xlconvert is component synth_reg generic (width : integer; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; component convert_func_call generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end component; -- synopsys translate_off signal real_din, real_dout : real; -- synopsys translate_on signal result : std_logic_vector(dout_width-1 downto 0); begin -- synopsys translate_off -- synopsys translate_on bool_conversion_generate : if (bool_conversion = 1) generate result <= din; end generate; std_conversion_generate : if (bool_conversion = 0) generate convert : convert_func_call generic map ( din_width => din_width, din_bin_pt => din_bin_pt, din_arith => din_arith, dout_width => dout_width, dout_bin_pt => dout_bin_pt, dout_arith => dout_arith, quantization => quantization, overflow => overflow) port map ( din => din, result => result); end generate; latency_test : if (latency > 0) generate reg : synth_reg generic map ( width => dout_width, latency => latency) port map (i => result, ce => ce, clr => clr, clk => clk, o => dout); end generate; latency0 : if (latency = 0) generate dout <= result; end generate latency0; end behavior; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlcounter_free is generic ( core_name0: string := ""; op_width: integer := 5; op_arith: integer := xlSigned ); port ( ce: in std_logic; clr: in std_logic; clk: in std_logic; op: out std_logic_vector(op_width - 1 downto 0); up: in std_logic_vector(0 downto 0) := (others => '0'); load: in std_logic_vector(0 downto 0) := (others => '0'); din: in std_logic_vector(op_width - 1 downto 0) := (others => '0'); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0) ); end xlcounter_free ; architecture behavior of xlcounter_free is component binary_counter_virtex2p_7_0_b57302a6bcbb6876 port ( clk: in std_logic; ce: in std_logic; sinit: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of binary_counter_virtex2p_7_0_b57302a6bcbb6876: component is true; attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b57302a6bcbb6876: component is "true"; attribute box_type of binary_counter_virtex2p_7_0_b57302a6bcbb6876: component is "black_box"; -- synopsys translate_off constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0'); constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1'); constant zeroStr: string(1 to op_width) := std_logic_vector_to_bin_string(zeroVec); constant oneStr: string(1 to op_width) := std_logic_vector_to_bin_string(oneVec); -- synopsys translate_on signal core_sinit: std_logic; signal core_ce: std_logic; signal op_net: std_logic_vector(op_width - 1 downto 0); begin core_ce <= ce and en(0); core_sinit <= (clr or rst(0)) and ce; op <= op_net; comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_b57302a6bcbb6876")) generate core_instance0: binary_counter_virtex2p_7_0_b57302a6bcbb6876 port map ( clk => clk, ce => core_ce, sinit => core_sinit, q => op_net ); end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity logical_6cb8f0ce02 is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); d2 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end logical_6cb8f0ce02; architecture behavior of logical_6cb8f0ce02 is signal d0_1_24: std_logic; signal d1_1_27: std_logic; signal d2_1_30: std_logic; signal fully_2_1_bit: std_logic; begin d0_1_24 <= d0(0); d1_1_27 <= d1(0); d2_1_30 <= d2(0); fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30; y <= std_logic_to_vector(fully_2_1_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity logical_aacf6e1b0e is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end logical_aacf6e1b0e; architecture behavior of logical_aacf6e1b0e is signal d0_1_24: std_logic; signal d1_1_27: std_logic; signal fully_2_1_bit: std_logic; begin d0_1_24 <= d0(0); d1_1_27 <= d1(0); fully_2_1_bit <= d0_1_24 or d1_1_27; y <= std_logic_to_vector(fully_2_1_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_112ed141f4 is port ( sel : in std_logic_vector((1 - 1) downto 0); d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_112ed141f4; architecture behavior of mux_112ed141f4 is signal sel_1_20: std_logic; signal d0_1_24: std_logic_vector((1 - 1) downto 0); signal d1_1_27: std_logic_vector((1 - 1) downto 0); signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0); signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0); begin sel_1_20 <= sel(0); d0_1_24 <= d0; d1_1_27 <= d1; sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned); proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert) is begin case sel_internal_2_1_convert is when "0" => unregy_join_6_1 <= d0_1_24; when others => unregy_join_6_1 <= d1_1_27; end case; end process proc_switch_6_1; y <= unregy_join_6_1; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_3ffd1d0a40 is port ( a : in std_logic_vector((32 - 1) downto 0); b : in std_logic_vector((32 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_3ffd1d0a40; architecture behavior of relational_3ffd1d0a40 is signal a_1_31: unsigned((32 - 1) downto 0); signal b_1_34: unsigned((32 - 1) downto 0); signal result_12_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_12_3_rel <= a_1_31 = b_1_34; op <= boolean_to_vector(result_12_3_rel); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_34fc311f5b is port ( a : in std_logic_vector((32 - 1) downto 0); b : in std_logic_vector((32 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_34fc311f5b; architecture behavior of relational_34fc311f5b is signal a_1_31: unsigned((32 - 1) downto 0); signal b_1_34: unsigned((32 - 1) downto 0); type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean; signal op_mem_32_22: array_type_op_mem_32_22 := ( 0 => false); signal op_mem_32_22_front_din: boolean; signal op_mem_32_22_back: boolean; signal op_mem_32_22_push_front_pop_back_en: std_logic; signal result_18_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); op_mem_32_22_back <= op_mem_32_22(0); proc_op_mem_32_22: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then op_mem_32_22(0) <= op_mem_32_22_front_din; end if; end if; end process proc_op_mem_32_22; result_18_3_rel <= a_1_31 > b_1_34; op_mem_32_22_front_din <= result_18_3_rel; op_mem_32_22_push_front_pop_back_en <= '1'; op <= boolean_to_vector(op_mem_32_22_back); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_37567836aa is port ( op : out std_logic_vector((32 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_37567836aa; architecture behavior of constant_37567836aa is begin op <= "00000000000000000000000000000000"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_a1e126f11c is port ( in0 : in std_logic_vector((8 - 1) downto 0); in1 : in std_logic_vector((8 - 1) downto 0); in2 : in std_logic_vector((8 - 1) downto 0); in3 : in std_logic_vector((8 - 1) downto 0); y : out std_logic_vector((32 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_a1e126f11c; architecture behavior of concat_a1e126f11c is signal in0_1_23: unsigned((8 - 1) downto 0); signal in1_1_27: unsigned((8 - 1) downto 0); signal in2_1_31: unsigned((8 - 1) downto 0); signal in3_1_35: unsigned((8 - 1) downto 0); signal y_2_1_concat: unsigned((32 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); in3_1_35 <= std_logic_vector_to_unsigned(in3); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_09e13b86e0 is port ( in0 : in std_logic_vector((1 - 1) downto 0); in1 : in std_logic_vector((1 - 1) downto 0); in2 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_09e13b86e0; architecture behavior of concat_09e13b86e0 is signal in0_1_23: boolean; signal in1_1_27: boolean; signal in2_1_31: boolean; signal y_2_1_concat: unsigned((3 - 1) downto 0); begin in0_1_23 <= ((in0) = "1"); in1_1_27 <= ((in1) = "1"); in2_1_31 <= ((in2) = "1"); y_2_1_concat <= std_logic_vector_to_unsigned(boolean_to_vector(in0_1_23) & boolean_to_vector(in1_1_27) & boolean_to_vector(in2_1_31)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity logical_a6d07705dd is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); d2 : in std_logic_vector((1 - 1) downto 0); d3 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end logical_a6d07705dd; architecture behavior of logical_a6d07705dd is signal d0_1_24: std_logic; signal d1_1_27: std_logic; signal d2_1_30: std_logic; signal d3_1_33: std_logic; signal fully_2_1_bit: std_logic; begin d0_1_24 <= d0(0); d1_1_27 <= d1(0); d2_1_30 <= d2(0); d3_1_33 <= d3(0); fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30 or d3_1_33; y <= std_logic_to_vector(fully_2_1_bit); end behavior; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlslice is generic ( new_msb : integer := 9; new_lsb : integer := 1; x_width : integer := 16; y_width : integer := 8); port ( x : in std_logic_vector (x_width-1 downto 0); y : out std_logic_vector (y_width-1 downto 0)); end xlslice; architecture behavior of xlslice is begin y <= x(new_msb downto new_lsb); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "warp_timer/EDK Processor" entity edk_processor_entity_cddda35d8e is port ( ce_1: in std_logic; clk_1: in std_logic; from_register: in std_logic_vector(31 downto 0); from_register1: in std_logic_vector(31 downto 0); from_register2: in std_logic_vector(31 downto 0); from_register3: in std_logic_vector(31 downto 0); from_register4: in std_logic_vector(31 downto 0); from_register5: in std_logic_vector(31 downto 0); plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; to_register: in std_logic_vector(31 downto 0); to_register1: in std_logic_vector(31 downto 0); to_register2: in std_logic_vector(31 downto 0); to_register3: in std_logic_vector(31 downto 0); to_register4: in std_logic_vector(31 downto 0); constant5_x0: out std_logic; plb_decode_x0: out std_logic; plb_decode_x1: out std_logic; plb_decode_x2: out std_logic; plb_decode_x3: out std_logic; plb_decode_x4: out std_logic_vector(31 downto 0); plb_memmap_x0: out std_logic_vector(31 downto 0); plb_memmap_x1: out std_logic; plb_memmap_x2: out std_logic_vector(31 downto 0); plb_memmap_x3: out std_logic; plb_memmap_x4: out std_logic_vector(31 downto 0); plb_memmap_x5: out std_logic; plb_memmap_x6: out std_logic_vector(31 downto 0); plb_memmap_x7: out std_logic; plb_memmap_x8: out std_logic_vector(31 downto 0); plb_memmap_x9: out std_logic ); end edk_processor_entity_cddda35d8e; architecture structural of edk_processor_entity_cddda35d8e is signal bankaddr: std_logic_vector(1 downto 0); signal ce_1_sg_x0: std_logic; signal clk_1_sg_x0: std_logic; signal linearaddr: std_logic_vector(7 downto 0); signal plb_abus_net_x0: std_logic_vector(31 downto 0); signal plb_pavalid_net_x0: std_logic; signal plb_rnw_net_x0: std_logic; signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0); signal rddata: std_logic_vector(31 downto 0); signal rnwreg: std_logic; signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_rddbus_x0: std_logic_vector(31 downto 0); signal sl_wait_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_net_x0: std_logic; signal timer0_countto_din_x0: std_logic_vector(31 downto 0); signal timer0_countto_dout_x0: std_logic_vector(31 downto 0); signal timer0_countto_en_x0: std_logic; signal timer0_timeleft_dout_x0: std_logic_vector(31 downto 0); signal timer1_countto_din_x0: std_logic_vector(31 downto 0); signal timer1_countto_dout_x0: std_logic_vector(31 downto 0); signal timer1_countto_en_x0: std_logic; signal timer1_timeleft_dout_x0: std_logic_vector(31 downto 0); signal timer2_countto_din_x0: std_logic_vector(31 downto 0); signal timer2_countto_dout_x0: std_logic_vector(31 downto 0); signal timer2_countto_en_x0: std_logic; signal timer2_timeleft_dout_x0: std_logic_vector(31 downto 0); signal timer3_countto_din_x0: std_logic_vector(31 downto 0); signal timer3_countto_dout_x0: std_logic_vector(31 downto 0); signal timer3_countto_en_x0: std_logic; signal timer3_timeleft_dout_x0: std_logic_vector(31 downto 0); signal timer_control_r_dout_x0: std_logic_vector(31 downto 0); signal timer_control_w_din_x0: std_logic_vector(31 downto 0); signal timer_control_w_dout_x0: std_logic_vector(31 downto 0); signal timer_control_w_en_x0: std_logic; signal timer_status_dout_x0: std_logic_vector(31 downto 0); signal wrdbusreg: std_logic_vector(31 downto 0); begin ce_1_sg_x0 <= ce_1; clk_1_sg_x0 <= clk_1; timer0_timeleft_dout_x0 <= from_register; timer1_timeleft_dout_x0 <= from_register1; timer2_timeleft_dout_x0 <= from_register2; timer3_timeleft_dout_x0 <= from_register3; timer_control_r_dout_x0 <= from_register4; timer_status_dout_x0 <= from_register5; plb_abus_net_x0 <= plb_abus; plb_pavalid_net_x0 <= plb_pavalid; plb_rnw_net_x0 <= plb_rnw; plb_wrdbus_net_x0 <= plb_wrdbus; sg_plb_addrpref_net_x0 <= sg_plb_addrpref; splb_rst_net_x0 <= splb_rst; timer0_countto_dout_x0 <= to_register; timer1_countto_dout_x0 <= to_register1; timer2_countto_dout_x0 <= to_register2; timer3_countto_dout_x0 <= to_register3; timer_control_w_dout_x0 <= to_register4; constant5_x0 <= sl_wait_x0; plb_decode_x0 <= sl_addrack_x0; plb_decode_x1 <= sl_rdcomp_x0; plb_decode_x2 <= sl_wrdack_x0; plb_decode_x3 <= sl_rddack_x0; plb_decode_x4 <= sl_rddbus_x0; plb_memmap_x0 <= timer0_countto_din_x0; plb_memmap_x1 <= timer0_countto_en_x0; plb_memmap_x2 <= timer1_countto_din_x0; plb_memmap_x3 <= timer1_countto_en_x0; plb_memmap_x4 <= timer2_countto_din_x0; plb_memmap_x5 <= timer2_countto_en_x0; plb_memmap_x6 <= timer3_countto_din_x0; plb_memmap_x7 <= timer3_countto_en_x0; plb_memmap_x8 <= timer_control_w_din_x0; plb_memmap_x9 <= timer_control_w_en_x0; constant5: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => sl_wait_x0 ); plb_decode: entity work.mcode_block_b389f41afb port map ( addrpref => sg_plb_addrpref_net_x0, ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', plbabus => plb_abus_net_x0, plbpavalid(0) => plb_pavalid_net_x0, plbrnw(0) => plb_rnw_net_x0, plbrst(0) => splb_rst_net_x0, plbwrdbus => plb_wrdbus_net_x0, rddata => rddata, addrack(0) => sl_addrack_x0, bankaddr => bankaddr, linearaddr => linearaddr, rdcomp(0) => sl_rdcomp_x0, rddack(0) => sl_rddack_x0, rddbus => sl_rddbus_x0, rnwreg(0) => rnwreg, wrdack(0) => sl_wrdack_x0, wrdbusreg => wrdbusreg ); plb_memmap: entity work.mcode_block_b59e0d51fc port map ( addrack(0) => sl_addrack_x0, bankaddr => bankaddr, ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', linearaddr => linearaddr, rnwreg(0) => rnwreg, sm_timer0_countto => timer0_countto_dout_x0, sm_timer0_timeleft => timer0_timeleft_dout_x0, sm_timer1_countto => timer1_countto_dout_x0, sm_timer1_timeleft => timer1_timeleft_dout_x0, sm_timer2_countto => timer2_countto_dout_x0, sm_timer2_timeleft => timer2_timeleft_dout_x0, sm_timer3_countto => timer3_countto_dout_x0, sm_timer3_timeleft => timer3_timeleft_dout_x0, sm_timer_control_r => timer_control_r_dout_x0, sm_timer_control_w => timer_control_w_dout_x0, sm_timer_status => timer_status_dout_x0, wrdbus => wrdbusreg, read_bank_out => rddata, sm_timer0_countto_din => timer0_countto_din_x0, sm_timer0_countto_en(0) => timer0_countto_en_x0, sm_timer1_countto_din => timer1_countto_din_x0, sm_timer1_countto_en(0) => timer1_countto_en_x0, sm_timer2_countto_din => timer2_countto_din_x0, sm_timer2_countto_en(0) => timer2_countto_en_x0, sm_timer3_countto_din => timer3_countto_din_x0, sm_timer3_countto_en(0) => timer3_countto_en_x0, sm_timer_control_w_din => timer_control_w_din_x0, sm_timer_control_w_en(0) => timer_control_w_en_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "warp_timer/timer/S-R_Latch1" entity s_r_latch1_entity_5f9ce35768 is port ( ce_1: in std_logic; clk_1: in std_logic; r: in std_logic; s: in std_logic; q: out std_logic ); end s_r_latch1_entity_5f9ce35768; architecture structural of s_r_latch1_entity_5f9ce35768 is signal ce_1_sg_x1: std_logic; signal clk_1_sg_x1: std_logic; signal inverter_op_net: std_logic; signal logical2_y_net_x0: std_logic; signal logical3_y_net_x0: std_logic; signal register_q_net_x0: std_logic; begin ce_1_sg_x1 <= ce_1; clk_1_sg_x1 <= clk_1; logical2_y_net_x0 <= r; logical3_y_net_x0 <= s; q <= register_q_net_x0; inverter: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', ip(0) => register_q_net_x0, op(0) => inverter_op_net ); register_x0: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, d(0) => logical3_y_net_x0, en(0) => inverter_op_net, rst(0) => logical2_y_net_x0, q(0) => register_q_net_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "warp_timer/timer/posedge" entity posedge_entity_8c50a6be04 is port ( ce_1: in std_logic; clk_1: in std_logic; in_x0: in std_logic; out_x0: out std_logic ); end posedge_entity_8c50a6be04; architecture structural of posedge_entity_8c50a6be04 is signal ce_1_sg_x3: std_logic; signal clk_1_sg_x3: std_logic; signal delay_q_net: std_logic; signal inverter_op_net: std_logic; signal logical_y_net_x0: std_logic; signal slice_y_net_x0: std_logic; begin ce_1_sg_x3 <= ce_1; clk_1_sg_x3 <= clk_1; slice_y_net_x0 <= in_x0; out_x0 <= logical_y_net_x0; delay: entity work.xldelay generic map ( latency => 1, reg_retiming => 0, width => 1 ) port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, d(0) => slice_y_net_x0, en => '1', q(0) => delay_q_net ); inverter: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, clr => '0', ip(0) => delay_q_net, op(0) => inverter_op_net ); logical: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => slice_y_net_x0, d1(0) => inverter_op_net, y(0) => logical_y_net_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "warp_timer/timer" entity timer_entity_fee90fe8e7 is port ( ce_1: in std_logic; clk_1: in std_logic; countto: in std_logic_vector(31 downto 0); idlefordifs_inp: in std_logic; interruptreset: in std_logic; mode: in std_logic; pause: in std_logic; resume: in std_logic; start: in std_logic; stop: in std_logic; active: out std_logic; interrupt: out std_logic; paused: out std_logic; timeleft: out std_logic_vector(31 downto 0) ); end timer_entity_fee90fe8e7; architecture structural of timer_entity_fee90fe8e7 is signal addsub_s_net_x0: std_logic_vector(31 downto 0); signal ce_1_sg_x5: std_logic; signal clk_1_sg_x5: std_logic; signal constant1_op_net: std_logic; signal constant_op_net: std_logic_vector(31 downto 0); signal convert1_dout_net: std_logic; signal counter_op_net: std_logic_vector(31 downto 0); signal from_register1_data_out_net_x0: std_logic_vector(31 downto 0); signal idlefordifs_net_x0: std_logic; signal inverter_op_net: std_logic; signal logical1_y_net: std_logic; signal logical2_y_net_x0: std_logic; signal logical3_y_net_x0: std_logic; signal logical4_y_net_x0: std_logic; signal logical_y_net: std_logic; signal logical_y_net_x0: std_logic; signal logical_y_net_x1: std_logic; signal mux_y_net: std_logic; signal register_q_net_x2: std_logic; signal register_q_net_x3: std_logic; signal relational1_op_net: std_logic; signal relational_op_net_x0: std_logic; signal slice1_y_net_x0: std_logic; signal slice2_y_net_x1: std_logic; signal slice3_y_net_x0: std_logic; signal slice4_y_net_x0: std_logic; signal slice5_y_net_x1: std_logic; signal slice_y_net_x1: std_logic; begin ce_1_sg_x5 <= ce_1; clk_1_sg_x5 <= clk_1; from_register1_data_out_net_x0 <= countto; idlefordifs_net_x0 <= idlefordifs_inp; slice5_y_net_x1 <= interruptreset; slice4_y_net_x0 <= mode; slice3_y_net_x0 <= pause; slice2_y_net_x1 <= resume; slice_y_net_x1 <= start; slice1_y_net_x0 <= stop; active <= register_q_net_x2; interrupt <= register_q_net_x3; paused <= logical4_y_net_x0; timeleft <= addsub_s_net_x0; addsub: entity work.xladdsub generic map ( a_arith => xlUnsigned, a_bin_pt => 0, a_width => 32, b_arith => xlUnsigned, b_bin_pt => 0, b_width => 32, c_has_b_out => 0, c_has_c_out => 0, c_has_q => 0, c_has_q_b_out => 0, c_has_q_c_out => 0, c_has_s => 1, c_latency => 0, c_output_width => 33, core_name0 => "adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e", extra_registers => 0, full_s_arith => 2, full_s_width => 33, latency => 0, mode => 2, overflow => 1, quantization => 1, s_arith => xlUnsigned, s_bin_pt => 0, s_width => 32 ) port map ( a => from_register1_data_out_net_x0, b => counter_op_net, ce => ce_1_sg_x5, clk => clk_1_sg_x5, clr => '0', en => "1", s => addsub_s_net_x0 ); constant1: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant1_op_net ); constant_x0: entity work.constant_37567836aa port map ( ce => '0', clk => '0', clr => '0', op => constant_op_net ); convert1: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => '0', clk => '0', clr => '0', din(0) => mux_y_net, dout(0) => convert1_dout_net ); counter: entity work.xlcounter_free generic map ( core_name0 => "binary_counter_virtex2p_7_0_b57302a6bcbb6876", op_arith => xlUnsigned, op_width => 32 ) port map ( ce => ce_1_sg_x5, clk => clk_1_sg_x5, clr => '0', en(0) => logical_y_net, rst(0) => logical1_y_net, op => counter_op_net ); inverter: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x5, clk => clk_1_sg_x5, clr => '0', ip(0) => register_q_net_x2, op(0) => inverter_op_net ); logical: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => convert1_dout_net, d1(0) => register_q_net_x2, y(0) => logical_y_net ); logical1: entity work.logical_6cb8f0ce02 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational_op_net_x0, d1(0) => slice1_y_net_x0, d2(0) => logical_y_net_x0, y(0) => logical1_y_net ); logical2: entity work.logical_6cb8f0ce02 port map ( ce => '0', clk => '0', clr => '0', d0(0) => slice1_y_net_x0, d1(0) => slice3_y_net_x0, d2(0) => relational_op_net_x0, y(0) => logical2_y_net_x0 ); logical3: entity work.logical_aacf6e1b0e port map ( ce => '0', clk => '0', clr => '0', d0(0) => logical_y_net_x0, d1(0) => logical_y_net_x1, y(0) => logical3_y_net_x0 ); logical4: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational1_op_net, d1(0) => inverter_op_net, y(0) => logical4_y_net_x0 ); mux: entity work.mux_112ed141f4 port map ( ce => '0', clk => '0', clr => '0', d0(0) => constant1_op_net, d1(0) => idlefordifs_net_x0, sel(0) => slice4_y_net_x0, y(0) => mux_y_net ); posedge1_8332b77348: entity work.posedge_entity_8c50a6be04 port map ( ce_1 => ce_1_sg_x5, clk_1 => clk_1_sg_x5, in_x0 => slice2_y_net_x1, out_x0 => logical_y_net_x1 ); posedge_8c50a6be04: entity work.posedge_entity_8c50a6be04 port map ( ce_1 => ce_1_sg_x5, clk_1 => clk_1_sg_x5, in_x0 => slice_y_net_x1, out_x0 => logical_y_net_x0 ); relational: entity work.relational_3ffd1d0a40 port map ( a => from_register1_data_out_net_x0, b => counter_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational_op_net_x0 ); relational1: entity work.relational_34fc311f5b port map ( a => counter_op_net, b => constant_op_net, ce => ce_1_sg_x5, clk => clk_1_sg_x5, clr => '0', op(0) => relational1_op_net ); s_r_latch1_5f9ce35768: entity work.s_r_latch1_entity_5f9ce35768 port map ( ce_1 => ce_1_sg_x5, clk_1 => clk_1_sg_x5, r => logical2_y_net_x0, s => logical3_y_net_x0, q => register_q_net_x2 ); s_r_latch2_722d862217: entity work.s_r_latch1_entity_5f9ce35768 port map ( ce_1 => ce_1_sg_x5, clk_1 => clk_1_sg_x5, r => slice5_y_net_x1, s => relational_op_net_x0, q => register_q_net_x3 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "warp_timer/timer_control" entity timer_control_entity_09b11c57d8 is port ( constant6_x0: out std_logic ); end timer_control_entity_09b11c57d8; architecture structural of timer_control_entity_09b11c57d8 is signal constant6_op_net_x0: std_logic; begin constant6_x0 <= constant6_op_net_x0; constant6: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant6_op_net_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "warp_timer" entity warp_timer is port ( ce_1: in std_logic; clk_1: in std_logic; data_out: in std_logic_vector(31 downto 0); data_out_x0: in std_logic_vector(31 downto 0); data_out_x1: in std_logic_vector(31 downto 0); data_out_x2: in std_logic_vector(31 downto 0); data_out_x3: in std_logic_vector(31 downto 0); data_out_x4: in std_logic_vector(31 downto 0); data_out_x5: in std_logic_vector(31 downto 0); data_out_x6: in std_logic_vector(31 downto 0); data_out_x7: in std_logic_vector(31 downto 0); data_out_x8: in std_logic_vector(31 downto 0); data_out_x9: in std_logic_vector(31 downto 0); dout_x4: in std_logic_vector(31 downto 0); dout_x5: in std_logic_vector(31 downto 0); dout_x6: in std_logic_vector(31 downto 0); dout_x7: in std_logic_vector(31 downto 0); dout_x8: in std_logic_vector(31 downto 0); idlefordifs: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; data_in: out std_logic_vector(31 downto 0); data_in_x0: out std_logic_vector(31 downto 0); data_in_x1: out std_logic_vector(31 downto 0); data_in_x2: out std_logic_vector(31 downto 0); data_in_x3: out std_logic_vector(31 downto 0); data_in_x4: out std_logic_vector(31 downto 0); data_in_x5: out std_logic_vector(31 downto 0); data_in_x6: out std_logic_vector(31 downto 0); data_in_x7: out std_logic_vector(31 downto 0); data_in_x8: out std_logic_vector(31 downto 0); data_in_x9: out std_logic_vector(31 downto 0); en: out std_logic; en_x0: out std_logic; en_x1: out std_logic; en_x2: out std_logic; en_x3: out std_logic; en_x4: out std_logic; en_x5: out std_logic; en_x6: out std_logic; en_x7: out std_logic; en_x8: out std_logic; en_x9: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; timer0_active: out std_logic; timer1_active: out std_logic; timer2_active: out std_logic; timer3_active: out std_logic; timerexpire: out std_logic ); end warp_timer; architecture structural of warp_timer is signal ce_1_sg_x21: std_logic; signal clk_1_sg_x21: std_logic; signal concat1_y_net: std_logic_vector(2 downto 0); signal concat2_y_net: std_logic_vector(2 downto 0); signal concat3_y_net: std_logic_vector(2 downto 0); signal concat4_y_net: std_logic_vector(2 downto 0); signal convert1_dout_net: std_logic_vector(7 downto 0); signal convert2_dout_net: std_logic_vector(7 downto 0); signal convert3_dout_net: std_logic_vector(7 downto 0); signal convert_dout_net: std_logic_vector(7 downto 0); signal data_in_net: std_logic_vector(31 downto 0); signal data_in_x0_net: std_logic_vector(31 downto 0); signal data_in_x1_net: std_logic_vector(31 downto 0); signal data_in_x2_net: std_logic_vector(31 downto 0); signal data_in_x3_net: std_logic_vector(31 downto 0); signal data_in_x4_net: std_logic_vector(31 downto 0); signal data_in_x5_net: std_logic_vector(31 downto 0); signal data_in_x6_net: std_logic_vector(31 downto 0); signal data_in_x7_net: std_logic_vector(31 downto 0); signal data_in_x8_net: std_logic_vector(31 downto 0); signal data_out_net: std_logic_vector(31 downto 0); signal data_out_x0_net: std_logic_vector(31 downto 0); signal data_out_x1_net: std_logic_vector(31 downto 0); signal data_out_x2_net: std_logic_vector(31 downto 0); signal data_out_x3_net: std_logic_vector(31 downto 0); signal data_out_x4_net: std_logic_vector(31 downto 0); signal data_out_x5_net: std_logic_vector(31 downto 0); signal data_out_x6_net: std_logic_vector(31 downto 0); signal data_out_x7_net: std_logic_vector(31 downto 0); signal data_out_x8_net: std_logic_vector(31 downto 0); signal dout_x4_net: std_logic_vector(31 downto 0); signal dout_x5_net: std_logic_vector(31 downto 0); signal dout_x6_net: std_logic_vector(31 downto 0); signal dout_x7_net: std_logic_vector(31 downto 0); signal dout_x8_net: std_logic_vector(31 downto 0); signal en_net: std_logic; signal en_x0_net: std_logic; signal en_x1_net: std_logic; signal en_x2_net: std_logic; signal en_x3_net: std_logic; signal en_x4_net: std_logic; signal en_x5_net: std_logic; signal en_x6_net: std_logic; signal en_x7_net: std_logic; signal en_x8_net: std_logic; signal en_x9_net: std_logic; signal from_register2_data_out_net_x0: std_logic_vector(31 downto 0); signal idlefordifs_net: std_logic; signal logical4_y_net_x0: std_logic; signal logical4_y_net_x1: std_logic; signal logical4_y_net_x2: std_logic; signal logical4_y_net_x3: std_logic; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal register_q_net_x3: std_logic; signal register_q_net_x5: std_logic; signal register_q_net_x7: std_logic; signal register_q_net_x9: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal slice10_y_net_x0: std_logic; signal slice11_y_net_x1: std_logic; signal slice12_y_net_x1: std_logic; signal slice13_y_net_x0: std_logic; signal slice14_y_net_x1: std_logic; signal slice15_y_net_x0: std_logic; signal slice16_y_net_x0: std_logic; signal slice17_y_net_x1: std_logic; signal slice18_y_net_x1: std_logic; signal slice19_y_net_x0: std_logic; signal slice1_y_net_x0: std_logic; signal slice20_y_net_x1: std_logic; signal slice21_y_net_x0: std_logic; signal slice22_y_net_x0: std_logic; signal slice23_y_net_x1: std_logic; signal slice2_y_net_x1: std_logic; signal slice3_y_net_x0: std_logic; signal slice4_y_net_x0: std_logic; signal slice5_y_net_x1: std_logic; signal slice6_y_net_x1: std_logic; signal slice7_y_net_x0: std_logic; signal slice8_y_net_x1: std_logic; signal slice9_y_net_x0: std_logic; signal slice_y_net_x1: std_logic; signal splb_rst_net: std_logic; signal timer0_active_net: std_logic; signal timer1_active_net: std_logic; signal timer2_active_net: std_logic; signal timer3_active_net: std_logic; signal timerexpire_net: std_logic; begin ce_1_sg_x21 <= ce_1; clk_1_sg_x21 <= clk_1; data_out_net <= data_out; data_out_x0_net <= data_out_x0; data_out_x1_net <= data_out_x1; data_out_x2_net <= data_out_x2; data_out_x3_net <= data_out_x3; data_out_x4_net <= data_out_x4; data_out_x5_net <= data_out_x5; data_out_x6_net <= data_out_x6; data_out_x7_net <= data_out_x7; data_out_x8_net <= data_out_x8; from_register2_data_out_net_x0 <= data_out_x9; dout_x4_net <= dout_x4; dout_x5_net <= dout_x5; dout_x6_net <= dout_x6; dout_x7_net <= dout_x7; dout_x8_net <= dout_x8; idlefordifs_net <= idlefordifs; plb_abus_net <= plb_abus; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; data_in <= data_in_net; data_in_x0 <= data_in_x0_net; data_in_x1 <= data_in_x1_net; data_in_x2 <= data_in_x2_net; data_in_x3 <= data_in_x3_net; data_in_x4 <= data_in_x4_net; data_in_x5 <= data_in_x5_net; data_in_x6 <= data_in_x6_net; data_in_x7 <= data_in_x7_net; data_in_x8 <= data_in_x8_net; data_in_x9 <= from_register2_data_out_net_x0; en <= en_net; en_x0 <= en_x0_net; en_x1 <= en_x1_net; en_x2 <= en_x2_net; en_x3 <= en_x3_net; en_x4 <= en_x4_net; en_x5 <= en_x5_net; en_x6 <= en_x6_net; en_x7 <= en_x7_net; en_x8 <= en_x8_net; en_x9 <= en_x9_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x1; sl_wrdack <= sl_wrdack_x1; timer0_active <= timer0_active_net; timer1_active <= timer1_active_net; timer2_active <= timer2_active_net; timer3_active <= timer3_active_net; timerexpire <= timerexpire_net; concat: entity work.concat_a1e126f11c port map ( ce => '0', clk => '0', clr => '0', in0 => convert3_dout_net, in1 => convert2_dout_net, in2 => convert1_dout_net, in3 => convert_dout_net, y => data_in_x3_net ); concat1: entity work.concat_09e13b86e0 port map ( ce => '0', clk => '0', clr => '0', in0(0) => logical4_y_net_x0, in1(0) => timer0_active_net, in2(0) => register_q_net_x3, y => concat1_y_net ); concat2: entity work.concat_09e13b86e0 port map ( ce => '0', clk => '0', clr => '0', in0(0) => logical4_y_net_x1, in1(0) => timer1_active_net, in2(0) => register_q_net_x5, y => concat2_y_net ); concat3: entity work.concat_09e13b86e0 port map ( ce => '0', clk => '0', clr => '0', in0(0) => logical4_y_net_x2, in1(0) => timer2_active_net, in2(0) => register_q_net_x7, y => concat3_y_net ); concat4: entity work.concat_09e13b86e0 port map ( ce => '0', clk => '0', clr => '0', in0(0) => logical4_y_net_x3, in1(0) => timer3_active_net, in2(0) => register_q_net_x9, y => concat4_y_net ); constant1: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => en_net ); constant2: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => en_x0_net ); constant3: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => en_x1_net ); constant4: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => en_x2_net ); constant5: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => en_x3_net ); convert: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 1, din_bin_pt => 0, din_width => 3, dout_arith => 1, dout_bin_pt => 0, dout_width => 8, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => '0', clk => '0', clr => '0', din => concat1_y_net, dout => convert_dout_net ); convert1: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 1, din_bin_pt => 0, din_width => 3, dout_arith => 1, dout_bin_pt => 0, dout_width => 8, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => '0', clk => '0', clr => '0', din => concat2_y_net, dout => convert1_dout_net ); convert2: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 1, din_bin_pt => 0, din_width => 3, dout_arith => 1, dout_bin_pt => 0, dout_width => 8, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => '0', clk => '0', clr => '0', din => concat3_y_net, dout => convert2_dout_net ); convert3: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 1, din_bin_pt => 0, din_width => 3, dout_arith => 1, dout_bin_pt => 0, dout_width => 8, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => '0', clk => '0', clr => '0', din => concat4_y_net, dout => convert3_dout_net ); edk_processor_cddda35d8e: entity work.edk_processor_entity_cddda35d8e port map ( ce_1 => ce_1_sg_x21, clk_1 => clk_1_sg_x21, from_register => data_out_x3_net, from_register1 => data_out_x4_net, from_register2 => data_out_x5_net, from_register3 => data_out_x6_net, from_register4 => data_out_x7_net, from_register5 => data_out_x8_net, plb_abus => plb_abus_net, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, to_register => dout_x4_net, to_register1 => dout_x5_net, to_register2 => dout_x6_net, to_register3 => dout_x7_net, to_register4 => dout_x8_net, constant5_x0 => sl_wait_net, plb_decode_x0 => sl_addrack_net, plb_decode_x1 => sl_rdcomp_net, plb_decode_x2 => sl_wrdack_x1, plb_decode_x3 => sl_rddack_net, plb_decode_x4 => sl_rddbus_net, plb_memmap_x0 => data_in_x4_net, plb_memmap_x1 => en_x4_net, plb_memmap_x2 => data_in_x5_net, plb_memmap_x3 => en_x5_net, plb_memmap_x4 => data_in_x6_net, plb_memmap_x5 => en_x6_net, plb_memmap_x6 => data_in_x7_net, plb_memmap_x7 => en_x7_net, plb_memmap_x8 => data_in_x8_net, plb_memmap_x9 => en_x8_net ); logical: entity work.logical_a6d07705dd port map ( ce => '0', clk => '0', clr => '0', d0(0) => register_q_net_x3, d1(0) => register_q_net_x5, d2(0) => register_q_net_x7, d3(0) => register_q_net_x9, y(0) => timerexpire_net ); slice: entity work.xlslice generic map ( new_lsb => 0, new_msb => 0, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice_y_net_x1 ); slice1: entity work.xlslice generic map ( new_lsb => 1, new_msb => 1, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice1_y_net_x0 ); slice10: entity work.xlslice generic map ( new_lsb => 12, new_msb => 12, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice10_y_net_x0 ); slice11: entity work.xlslice generic map ( new_lsb => 13, new_msb => 13, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice11_y_net_x1 ); slice12: entity work.xlslice generic map ( new_lsb => 16, new_msb => 16, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice12_y_net_x1 ); slice13: entity work.xlslice generic map ( new_lsb => 17, new_msb => 17, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice13_y_net_x0 ); slice14: entity work.xlslice generic map ( new_lsb => 18, new_msb => 18, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice14_y_net_x1 ); slice15: entity work.xlslice generic map ( new_lsb => 19, new_msb => 19, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice15_y_net_x0 ); slice16: entity work.xlslice generic map ( new_lsb => 20, new_msb => 20, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice16_y_net_x0 ); slice17: entity work.xlslice generic map ( new_lsb => 21, new_msb => 21, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice17_y_net_x1 ); slice18: entity work.xlslice generic map ( new_lsb => 24, new_msb => 24, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice18_y_net_x1 ); slice19: entity work.xlslice generic map ( new_lsb => 25, new_msb => 25, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice19_y_net_x0 ); slice2: entity work.xlslice generic map ( new_lsb => 2, new_msb => 2, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice2_y_net_x1 ); slice20: entity work.xlslice generic map ( new_lsb => 26, new_msb => 26, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice20_y_net_x1 ); slice21: entity work.xlslice generic map ( new_lsb => 27, new_msb => 27, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice21_y_net_x0 ); slice22: entity work.xlslice generic map ( new_lsb => 28, new_msb => 28, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice22_y_net_x0 ); slice23: entity work.xlslice generic map ( new_lsb => 29, new_msb => 29, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice23_y_net_x1 ); slice3: entity work.xlslice generic map ( new_lsb => 3, new_msb => 3, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice3_y_net_x0 ); slice4: entity work.xlslice generic map ( new_lsb => 4, new_msb => 4, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice4_y_net_x0 ); slice5: entity work.xlslice generic map ( new_lsb => 5, new_msb => 5, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice5_y_net_x1 ); slice6: entity work.xlslice generic map ( new_lsb => 8, new_msb => 8, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice6_y_net_x1 ); slice7: entity work.xlslice generic map ( new_lsb => 9, new_msb => 9, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice7_y_net_x0 ); slice8: entity work.xlslice generic map ( new_lsb => 10, new_msb => 10, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice8_y_net_x1 ); slice9: entity work.xlslice generic map ( new_lsb => 11, new_msb => 11, x_width => 32, y_width => 1 ) port map ( x => from_register2_data_out_net_x0, y(0) => slice9_y_net_x0 ); timer1_a9ea58dee7: entity work.timer_entity_fee90fe8e7 port map ( ce_1 => ce_1_sg_x21, clk_1 => clk_1_sg_x21, countto => data_out_x0_net, idlefordifs_inp => idlefordifs_net, interruptreset => slice11_y_net_x1, mode => slice10_y_net_x0, pause => slice9_y_net_x0, resume => slice8_y_net_x1, start => slice6_y_net_x1, stop => slice7_y_net_x0, active => timer1_active_net, interrupt => register_q_net_x5, paused => logical4_y_net_x1, timeleft => data_in_x0_net ); timer2_15928ecc3b: entity work.timer_entity_fee90fe8e7 port map ( ce_1 => ce_1_sg_x21, clk_1 => clk_1_sg_x21, countto => data_out_x1_net, idlefordifs_inp => idlefordifs_net, interruptreset => slice17_y_net_x1, mode => slice16_y_net_x0, pause => slice15_y_net_x0, resume => slice14_y_net_x1, start => slice12_y_net_x1, stop => slice13_y_net_x0, active => timer2_active_net, interrupt => register_q_net_x7, paused => logical4_y_net_x2, timeleft => data_in_x1_net ); timer3_4ea9afe7c4: entity work.timer_entity_fee90fe8e7 port map ( ce_1 => ce_1_sg_x21, clk_1 => clk_1_sg_x21, countto => data_out_x2_net, idlefordifs_inp => idlefordifs_net, interruptreset => slice23_y_net_x1, mode => slice22_y_net_x0, pause => slice21_y_net_x0, resume => slice20_y_net_x1, start => slice18_y_net_x1, stop => slice19_y_net_x0, active => timer3_active_net, interrupt => register_q_net_x9, paused => logical4_y_net_x3, timeleft => data_in_x2_net ); timer_control_09b11c57d8: entity work.timer_control_entity_09b11c57d8 port map ( constant6_x0 => en_x9_net ); timer_fee90fe8e7: entity work.timer_entity_fee90fe8e7 port map ( ce_1 => ce_1_sg_x21, clk_1 => clk_1_sg_x21, countto => data_out_net, idlefordifs_inp => idlefordifs_net, interruptreset => slice5_y_net_x1, mode => slice4_y_net_x0, pause => slice3_y_net_x0, resume => slice2_y_net_x1, start => slice_y_net_x1, stop => slice1_y_net_x0, active => timer0_active_net, interrupt => register_q_net_x3, paused => logical4_y_net_x0, timeleft => data_in_net ); end structural; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; use work.clock_pkg.all; entity xlclkprobe is port (clk : in std_logic; clr : in std_logic; ce : in std_logic; fakeOutForXst : out std_logic); end xlclkprobe; architecture behavior of xlclkprobe is begin fakeOutForXst <= '0'; -- synopsys translate_off work.clock_pkg.int_clk <= clk; -- synopsys translate_on end behavior; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on entity xlclockdriver is generic ( period: integer := 2; log_2_period: integer := 0; pipeline_regs: integer := 5; use_bufg: integer := 0 ); port ( sysclk: in std_logic; sysclr: in std_logic; sysce: in std_logic; clk: out std_logic; clr: out std_logic; ce: out std_logic ); end xlclockdriver; architecture behavior of xlclockdriver is component bufg port ( i: in std_logic; o: out std_logic ); end component; component synth_reg_w_init generic ( width: integer; init_index: integer; init_value: bit_vector; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function size_of_uint(inp: integer; power_of_2: boolean) return integer is constant inp_vec: std_logic_vector(31 downto 0) := integer_to_std_logic_vector(inp,32, xlUnsigned); variable result: integer; begin result := 32; for i in 0 to 31 loop if inp_vec(i) = '1' then result := i; end if; end loop; if power_of_2 then return result; else return result+1; end if; end; function is_power_of_2(inp: std_logic_vector) return boolean is constant width: integer := inp'length; variable vec: std_logic_vector(width - 1 downto 0); variable single_bit_set: boolean; variable more_than_one_bit_set: boolean; variable result: boolean; begin vec := inp; single_bit_set := false; more_than_one_bit_set := false; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if width > 0 then for i in 0 to width - 1 loop if vec(i) = '1' then if single_bit_set then more_than_one_bit_set := true; end if; single_bit_set := true; end if; end loop; end if; if (single_bit_set and not(more_than_one_bit_set)) then result := true; else result := false; end if; return result; end; function ce_reg_init_val(index, period : integer) return integer is variable result: integer; begin result := 0; if ((index mod period) = 0) then result := 1; end if; return result; end; function remaining_pipe_regs(num_pipeline_regs, period : integer) return integer is variable factor, result: integer; begin factor := (num_pipeline_regs / period); result := num_pipeline_regs - (period * factor) + 1; return result; end; function sg_min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; constant max_pipeline_regs : integer := 8; constant pipe_regs : integer := 5; constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); constant period_floor: integer := max(2, period); constant power_of_2_counter: boolean := is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); constant cnt_width: integer := size_of_uint(period_floor, power_of_2_counter); constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT : string; attribute MAX_FANOUT of ce_vec:signal is "REDUCE"; signal internal_ce: std_logic_vector(0 downto 0); signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); begin clk <= sysclk; clr <= sysclr; cntr_gen: process(sysclk) begin if sysclk'event and sysclk = '1' then if (sysce = '1') then if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then clk_num <= (others => '0'); else clk_num <= clk_num + 1; end if; end if; end if; end process; clr_gen: process(clk_num, sysclr) begin if power_of_2_counter then cnt_clr(0) <= sysclr; else if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 or sysclr = '1') then cnt_clr(0) <= '1'; else cnt_clr(0) <= '0'; end if; end if; end process; clr_reg: synth_reg_w_init generic map ( width => 1, init_index => 0, init_value => b"0000", latency => 1 ) port map ( i => cnt_clr, ce => sysce, clr => sysclr, clk => sysclk, o => cnt_clr_dly ); pipelined_ce : if period > 1 generate ce_gen: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec(num_pipeline_regs) <= '1'; else ce_vec(num_pipeline_regs) <= '0'; end if; end process; ce_pipeline: for index in num_pipeline_regs downto 1 generate ce_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec(index-1 downto index-1) ); end generate; internal_ce <= ce_vec(0 downto 0); end generate; use_bufg_true: if period > 1 and use_bufg = 1 generate ce_bufg_inst: bufg port map ( i => internal_ce(0), o => ce ); end generate; use_bufg_false: if period > 1 and (use_bufg = 0) generate ce <= internal_ce(0); end generate; generate_system_clk: if period = 1 generate ce <= sysce; end generate; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 10.1.2 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xland2 is port ( a : in std_logic; b : in std_logic; dout : out std_logic ); end xland2; architecture behavior of xland2 is begin dout <= a and b; end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity default_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; ce_1: out std_logic; clk_1: out std_logic ); end default_clock_driver; architecture structural of default_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; ce_1 <= xlclockdriver_1_ce; clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity warp_timer_cw is port ( ce: in std_logic := '1'; clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) idlefordifs: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; timer0_active: out std_logic; timer1_active: out std_logic; timer2_active: out std_logic; timer3_active: out std_logic; timerexpire: out std_logic ); end warp_timer_cw; architecture structural of warp_timer_cw is component xlpersistentdff port ( clk: in std_logic; d: in std_logic; q: out std_logic ); end component; attribute syn_black_box: boolean; attribute syn_black_box of xlpersistentdff: component is true; attribute box_type: string; attribute box_type of xlpersistentdff: component is "black_box"; attribute syn_noprune: boolean; attribute optimize_primitives: boolean; attribute dont_touch: boolean; attribute syn_noprune of xlpersistentdff: component is true; attribute optimize_primitives of xlpersistentdff: component is false; attribute dont_touch of xlpersistentdff: component is true; signal ce_1_sg_x21: std_logic; attribute MAX_FANOUT: string; attribute MAX_FANOUT of ce_1_sg_x21: signal is "REDUCE"; signal clkNet: std_logic; signal clk_1_sg_x21: std_logic; signal data_in_net: std_logic_vector(31 downto 0); signal data_in_x0_net: std_logic_vector(31 downto 0); signal data_in_x1_net: std_logic_vector(31 downto 0); signal data_in_x2_net: std_logic_vector(31 downto 0); signal data_in_x3_net: std_logic_vector(31 downto 0); signal data_in_x4_net: std_logic_vector(31 downto 0); signal data_in_x5_net: std_logic_vector(31 downto 0); signal data_in_x6_net: std_logic_vector(31 downto 0); signal data_in_x7_net: std_logic_vector(31 downto 0); signal data_in_x8_net: std_logic_vector(31 downto 0); signal data_out_net: std_logic_vector(31 downto 0); signal data_out_x0_net: std_logic_vector(31 downto 0); signal data_out_x1_net: std_logic_vector(31 downto 0); signal data_out_x2_net: std_logic_vector(31 downto 0); signal data_out_x3_net: std_logic_vector(31 downto 0); signal data_out_x4_net: std_logic_vector(31 downto 0); signal data_out_x5_net: std_logic_vector(31 downto 0); signal data_out_x6_net: std_logic_vector(31 downto 0); signal data_out_x7_net: std_logic_vector(31 downto 0); signal data_out_x8_net: std_logic_vector(31 downto 0); signal en_net: std_logic; signal en_x0_net: std_logic; signal en_x1_net: std_logic; signal en_x2_net: std_logic; signal en_x3_net: std_logic; signal en_x4_net: std_logic; signal en_x5_net: std_logic; signal en_x6_net: std_logic; signal en_x7_net: std_logic; signal en_x8_net: std_logic; signal en_x9_net: std_logic; signal from_register2_data_out_net_x0: std_logic_vector(31 downto 0); signal from_register2_data_out_net_x1: std_logic_vector(31 downto 0); signal idlefordifs_net: std_logic; signal persistentdff_inst_q: std_logic; attribute syn_keep: boolean; attribute syn_keep of persistentdff_inst_q: signal is true; attribute keep: boolean; attribute keep of persistentdff_inst_q: signal is true; attribute preserve_signal: boolean; attribute preserve_signal of persistentdff_inst_q: signal is true; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal sl_wrdack_x2: std_logic; signal splb_rst_net: std_logic; signal timer0_active_net: std_logic; signal timer0_countTo_reg_ce: std_logic; signal timer0_timeLeft_reg_ce: std_logic; signal timer1_active_net: std_logic; signal timer1_countTo_reg_ce: std_logic; signal timer1_timeLeft_reg_ce: std_logic; signal timer2_active_net: std_logic; signal timer2_countTo_reg_ce: std_logic; signal timer2_timeLeft_reg_ce: std_logic; signal timer3_active_net: std_logic; signal timer3_countTo_reg_ce: std_logic; signal timer3_timeLeft_reg_ce: std_logic; signal timer_control_r_reg_ce: std_logic; signal timer_control_w_reg_ce: std_logic; signal timer_status_reg_ce: std_logic; signal timerexpire_net: std_logic; begin clkNet <= clk; idlefordifs_net <= idlefordifs; plb_abus_net <= plb_abus; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x2; sl_wrdack <= sl_wrdack_x1; timer0_active <= timer0_active_net; timer1_active <= timer1_active_net; timer2_active <= timer2_active_net; timer3_active <= timer3_active_net; timerexpire <= timerexpire_net; clk_probe: entity work.xlclkprobe port map ( ce => '1', clk => clkNet, clr => '0' ); default_clock_driver_x0: entity work.default_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet, ce_1 => ce_1_sg_x21, clk_1 => clk_1_sg_x21 ); persistentdff_inst: xlpersistentdff port map ( clk => clkNet, d => persistentdff_inst_q, q => persistentdff_inst_q ); timer0_countTo: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer0_countTo_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x4_net, o => data_out_net ); timer0_countTo_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x4_net, dout => timer0_countTo_reg_ce ); timer0_timeLeft: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer0_timeLeft_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_net, o => data_out_x3_net ); timer0_timeLeft_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_net, dout => timer0_timeLeft_reg_ce ); timer1_countTo: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer1_countTo_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x5_net, o => data_out_x0_net ); timer1_countTo_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x5_net, dout => timer1_countTo_reg_ce ); timer1_timeLeft: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer1_timeLeft_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x0_net, o => data_out_x4_net ); timer1_timeLeft_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x0_net, dout => timer1_timeLeft_reg_ce ); timer2_countTo: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer2_countTo_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x6_net, o => data_out_x1_net ); timer2_countTo_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x6_net, dout => timer2_countTo_reg_ce ); timer2_timeLeft: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer2_timeLeft_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x1_net, o => data_out_x5_net ); timer2_timeLeft_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x1_net, dout => timer2_timeLeft_reg_ce ); timer3_countTo: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer3_countTo_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x7_net, o => data_out_x2_net ); timer3_countTo_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x7_net, dout => timer3_countTo_reg_ce ); timer3_timeLeft: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer3_timeLeft_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x2_net, o => data_out_x6_net ); timer3_timeLeft_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x2_net, dout => timer3_timeLeft_reg_ce ); timer_control_r: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer_control_r_reg_ce, clk => clk_1_sg_x21, clr => '0', i => from_register2_data_out_net_x1, o => data_out_x7_net ); timer_control_r_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x9_net, dout => timer_control_r_reg_ce ); timer_control_w: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer_control_w_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x8_net, o => from_register2_data_out_net_x0 ); timer_control_w_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x8_net, dout => timer_control_w_reg_ce ); timer_status: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000000000000000000000000000000", latency => 1 ) port map ( ce => timer_status_reg_ce, clk => clk_1_sg_x21, clr => '0', i => data_in_x3_net, o => data_out_x8_net ); timer_status_ce_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x21, b => en_x3_net, dout => timer_status_reg_ce ); warp_timer_x0: entity work.warp_timer port map ( ce_1 => ce_1_sg_x21, clk_1 => clk_1_sg_x21, data_out => data_out_net, data_out_x0 => data_out_x0_net, data_out_x1 => data_out_x1_net, data_out_x2 => data_out_x2_net, data_out_x3 => data_out_x3_net, data_out_x4 => data_out_x4_net, data_out_x5 => data_out_x5_net, data_out_x6 => data_out_x6_net, data_out_x7 => data_out_x7_net, data_out_x8 => data_out_x8_net, data_out_x9 => from_register2_data_out_net_x0, dout_x4 => data_out_net, dout_x5 => data_out_x0_net, dout_x6 => data_out_x1_net, dout_x7 => data_out_x2_net, dout_x8 => from_register2_data_out_net_x0, idlefordifs => idlefordifs_net, plb_abus => plb_abus_net, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, data_in => data_in_net, data_in_x0 => data_in_x0_net, data_in_x1 => data_in_x1_net, data_in_x2 => data_in_x2_net, data_in_x3 => data_in_x3_net, data_in_x4 => data_in_x4_net, data_in_x5 => data_in_x5_net, data_in_x6 => data_in_x6_net, data_in_x7 => data_in_x7_net, data_in_x8 => data_in_x8_net, data_in_x9 => from_register2_data_out_net_x1, en => en_net, en_x0 => en_x0_net, en_x1 => en_x1_net, en_x2 => en_x2_net, en_x3 => en_x3_net, en_x4 => en_x4_net, en_x5 => en_x5_net, en_x6 => en_x6_net, en_x7 => en_x7_net, en_x8 => en_x8_net, en_x9 => en_x9_net, sl_addrack => sl_addrack_net, sl_rdcomp => sl_rdcomp_net, sl_rddack => sl_rddack_net, sl_rddbus => sl_rddbus_net, sl_wait => sl_wait_net, sl_wrcomp => sl_wrdack_x2, sl_wrdack => sl_wrdack_x1, timer0_active => timer0_active_net, timer1_active => timer1_active_net, timer2_active => timer2_active_net, timer3_active => timer3_active_net, timerexpire => timerexpire_net ); end structural;