[1042] | 1 | ------------------------------------------------------------------- |
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| 2 | -- System Generator version 10.1.00 VHDL source file. |
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| 3 | -- |
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| 4 | -- Copyright(C) 2007 by Xilinx, Inc. All rights reserved. This |
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| 5 | -- text/file contains proprietary, confidential information of Xilinx, |
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| 6 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
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| 7 | -- copied and/or disclosed only pursuant to the terms of a valid license |
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| 8 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
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| 9 | -- this text/file solely for design, simulation, implementation and |
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| 10 | -- creation of design files limited to Xilinx devices or technologies. |
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| 11 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
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| 12 | -- and immediately terminates your license unless covered by a separate |
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| 13 | -- agreement. |
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| 14 | -- |
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| 15 | -- Xilinx is providing this design, code, or information "as is" solely |
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| 16 | -- for use in developing programs and solutions for Xilinx devices. By |
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| 17 | -- providing this design, code, or information as one possible |
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| 18 | -- implementation of this feature, application or standard, Xilinx is |
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| 19 | -- making no representation that this implementation is free from any |
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| 20 | -- claims of infringement. You are responsible for obtaining any rights |
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| 21 | -- you may require for your implementation. Xilinx expressly disclaims |
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| 22 | -- any warranty whatsoever with respect to the adequacy of the |
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| 23 | -- implementation, including but not limited to warranties of |
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| 24 | -- merchantability or fitness for a particular purpose. |
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| 25 | -- |
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| 26 | -- Xilinx products are not intended for use in life support appliances, |
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| 27 | -- devices, or systems. Use in such applications is expressly prohibited. |
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| 28 | -- |
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| 29 | -- Any modifications that are made to the source code are done at the user's |
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| 30 | -- sole risk and will be unsupported. |
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| 31 | -- |
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| 32 | -- This copyright and support notice must be retained as part of this |
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| 33 | -- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights |
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| 34 | -- reserved. |
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| 35 | ------------------------------------------------------------------- |
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| 36 | library IEEE; |
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| 37 | use IEEE.std_logic_1164.all; |
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| 38 | |
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| 39 | entity plbaddrpref is |
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| 40 | generic ( |
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| 41 | C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000"; |
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| 42 | C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF"; |
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| 43 | C_SPLB_DWIDTH : integer range 32 to 128 := 32; |
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| 44 | C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32 |
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| 45 | ); |
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| 46 | port ( |
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| 47 | addrpref : out std_logic_vector(20-1 downto 0); |
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| 48 | sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 49 | plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 50 | sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1); |
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| 51 | sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) |
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| 52 | ); |
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| 53 | end plbaddrpref; |
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| 54 | |
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| 55 | architecture behavior of plbaddrpref is |
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| 56 | |
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| 57 | signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 58 | |
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| 59 | begin |
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| 60 | addrpref <= C_BASEADDR(32-1 downto 12); |
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| 61 | |
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| 62 | ------------------------------------------------------------------------------- |
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| 63 | -- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb |
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| 64 | ------------------------------------------------------------------------------- |
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| 65 | GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate |
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| 66 | begin |
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| 67 | ----------------------------------------------------------------------- |
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| 68 | -- Map lower rd data to each quarter of the plb slave read bus |
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| 69 | ----------------------------------------------------------------------- |
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| 70 | sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); |
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| 71 | sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); |
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| 72 | sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); |
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| 73 | sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); |
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| 74 | end generate GEN_128_TO_32_SLAVE; |
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| 75 | |
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| 76 | ------------------------------------------------------------------------------- |
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| 77 | -- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb |
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| 78 | ------------------------------------------------------------------------------- |
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| 79 | GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate |
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| 80 | begin |
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| 81 | --------------------------------------------------------------------------- |
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| 82 | -- Map lower rd data to upper and lower halves of plb slave read bus |
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| 83 | --------------------------------------------------------------------------- |
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| 84 | sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); |
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| 85 | sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); |
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| 86 | end generate GEN_64_TO_32_SLAVE; |
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| 87 | |
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| 88 | ------------------------------------------------------------------------------- |
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| 89 | -- IPIF DWidth = PLB DWidth |
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| 90 | -- If IPIF Slave Data width is equal to the PLB Bus Data Width |
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| 91 | -- Then BE and Read Data Bus map directly to eachother. |
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| 92 | ------------------------------------------------------------------------------- |
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| 93 | GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate |
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| 94 | sl_rddbus_i <= sgsl_rddbus; |
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| 95 | end generate GEN_FOR_EQUAL_SLAVE; |
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| 96 | |
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| 97 | sl_rddbus <= sl_rddbus_i; |
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| 98 | sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1); |
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| 99 | |
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| 100 | end behavior; |
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| 101 | library IEEE; |
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| 102 | use IEEE.std_logic_1164.all; |
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| 103 | use work.conv_pkg.all; |
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| 104 | |
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| 105 | entity warp_timer_plbw is |
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| 106 | generic ( |
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| 107 | C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000"; |
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| 108 | C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF"; |
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| 109 | C_SPLB_DWIDTH: integer range 32 to 128 := 32; |
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| 110 | C_SPLB_NATIVE_DWIDTH: integer range 32 to 32 := 32; |
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| 111 | C_SPLB_AWIDTH: integer := 0; |
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| 112 | C_SPLB_P2P: integer := 0; |
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| 113 | C_SPLB_MID_WIDTH: integer := 0; |
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| 114 | C_SPLB_NUM_MASTERS: integer := 0; |
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| 115 | C_SPLB_SUPPORT_BURSTS: integer := 0; |
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| 116 | C_MEMMAP_TIMER0_TIMELEFT: integer := 0; |
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| 117 | C_MEMMAP_TIMER0_TIMELEFT_N_BITS: integer := 0; |
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| 118 | C_MEMMAP_TIMER0_TIMELEFT_BIN_PT: integer := 0; |
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| 119 | C_MEMMAP_TIMER1_TIMELEFT: integer := 0; |
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| 120 | C_MEMMAP_TIMER1_TIMELEFT_N_BITS: integer := 0; |
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| 121 | C_MEMMAP_TIMER1_TIMELEFT_BIN_PT: integer := 0; |
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| 122 | C_MEMMAP_TIMER2_TIMELEFT: integer := 0; |
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| 123 | C_MEMMAP_TIMER2_TIMELEFT_N_BITS: integer := 0; |
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| 124 | C_MEMMAP_TIMER2_TIMELEFT_BIN_PT: integer := 0; |
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| 125 | C_MEMMAP_TIMER3_TIMELEFT: integer := 0; |
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| 126 | C_MEMMAP_TIMER3_TIMELEFT_N_BITS: integer := 0; |
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| 127 | C_MEMMAP_TIMER3_TIMELEFT_BIN_PT: integer := 0; |
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| 128 | C_MEMMAP_TIMER_CONTROL_R: integer := 0; |
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| 129 | C_MEMMAP_TIMER_CONTROL_R_N_BITS: integer := 0; |
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| 130 | C_MEMMAP_TIMER_CONTROL_R_BIN_PT: integer := 0; |
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| 131 | C_MEMMAP_TIMER_STATUS: integer := 0; |
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| 132 | C_MEMMAP_TIMER_STATUS_N_BITS: integer := 0; |
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| 133 | C_MEMMAP_TIMER_STATUS_BIN_PT: integer := 0; |
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| 134 | C_MEMMAP_TIMER0_COUNTTO: integer := 0; |
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| 135 | C_MEMMAP_TIMER0_COUNTTO_N_BITS: integer := 0; |
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| 136 | C_MEMMAP_TIMER0_COUNTTO_BIN_PT: integer := 0; |
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| 137 | C_MEMMAP_TIMER1_COUNTTO: integer := 0; |
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| 138 | C_MEMMAP_TIMER1_COUNTTO_N_BITS: integer := 0; |
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| 139 | C_MEMMAP_TIMER1_COUNTTO_BIN_PT: integer := 0; |
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| 140 | C_MEMMAP_TIMER2_COUNTTO: integer := 0; |
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| 141 | C_MEMMAP_TIMER2_COUNTTO_N_BITS: integer := 0; |
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| 142 | C_MEMMAP_TIMER2_COUNTTO_BIN_PT: integer := 0; |
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| 143 | C_MEMMAP_TIMER3_COUNTTO: integer := 0; |
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| 144 | C_MEMMAP_TIMER3_COUNTTO_N_BITS: integer := 0; |
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| 145 | C_MEMMAP_TIMER3_COUNTTO_BIN_PT: integer := 0; |
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| 146 | C_MEMMAP_TIMER_CONTROL_W: integer := 0; |
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| 147 | C_MEMMAP_TIMER_CONTROL_W_N_BITS: integer := 0; |
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| 148 | C_MEMMAP_TIMER_CONTROL_W_BIN_PT: integer := 0 |
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| 149 | ); |
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| 150 | port ( |
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| 151 | ce: in std_logic; |
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| 152 | idlefordifs: in std_logic; |
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| 153 | plb_abus: in std_logic_vector(0 to 31); |
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| 154 | plb_pavalid: in std_logic; |
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| 155 | plb_rnw: in std_logic; |
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| 156 | plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 157 | splb_clk: in std_logic; |
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| 158 | splb_rst: in std_logic; |
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| 159 | sl_addrack: out std_logic; |
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| 160 | sl_rdcomp: out std_logic; |
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| 161 | sl_rddack: out std_logic; |
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| 162 | sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 163 | sl_wait: out std_logic; |
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| 164 | sl_wrcomp: out std_logic; |
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| 165 | sl_wrdack: out std_logic; |
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| 166 | timer0_active: out std_logic; |
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| 167 | timer1_active: out std_logic; |
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| 168 | timer2_active: out std_logic; |
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| 169 | timer3_active: out std_logic; |
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| 170 | timerexpire: out std_logic |
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| 171 | ); |
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| 172 | end warp_timer_plbw; |
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| 173 | |
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| 174 | architecture structural of warp_timer_plbw is |
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| 175 | signal ce_x0: std_logic; |
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| 176 | signal clk: std_logic; |
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| 177 | signal idlefordifs_x0: std_logic; |
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| 178 | signal plb_abus_x0: std_logic_vector(31 downto 0); |
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| 179 | signal plb_pavalid_x0: std_logic; |
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| 180 | signal plb_rnw_x0: std_logic; |
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| 181 | signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0); |
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| 182 | signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); |
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| 183 | signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0); |
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| 184 | signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0); |
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| 185 | signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); |
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| 186 | signal sl_addrack_x0: std_logic; |
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| 187 | signal sl_rdcomp_x0: std_logic; |
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| 188 | signal sl_rddack_x0: std_logic; |
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| 189 | signal sl_wait_x0: std_logic; |
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| 190 | signal sl_wrcomp_x0: std_logic; |
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| 191 | signal sl_wrdack_x0: std_logic; |
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| 192 | signal splb_rst_x0: std_logic; |
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| 193 | signal timer0_active_x0: std_logic; |
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| 194 | signal timer1_active_x0: std_logic; |
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| 195 | signal timer2_active_x0: std_logic; |
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| 196 | signal timer3_active_x0: std_logic; |
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| 197 | signal timerexpire_x0: std_logic; |
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| 198 | |
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| 199 | begin |
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| 200 | ce_x0 <= ce; |
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| 201 | idlefordifs_x0 <= idlefordifs; |
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| 202 | plb_abus_x0 <= plb_abus; |
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| 203 | plb_pavalid_x0 <= plb_pavalid; |
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| 204 | plb_rnw_x0 <= plb_rnw; |
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| 205 | plbaddrpref_plb_wrdbus_net <= plb_wrdbus; |
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| 206 | clk <= splb_clk; |
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| 207 | splb_rst_x0 <= splb_rst; |
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| 208 | sl_addrack <= sl_addrack_x0; |
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| 209 | sl_rdcomp <= sl_rdcomp_x0; |
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| 210 | sl_rddack <= sl_rddack_x0; |
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| 211 | sl_rddbus <= plbaddrpref_sl_rddbus_net; |
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| 212 | sl_wait <= sl_wait_x0; |
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| 213 | sl_wrcomp <= sl_wrcomp_x0; |
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| 214 | sl_wrdack <= sl_wrdack_x0; |
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| 215 | timer0_active <= timer0_active_x0; |
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| 216 | timer1_active <= timer1_active_x0; |
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| 217 | timer2_active <= timer2_active_x0; |
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| 218 | timer3_active <= timer3_active_x0; |
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| 219 | timerexpire <= timerexpire_x0; |
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| 220 | |
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| 221 | plbaddrpref_x0: entity work.plbaddrpref |
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| 222 | generic map ( |
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| 223 | C_BASEADDR => C_BASEADDR, |
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| 224 | C_HIGHADDR => C_HIGHADDR, |
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| 225 | C_SPLB_DWIDTH => C_SPLB_DWIDTH, |
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| 226 | C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH |
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| 227 | ) |
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| 228 | port map ( |
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| 229 | plb_wrdbus => plbaddrpref_plb_wrdbus_net, |
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| 230 | sgsl_rddbus => plbaddrpref_sgsl_rddbus_net, |
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| 231 | addrpref => plbaddrpref_addrpref_net, |
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| 232 | sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net, |
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| 233 | sl_rddbus => plbaddrpref_sl_rddbus_net |
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| 234 | ); |
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| 235 | |
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| 236 | sysgen_dut: entity work.warp_timer_cw |
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| 237 | port map ( |
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| 238 | ce => ce_x0, |
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| 239 | clk => clk, |
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| 240 | idlefordifs => idlefordifs_x0, |
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| 241 | plb_abus => plb_abus_x0, |
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| 242 | plb_pavalid => plb_pavalid_x0, |
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| 243 | plb_rnw => plb_rnw_x0, |
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| 244 | plb_wrdbus => plbaddrpref_sgplb_wrdbus_net, |
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| 245 | sg_plb_addrpref => plbaddrpref_addrpref_net, |
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| 246 | splb_rst => splb_rst_x0, |
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| 247 | sl_addrack => sl_addrack_x0, |
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| 248 | sl_rdcomp => sl_rdcomp_x0, |
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| 249 | sl_rddack => sl_rddack_x0, |
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| 250 | sl_rddbus => plbaddrpref_sgsl_rddbus_net, |
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| 251 | sl_wait => sl_wait_x0, |
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| 252 | sl_wrcomp => sl_wrcomp_x0, |
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| 253 | sl_wrdack => sl_wrdack_x0, |
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| 254 | timer0_active => timer0_active_x0, |
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| 255 | timer1_active => timer1_active_x0, |
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| 256 | timer2_active => timer2_active_x0, |
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| 257 | timer3_active => timer3_active_x0, |
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| 258 | timerexpire => timerexpire_x0 |
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| 259 | ); |
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| 260 | |
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| 261 | end structural; |
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